#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
99c7cc58 |
|
26-Jul-2022 |
Ye Li <ye.li@nxp.com> |
ddr: imx: Add i.MX9 DDR controller driver Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
c994d3d2 |
|
19-Mar-2021 |
haidong.zheng <haidong.zheng@nxp.com> |
imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
f3acb023 |
|
19-Jan-2020 |
Sherry Sun <sherry.sun@nxp.com> |
drivers: ddr: imx8mp: Add inline ECC feature support the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
825ab6b4 |
|
08-Aug-2019 |
Jacky Bai <ping.bai@nxp.com> |
driver: ddr: Refine the ddr init driver on imx8m Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
5e479ccd |
|
22-Apr-2019 |
Peng Fan <peng.fan@nxp.com> |
ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
e3963c09 |
|
20-Nov-2018 |
Peng Fan <peng.fan@nxp.com> |
drivers: ddr: introduce DDR driver for i.MX8M Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
|