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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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2cd80a8c |
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29-May-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Document internal machine/interrupt.h interface Every platform has to implement a standard set of interrupt interfaces that the kernel uses to interract with a machine's interrupt controller. Providing a single header file for each of these functions provides a single location to document their behavior.
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9a552d84 |
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22-May-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
RISC-V: Refactor IRQ handling to use PLIC Previously we only handled IRQs generated by the BBL running in machine mode via changes to supervisor interrupt pending (SIP) bits. Now that we need to support shared global interrupts through the PLIC we need to modify the way interrupts are processed. We additionally remove many DONT_TRANSLATE annotations on functions that the CParser is able to parse. Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
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c73d5178 |
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22-May-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
RISC-V: Add PLIC interface and HiFive driver We assume the PLIC is currently the only global interrupt controller that RISC-V platforms are going to use. Each platform may have a different programmers model for interracting with the hardware controller. We provide a common interface for PLIC drivers to implement that the kernel will use to manage IRQs. Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
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4b240066 |
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22-May-2019 |
Siwei Zhuang <siwei.zhuang@data61.csiro.au> |
RISC-V: Add kernel device functionalty - Create device untypeds for platform devices that can be passed to user space. - Create kernel device mapping for devices required by the kernel. Note that the current kernel device mapping is simply a 1GiB of page physical memory as that contains all devices for all RISC-V platforms that are currently supported.
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2865d6b6 |
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22-May-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
spike: Refactor into clearer subplatforms For now we keep the RISC-V platforms under the spike kernel platform name. Splitting the different platform definitions into different header files will help maintainability as we add different device layouts and kernel device drivers.
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