Rename the unhelpfully named mips_emul_lwc0() and mips_emul_swc0() to
mips_emul_ll() and mips_emul_sc(); make these static to mips_emul.c.

Whitespace nit.

branches: 1.117.4;
Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32

branches: 1.116.2;
Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.

port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@

Fix a tyop. Thankfully this #define was unused.

CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.

Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.

#define<tab>
Nuke trailing whitespace.

unifdef -U_LKM

Trailing whitespace

Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS

branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.

Rework cavium support in preparation for MULTIPROCESSOR support

mips_{l,s}d_a64 only valid for !O32

change #error to KASSERT

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.94.2;
deal with Ingenic XBurst CPUs

branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.

Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.

ras atomicvec is no more.

Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.

- add lsw_cpu_run function pointer to struct locoresw

Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}

Add a tiny bit of whitespace.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.

branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile

merge ktrace-lwp.

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.

Use #define<space> for consistency.

branches: 1.69.2;
Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.68.6; 1.68.14; 1.68.16;
Uppercase CPU, plural is CPUs.

Add some more MIPS vendor IDs.

No need to include opt_mips_cache.h here.

branches: 1.65.6;
Use named indices for RA, SR, MULLO, MULHI, and EPC in the
trapframe.

Define named constants for the trapframe register idices (they
are different from the normal register numbers). Use these names
in genassym.cf. (Wow, how ever did that test kernel boot before...)

Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

branches: 1.61.2;
Add a comment after an #endif to match up with an #ifdef.

make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.

branches: 1.58.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.57.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Reorder some function prototypes more logically.

Add Alchemy and SiByte company IDs (from oss.sgi.com).

Remove parameter names from function prototypes.

branches: 1.53.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

branches: 1.52.2;
Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.

Add mips_indexof() macro to make code for checking the cache index
easier to read.

mips1_ConfigCache() has gone.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).

rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)

add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

Introduce new MIPS1 direct mapped cache capacity detection logics.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

kill mips3_write_xcontext_upper

convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.

Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB. This allows best fit and will
support bigger caches.

un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded. no functional changes.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

branches: 1.36.2;
3rd argument of TBRPL() is not paddr_t but PTE.
XXX - mips3_TBRPL seems to be never called.

Add mips3_write_config().

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

branches: 1.33.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.

Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.

- Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.

Make MIPS1+MIPS3 compile again.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

CPU specific idle hook and VR idle routine.

Prototype stacktrace() and logstacktrace().

Make sure wbflush symbol treated as a C function call.

branches: 1.21.2; 1.21.4; 1.21.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.19.4;
Define C structures (struct kernframe, struct trapframe)
for kernel-to-user trapframe. Use C structs in genassym.cf.

* Add prototype for mips1_clean_tlb
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c

Protect defopt against -D_LKM

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.

branches: 1.14.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

Commit change missed during Decsystem 5100 chagnes:

prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.

Fix typo mips3_mips_switch_exit.

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

MachHitFlushDCache is gone.

More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.

Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.

Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.

DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].

lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code.

Rename mips CPU-family locore prefixes for case-consistency:
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).

* Move the declarations of mips locore functions from the pmax tree
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.

Define the conventional pmax locore entry-point names to be calls through
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.

Whitespace nit.

Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32

branches: 1.116.2;
Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.

port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@

Fix a tyop. Thankfully this #define was unused.

CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.

Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.

#define<tab>
Nuke trailing whitespace.

unifdef -U_LKM

Trailing whitespace

Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS

branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.

Rework cavium support in preparation for MULTIPROCESSOR support

mips_{l,s}d_a64 only valid for !O32

change #error to KASSERT

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.94.2;
deal with Ingenic XBurst CPUs

branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.

Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.

ras atomicvec is no more.

Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.

- add lsw_cpu_run function pointer to struct locoresw

Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}

Add a tiny bit of whitespace.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.

branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile

merge ktrace-lwp.

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.

Use #define<space> for consistency.

branches: 1.69.2;
Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.68.6; 1.68.14; 1.68.16;
Uppercase CPU, plural is CPUs.

Add some more MIPS vendor IDs.

No need to include opt_mips_cache.h here.

branches: 1.65.6;
Use named indices for RA, SR, MULLO, MULHI, and EPC in the
trapframe.

Define named constants for the trapframe register idices (they
are different from the normal register numbers). Use these names
in genassym.cf. (Wow, how ever did that test kernel boot before...)

Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

branches: 1.61.2;
Add a comment after an #endif to match up with an #ifdef.

make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.

branches: 1.58.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.57.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Reorder some function prototypes more logically.

Add Alchemy and SiByte company IDs (from oss.sgi.com).

Remove parameter names from function prototypes.

branches: 1.53.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

branches: 1.52.2;
Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.

Add mips_indexof() macro to make code for checking the cache index
easier to read.

mips1_ConfigCache() has gone.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).

rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)

add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

Introduce new MIPS1 direct mapped cache capacity detection logics.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

kill mips3_write_xcontext_upper

convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.

Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB. This allows best fit and will
support bigger caches.

un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded. no functional changes.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

branches: 1.36.2;
3rd argument of TBRPL() is not paddr_t but PTE.
XXX - mips3_TBRPL seems to be never called.

Add mips3_write_config().

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

branches: 1.33.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.

Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.

- Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.

Make MIPS1+MIPS3 compile again.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

CPU specific idle hook and VR idle routine.

Prototype stacktrace() and logstacktrace().

Make sure wbflush symbol treated as a C function call.

branches: 1.21.2; 1.21.4; 1.21.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.19.4;
Define C structures (struct kernframe, struct trapframe)
for kernel-to-user trapframe. Use C structs in genassym.cf.

* Add prototype for mips1_clean_tlb
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c

Protect defopt against -D_LKM

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.

branches: 1.14.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

Commit change missed during Decsystem 5100 chagnes:

prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.

Fix typo mips3_mips_switch_exit.

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

MachHitFlushDCache is gone.

More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.

Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.

Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.

DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].

lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code.

Rename mips CPU-family locore prefixes for case-consistency:
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).

* Move the declarations of mips locore functions from the pmax tree
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.

Define the conventional pmax locore entry-point names to be calls through
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.

Ensure the "memory" clobber is on inline assembly store operations

No binary change of note with this change in MALTA32

Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.

port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@

Fix a tyop. Thankfully this #define was unused.

CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.

Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.

#define<tab>
Nuke trailing whitespace.

unifdef -U_LKM

Trailing whitespace

Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS

branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.

Rework cavium support in preparation for MULTIPROCESSOR support

mips_{l,s}d_a64 only valid for !O32

change #error to KASSERT

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.94.2;
deal with Ingenic XBurst CPUs

branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.

Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.

ras atomicvec is no more.

Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.

- add lsw_cpu_run function pointer to struct locoresw

Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}

Add a tiny bit of whitespace.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.

branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile

merge ktrace-lwp.

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.

Use #define<space> for consistency.

branches: 1.69.2;
Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.68.6; 1.68.14; 1.68.16;
Uppercase CPU, plural is CPUs.

Add some more MIPS vendor IDs.

No need to include opt_mips_cache.h here.

branches: 1.65.6;
Use named indices for RA, SR, MULLO, MULHI, and EPC in the
trapframe.

Define named constants for the trapframe register idices (they
are different from the normal register numbers). Use these names
in genassym.cf. (Wow, how ever did that test kernel boot before...)

Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

branches: 1.61.2;
Add a comment after an #endif to match up with an #ifdef.

make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.

branches: 1.58.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.57.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Reorder some function prototypes more logically.

Add Alchemy and SiByte company IDs (from oss.sgi.com).

Remove parameter names from function prototypes.

branches: 1.53.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

branches: 1.52.2;
Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.

Add mips_indexof() macro to make code for checking the cache index
easier to read.

mips1_ConfigCache() has gone.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).

rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)

add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

Introduce new MIPS1 direct mapped cache capacity detection logics.

IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h

kill mips3_write_xcontext_upper

convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.

Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB. This allows best fit and will
support bigger caches.

un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded. no functional changes.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

branches: 1.36.2;
3rd argument of TBRPL() is not paddr_t but PTE.
XXX - mips3_TBRPL seems to be never called.

Add mips3_write_config().

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

branches: 1.33.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.

Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.

- Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.

Make MIPS1+MIPS3 compile again.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

CPU specific idle hook and VR idle routine.

Prototype stacktrace() and logstacktrace().

Make sure wbflush symbol treated as a C function call.

branches: 1.21.2; 1.21.4; 1.21.8;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.19.4;
Define C structures (struct kernframe, struct trapframe)
for kernel-to-user trapframe. Use C structs in genassym.cf.

* Add prototype for mips1_clean_tlb
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c

Protect defopt against -D_LKM

* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.

branches: 1.14.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.

* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.

Commit change missed during Decsystem 5100 chagnes:

prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.

Fix typo mips3_mips_switch_exit.

Final changes for configuring MIPS1 and MIPS3 in a single kernel.

* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.

* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.

* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if

* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).

Add `options MIPS3' to pmax/conf/GENERIC.

MachHitFlushDCache is gone.

More merged mips1/mips3 support:
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.

mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
mips1 TLB bit definitions.

mips/include/mips3_pte.h:
mips3 TLB bit definitions.

mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().

pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.

Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.

Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.

* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.

DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from
machine/locore.h.
From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline() [also cpu-dependent].

lint: prototype blkclr __P((caddr_t val, int size)). Used in pmap code.

Rename mips CPU-family locore prefixes for case-consistency:
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).

* Move the declarations of mips locore functions from the pmax tree
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.

Define the conventional pmax locore entry-point names to be calls through
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.

Invert the MIPS-I non-4kB page size check. The previous check doesn't
fail if both MIPS1 and MIPS3_PLUS are defined. Explictly check against
MIPS1.

port crash(8) to mips. (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@

Fix a tyop. Thankfully this #define was unused.

CP0 Config6 and Config7 aren't probeable. Adjust comments for these two.

Fix typo _MODULAR -> _MODULE. Hopefully this fixes the builds.

#define<tab>
Nuke trailing whitespace.

unifdef -U_LKM

Trailing whitespace

Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register. Probe correctly and save probed info somewhere we can
actually use it. Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

Note some hard-coded capabilties that can be probed.

XXX: Fix this and CPU table in mips/mips_machdep.c one day...

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

branches: 1.103.4;
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an infinite loop in ddb if something goes wrong.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.101.2;
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS

branches: 1.100.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix mips_fixup_zero_relative to have a third argument (ignored).
When reading COP0 EBASE, verify that the fixed bits have the right value.

Rework cavium support in preparation for MULTIPROCESSOR support

mips_{l,s}d_a64 only valid for !O32

change #error to KASSERT

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

branches: 1.94.2;
deal with Ingenic XBurst CPUs

branches: 1.93.2;
Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

branches: 1.92.2; 1.92.6;
Redo mips_fixup so that it can handle indirect loads and deal with loongson2
extra instructions.

Don't #include "opt_cputype.h" unless _KERNEL_OPT is #defined.

ras atomicvec is no more.

Fix printing of watch{lo,hi} and make mipsNN_watchlo_* use intptr_t so that
sign extention happens.

- add lsw_cpu_run function pointer to struct locoresw

Add prototypes for mipsNN_cp0_watch{lo,hi}_{read,write}

Add a tiny bit of whitespace.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

branches: 1.81.2; 1.81.4; 1.81.6;
Fix a couple old typos in comments.

branches: 1.80.2;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

branches: 1.78.20; 1.78.30; 1.78.36;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.77.10;
Move declaretions of _spl*() and _{clr,set}softintr() functions
(which are in mips/locore.S) into <mips/locore.h>
from various MD files.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.75.2; 1.75.4; 1.75.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.74.20;
Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

branches: 1.73.2; 1.73.4; 1.73.6;
__asm__ -> __asm
__const__ -> const
__inline__ -> inline
__volatile__ -> volatile

merge ktrace-lwp.

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.