locore.h revision 1.102
1/* $NetBSD: locore.h,v 1.102 2017/03/16 16:13:20 chs Exp $ */ 2 3/* 4 * This file should not be included by MI code!!! 5 */ 6 7/* 8 * Copyright 1996 The Board of Trustees of The Leland Stanford 9 * Junior University. All Rights Reserved. 10 * 11 * Permission to use, copy, modify, and distribute this 12 * software and its documentation for any purpose and without 13 * fee is hereby granted, provided that the above copyright 14 * notice appear in all copies. Stanford University 15 * makes no representations about the suitability of this 16 * software for any purpose. It is provided "as is" without 17 * express or implied warranty. 18 */ 19 20/* 21 * Jump table for MIPS CPU locore functions that are implemented 22 * differently on different generations, or instruction-level 23 * architecture (ISA) level, the Mips family. 24 * 25 * We currently provide support for MIPS I and MIPS III. 26 */ 27 28#ifndef _MIPS_LOCORE_H 29#define _MIPS_LOCORE_H 30 31#if !defined(_LKM) && defined(_KERNEL_OPT) 32#include "opt_cputype.h" 33#endif 34 35#ifndef __ASSEMBLER__ 36 37#include <sys/cpu.h> 38 39#include <mips/mutex.h> 40#include <mips/cpuregs.h> 41#include <mips/reg.h> 42 43#ifndef __BSD_PTENTRY_T__ 44#define __BSD_PTENTRY_T__ 45typedef uint32_t pt_entry_t; 46#define PRIxPTE PRIx32 47#endif 48 49#include <uvm/pmap/tlb.h> 50#endif /* !__ASSEMBLER__ */ 51 52#ifdef _KERNEL 53 54#if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 55/* Assume all CPU architectures are valid for LKM's and standlone progs */ 56#if !defined(__mips_n32) && !defined(__mips_n64) 57#define MIPS1 1 58#endif 59#define MIPS3 1 60#define MIPS4 1 61#if !defined(__mips_n32) && !defined(__mips_n64) 62#define MIPS32 1 63#define MIPS32R2 1 64#endif 65#define MIPS64 1 66#define MIPS64R2 1 67#endif /* _MODULAR || _LKM || _STANDALONE */ 68 69#if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 70#error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 71#endif 72 73/* Shortcut for MIPS3 or above defined */ 74#if defined(MIPS3) || defined(MIPS4) \ 75 || defined(MIPS32) || defined(MIPS32R2) \ 76 || defined(MIPS64) || defined(MIPS64R2) 77 78#define MIPS3_PLUS 1 79#if !defined(MIPS32) && !defined(MIPS32R2) 80#define MIPS3_64BIT 1 81#endif 82#if !defined(MIPS3) && !defined(MIPS4) 83#define MIPSNN 1 84#endif 85#if defined(MIPS32R2) || defined(MIPS64R2) 86#define MIPSNNR2 1 87#endif 88#else 89#undef MIPS3_PLUS 90#endif 91 92#if !defined(MIPS3_PLUS) && (ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_16KB_PAGE) > 0 93#error MIPS1 does not support non-4KB page sizes. 94#endif 95 96/* XXX some .S files look for MIPS3_PLUS */ 97#ifndef __ASSEMBLER__ 98 99/* XXX simonb 100 * Should the following be in a cpu_info type structure? 101 * And how many of these are per-cpu vs. per-system? (Ie, 102 * we can assume that all cpus have the same mmu-type, but 103 * maybe not that all cpus run at the same clock speed. 104 * Some SGI's apparently support R12k and R14k in the same 105 * box.) 106 */ 107struct mips_options { 108 const struct pridtab *mips_cpu; 109 110 u_int mips_cpu_arch; 111 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 112 u_int mips_cpu_flags; 113 u_int mips_num_tlb_entries; 114 mips_prid_t mips_cpu_id; 115 mips_prid_t mips_fpu_id; 116 bool mips_has_r4k_mmu; 117 bool mips_has_llsc; 118 u_int mips3_pg_shift; 119 u_int mips3_pg_cached; 120 u_int mips3_cca_devmem; 121#ifdef MIPS3_PLUS 122#ifndef __mips_o32 123 uint64_t mips3_xkphys_cached; 124#endif 125 uint64_t mips3_tlb_vpn_mask; 126 uint64_t mips3_tlb_pfn_mask; 127 uint32_t mips3_tlb_pg_mask; 128#endif 129}; 130 131#endif /* !__ASSEMBLER__ */ 132 133/* 134 * Macros to find the CPU architecture we're on at run-time, 135 * or if possible, at compile-time. 136 */ 137 138#define CPU_ARCH_MIPSx 0 /* XXX unknown */ 139#define CPU_ARCH_MIPS1 (1 << 0) 140#define CPU_ARCH_MIPS2 (1 << 1) 141#define CPU_ARCH_MIPS3 (1 << 2) 142#define CPU_ARCH_MIPS4 (1 << 3) 143#define CPU_ARCH_MIPS5 (1 << 4) 144#define CPU_ARCH_MIPS32 (1 << 5) 145#define CPU_ARCH_MIPS64 (1 << 6) 146#define CPU_ARCH_MIPS32R2 (1 << 7) 147#define CPU_ARCH_MIPS64R2 (1 << 8) 148 149#define CPU_MIPS_R4K_MMU 0x0001 150#define CPU_MIPS_NO_LLSC 0x0002 151#define CPU_MIPS_CAUSE_IV 0x0004 152#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 153#define CPU_MIPS_CACHED_CCA_MASK 0x0070 154#define CPU_MIPS_CACHED_CCA_SHIFT 4 155#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 156#define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 157#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 158#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 159#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 160#define CPU_MIPS_NO_LLADDR 0x1000 161#define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 162#define CPU_MIPS_LOONGSON2 0x4000 163#define MIPS_NOT_SUPP 0x8000 164#define CPU_MIPS_HAVE_DSP 0x10000 165 166#endif /* !_LOCORE */ 167 168#if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 169 170#if defined(MIPS1) 171 172# define CPUISMIPS3 0 173# define CPUIS64BITS 0 174# define CPUISMIPS32 0 175# define CPUISMIPS32R2 0 176# define CPUISMIPS64 0 177# define CPUISMIPS64R2 0 178# define CPUISMIPSNN 0 179# define CPUISMIPSNNR2 0 180# define MIPS_HAS_R4K_MMU 0 181# define MIPS_HAS_CLOCK 0 182# define MIPS_HAS_LLSC 0 183# define MIPS_HAS_LLADDR 0 184# define MIPS_HAS_DSP 0 185# define MIPS_HAS_LMMI 0 186 187#elif defined(MIPS3) || defined(MIPS4) 188 189# define CPUISMIPS3 1 190# define CPUIS64BITS 1 191# define CPUISMIPS32 0 192# define CPUISMIPS32R2 0 193# define CPUISMIPS64 0 194# define CPUISMIPS64R2 0 195# define CPUISMIPSNN 0 196# define CPUISMIPSNNR2 0 197# define MIPS_HAS_R4K_MMU 1 198# define MIPS_HAS_CLOCK 1 199# if defined(_LOCORE) 200# if !defined(MIPS3_4100) 201# define MIPS_HAS_LLSC 1 202# else 203# define MIPS_HAS_LLSC 0 204# endif 205# else /* _LOCORE */ 206# define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 207# endif /* _LOCORE */ 208# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 209# define MIPS_HAS_DSP 0 210# if defined(MIPS3_LOONGSON2) 211# define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 212# else 213# define MIPS_HAS_LMMI 0 214# endif 215#elif defined(MIPS32) 216 217# define CPUISMIPS3 1 218# define CPUIS64BITS 0 219# define CPUISMIPS32 1 220# define CPUISMIPS32R2 0 221# define CPUISMIPS64 0 222# define CPUISMIPS64R2 0 223# define CPUISMIPSNN 1 224# define CPUISMIPSNNR2 0 225# define MIPS_HAS_R4K_MMU 1 226# define MIPS_HAS_CLOCK 1 227# define MIPS_HAS_LLSC 1 228# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 229# define MIPS_HAS_DSP 0 230# define MIPS_HAS_LMMI 0 231 232#elif defined(MIPS32R2) 233 234# define CPUISMIPS3 1 235# define CPUIS64BITS 0 236# define CPUISMIPS32 0 237# define CPUISMIPS32R2 1 238# define CPUISMIPS64 0 239# define CPUISMIPS64R2 0 240# define CPUISMIPSNN 1 241# define CPUISMIPSNNR2 1 242# define MIPS_HAS_R4K_MMU 1 243# define MIPS_HAS_CLOCK 1 244# define MIPS_HAS_LLSC 1 245# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 246# define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 247# define MIPS_HAS_LMMI 0 248 249#elif defined(MIPS64) 250 251# define CPUISMIPS3 1 252# define CPUIS64BITS 1 253# define CPUISMIPS32 0 254# define CPUISMIPS32R2 0 255# define CPUISMIPS64 1 256# define CPUISMIPS64R2 0 257# define CPUISMIPSNN 1 258# define CPUISMIPSNNR2 0 259# define MIPS_HAS_R4K_MMU 1 260# define MIPS_HAS_CLOCK 1 261# define MIPS_HAS_LLSC 1 262# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 263# define MIPS_HAS_DSP 0 264# define MIPS_HAS_LMMI 0 265 266#elif defined(MIPS64R2) 267 268# define CPUISMIPS3 1 269# define CPUIS64BITS 1 270# define CPUISMIPS32 0 271# define CPUISMIPS32R2 0 272# define CPUISMIPS64 0 273# define CPUISMIPS64R2 1 274# define CPUISMIPSNN 1 275# define CPUISMIPSNNR2 1 276# define MIPS_HAS_R4K_MMU 1 277# define MIPS_HAS_CLOCK 1 278# define MIPS_HAS_LLSC 1 279# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 280# define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 281# define MIPS_HAS_LMMI 0 282 283#endif 284 285#else /* run-time test */ 286 287#ifdef MIPS1 288#define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 289#define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 290#else 291#define MIPS_HAS_R4K_MMU 1 292#if !defined(MIPS3_4100) 293#define MIPS_HAS_LLSC 1 294#else 295#define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 296#endif 297#endif 298#define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 299#define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 300 301/* This test is ... rather bogus */ 302#define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 303 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 304 305/* And these aren't much better while the previous test exists as is... */ 306#define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 307#define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 308#define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 309#define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 310#define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 311#define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 312#define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 313#define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 314 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 315 316#define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 317 318#endif /* run-time test */ 319 320#ifndef __ASSEMBLER__ 321 322struct tlbmask; 323struct trapframe; 324 325void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *); 326void ast(void); 327 328void mips_fpu_trap(vaddr_t, struct trapframe *); 329void mips_fpu_intr(vaddr_t, struct trapframe *); 330 331vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool); 332void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *); 333 334void mips_emul_fp(uint32_t, struct trapframe *, uint32_t); 335void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t); 336 337void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t); 338void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t); 339void mips_emul_special(uint32_t, struct trapframe *, uint32_t); 340void mips_emul_special3(uint32_t, struct trapframe *, uint32_t); 341 342void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t); 343void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t); 344void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t); 345void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t); 346 347void mips_emul_lb(uint32_t, struct trapframe *, uint32_t); 348void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t); 349void mips_emul_lh(uint32_t, struct trapframe *, uint32_t); 350void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t); 351void mips_emul_lw(uint32_t, struct trapframe *, uint32_t); 352void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t); 353void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t); 354#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 355void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t); 356void mips_emul_ld(uint32_t, struct trapframe *, uint32_t); 357void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t); 358void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t); 359#endif 360void mips_emul_sb(uint32_t, struct trapframe *, uint32_t); 361void mips_emul_sh(uint32_t, struct trapframe *, uint32_t); 362void mips_emul_sw(uint32_t, struct trapframe *, uint32_t); 363void mips_emul_swl(uint32_t, struct trapframe *, uint32_t); 364void mips_emul_swr(uint32_t, struct trapframe *, uint32_t); 365#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64) 366void mips_emul_sd(uint32_t, struct trapframe *, uint32_t); 367void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t); 368void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t); 369#endif 370 371uint32_t mips_cp0_cause_read(void); 372void mips_cp0_cause_write(uint32_t); 373uint32_t mips_cp0_status_read(void); 374void mips_cp0_status_write(uint32_t); 375 376void softint_process(uint32_t); 377void softint_fast_dispatch(struct lwp *, int); 378 379/* 380 * Convert an address to an offset used in a MIPS jump instruction. The offset 381 * contains the low 28 bits (allowing a jump to anywhere within the same 256MB 382 * segment of address space) of the address but since mips instructions are 383 * always on a 4 byte boundary the low 2 bits are always zero so the 28 bits 384 * get shifted right by 2 bits leaving us with a 26 bit result. To make the 385 * offset, we shift left to clear the upper four bits and then right by 6. 386 */ 387#define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6) 388typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2], void *); 389struct mips_jump_fixup_info { 390 uint32_t jfi_stub; 391 uint32_t jfi_real; 392}; 393 394void fixup_splcalls(void); /* splstubs.c */ 395bool mips_fixup_exceptions(mips_fixup_callback_t, void *); 396bool mips_fixup_zero_relative(int32_t, uint32_t [2], void *); 397intptr_t 398 mips_fixup_addr(const uint32_t *); 399void mips_fixup_stubs(uint32_t *, uint32_t *); 400 401/* 402 * Define these stubs... 403 */ 404void mips_cpu_switch_resume(struct lwp *); 405void wbflush(void); 406 407#ifdef MIPS1 408void mips1_tlb_invalidate_all(void); 409 410uint32_t tx3900_cp0_config_read(void); 411#endif 412 413#ifdef MIPS3_PLUS 414uint32_t mips3_cp0_compare_read(void); 415void mips3_cp0_compare_write(uint32_t); 416 417uint32_t mips3_cp0_config_read(void); 418void mips3_cp0_config_write(uint32_t); 419 420#ifdef MIPSNN 421uint32_t mipsNN_cp0_config1_read(void); 422void mipsNN_cp0_config1_write(uint32_t); 423uint32_t mipsNN_cp0_config2_read(void); 424uint32_t mipsNN_cp0_config3_read(void); 425uint32_t mipsNN_cp0_config4_read(void); 426uint32_t mipsNN_cp0_config5_read(void); 427uint32_t mipsNN_cp0_config6_read(void); 428uint32_t mipsNN_cp0_config7_read(void); 429 430intptr_t mipsNN_cp0_watchlo_read(u_int); 431void mipsNN_cp0_watchlo_write(u_int, intptr_t); 432uint32_t mipsNN_cp0_watchhi_read(u_int); 433void mipsNN_cp0_watchhi_write(u_int, uint32_t); 434 435int32_t mipsNN_cp0_ebase_read(void); 436void mipsNN_cp0_ebase_write(int32_t); 437 438#ifdef MIPSNNR2 439void mipsNN_cp0_hwrena_write(uint32_t); 440void mipsNN_cp0_userlocal_write(void *); 441#endif 442#endif /* MIPSNN */ 443 444uint32_t mips3_cp0_count_read(void); 445void mips3_cp0_count_write(uint32_t); 446 447uint32_t mips3_cp0_wired_read(void); 448void mips3_cp0_wired_write(uint32_t); 449void mips3_cp0_pg_mask_write(uint32_t); 450 451#endif /* MIPS3_PLUS */ 452 453/* 64-bit address space accessor for n32, n64 ABI */ 454/* 32-bit address space accessor for o32 ABI */ 455static inline uint8_t mips_lbu(register_t addr) __unused; 456static inline void mips_sb(register_t addr, uint8_t val) __unused; 457static inline uint16_t mips_lhu(register_t addr) __unused; 458static inline void mips_sh(register_t addr, uint16_t val) __unused; 459static inline uint32_t mips_lwu(register_t addr) __unused; 460static inline void mips_sw(register_t addr, uint32_t val) __unused; 461#ifdef MIPS3_64BIT 462#if defined(__mips_o32) 463uint64_t mips3_ld(register_t addr); 464void mips3_sd(register_t addr, uint64_t val); 465#else 466static inline uint64_t mips3_ld(register_t addr) __unused; 467static inline void mips3_sd(register_t addr, uint64_t val) __unused; 468#endif 469#endif 470 471static inline uint8_t 472mips_lbu(register_t addr) 473{ 474 uint8_t rv; 475#if defined(__mips_n32) 476 __asm volatile("lbu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 477#else 478 rv = *(const volatile uint8_t *)addr; 479#endif 480 return rv; 481} 482 483static inline uint16_t 484mips_lhu(register_t addr) 485{ 486 uint16_t rv; 487#if defined(__mips_n32) 488 __asm volatile("lhu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 489#else 490 rv = *(const volatile uint16_t *)addr; 491#endif 492 return rv; 493} 494 495static inline uint32_t 496mips_lwu(register_t addr) 497{ 498 uint32_t rv; 499#if defined(__mips_n32) 500 __asm volatile("lwu\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 501#else 502 rv = *(const volatile uint32_t *)addr; 503#endif 504 return (rv); 505} 506 507#if defined(MIPS3_64BIT) && !defined(__mips_o32) 508static inline uint64_t 509mips3_ld(register_t addr) 510{ 511 uint64_t rv; 512#if defined(__mips_n32) 513 __asm volatile("ld\t%0, 0(%1)" : "=r"(rv) : "d"(addr)); 514#elif defined(_LP64) 515 rv = *(const volatile uint64_t *)addr; 516#else 517#error unknown ABI 518#endif 519 return (rv); 520} 521#endif /* MIPS3_64BIT && !__mips_o32 */ 522 523static inline void 524mips_sb(register_t addr, uint8_t val) 525{ 526#if defined(__mips_n32) 527 __asm volatile("sb\t%1, 0(%0)" :: "d"(addr), "r"(val)); 528#else 529 *(volatile uint8_t *)addr = val; 530#endif 531} 532 533static inline void 534mips_sh(register_t addr, uint16_t val) 535{ 536#if defined(__mips_n32) 537 __asm volatile("sh\t%1, 0(%0)" :: "d"(addr), "r"(val)); 538#else 539 *(volatile uint16_t *)addr = val; 540#endif 541} 542 543static inline void 544mips_sw(register_t addr, uint32_t val) 545{ 546#if defined(__mips_n32) 547 __asm volatile("sw\t%1, 0(%0)" :: "d"(addr), "r"(val)); 548#else 549 *(volatile uint32_t *)addr = val; 550#endif 551} 552 553#if defined(MIPS3_64BIT) && !defined(__mips_o32) 554static inline void 555mips3_sd(register_t addr, uint64_t val) 556{ 557#if defined(__mips_n32) 558 __asm volatile("sd\t%1, 0(%0)" :: "d"(addr), "r"(val)); 559#else 560 *(volatile uint64_t *)addr = val; 561#endif 562} 563#endif /* MIPS3_64BIT && !__mips_o32 */ 564 565/* 566 * A vector with an entry for each mips-ISA-level dependent 567 * locore function, and macros which jump through it. 568 */ 569typedef struct { 570 void (*ljv_cpu_switch_resume)(struct lwp *); 571 intptr_t ljv_lwp_trampoline; 572 void (*ljv_wbflush)(void); 573 tlb_asid_t (*ljv_tlb_get_asid)(void); 574 void (*ljv_tlb_set_asid)(tlb_asid_t pid); 575 void (*ljv_tlb_invalidate_asids)(tlb_asid_t, tlb_asid_t); 576 void (*ljv_tlb_invalidate_addr)(vaddr_t, tlb_asid_t); 577 void (*ljv_tlb_invalidate_globals)(void); 578 void (*ljv_tlb_invalidate_all)(void); 579 u_int (*ljv_tlb_record_asids)(u_long *, tlb_asid_t); 580 int (*ljv_tlb_update_addr)(vaddr_t, tlb_asid_t, pt_entry_t, bool); 581 void (*ljv_tlb_read_entry)(size_t, struct tlbmask *); 582 void (*ljv_tlb_write_entry)(size_t, const struct tlbmask *); 583} mips_locore_jumpvec_t; 584 585typedef struct { 586 u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int); 587 u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long); 588 int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *); 589 int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *); 590 void (*lav_mutex_enter)(kmutex_t *); 591 void (*lav_mutex_exit)(kmutex_t *); 592 void (*lav_mutex_spin_enter)(kmutex_t *); 593 void (*lav_mutex_spin_exit)(kmutex_t *); 594} mips_locore_atomicvec_t; 595 596void mips_set_wbflush(void (*)(void)); 597void mips_wait_idle(void); 598 599void stacktrace(void); 600void logstacktrace(void); 601 602struct cpu_info; 603struct splsw; 604 605struct locoresw { 606 void (*lsw_wbflush)(void); 607 void (*lsw_cpu_idle)(void); 608 int (*lsw_send_ipi)(struct cpu_info *, int); 609 void (*lsw_cpu_offline_md)(void); 610 void (*lsw_cpu_init)(struct cpu_info *); 611 void (*lsw_cpu_run)(struct cpu_info *); 612 int (*lsw_bus_error)(unsigned int); 613}; 614 615struct mips_vmfreelist { 616 paddr_t fl_start; 617 paddr_t fl_end; 618 int fl_freelist; 619}; 620 621struct cpu_info * 622 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 623 cpuid_t); 624void cpu_attach_common(device_t, struct cpu_info *); 625void cpu_startup_common(void); 626 627#ifdef MULTIPROCESSOR 628void cpu_hatch(struct cpu_info *ci); 629void cpu_trampoline(void); 630void cpu_halt(void); 631void cpu_halt_others(void); 632void cpu_pause(struct reg *); 633void cpu_pause_others(void); 634void cpu_resume(cpuid_t); 635void cpu_resume_others(void); 636bool cpu_is_paused(cpuid_t); 637void cpu_debug_dump(void); 638 639extern kcpuset_t *cpus_running; 640extern kcpuset_t *cpus_hatched; 641extern kcpuset_t *cpus_paused; 642extern kcpuset_t *cpus_resumed; 643extern kcpuset_t *cpus_halted; 644#endif 645 646/* copy.S */ 647int32_t kfetch_32(volatile uint32_t *, uint32_t); 648int8_t ufetch_int8(void *); 649int16_t ufetch_int16(void *); 650int32_t ufetch_int32(void *); 651uint8_t ufetch_uint8(void *); 652uint16_t ufetch_uint16(void *); 653uint32_t ufetch_uint32(void *); 654int8_t ufetch_int8_intrsafe(void *); 655int16_t ufetch_int16_intrsafe(void *); 656int32_t ufetch_int32_intrsafe(void *); 657uint8_t ufetch_uint8_intrsafe(void *); 658uint16_t ufetch_uint16_intrsafe(void *); 659uint32_t ufetch_uint32_intrsafe(void *); 660#ifdef _LP64 661int64_t ufetch_int64(void *); 662uint64_t ufetch_uint64(void *); 663int64_t ufetch_int64_intrsafe(void *); 664uint64_t ufetch_uint64_intrsafe(void *); 665#endif 666char ufetch_char(void *); 667short ufetch_short(void *); 668int ufetch_int(void *); 669long ufetch_long(void *); 670char ufetch_char_intrsafe(void *); 671short ufetch_short_intrsafe(void *); 672int ufetch_int_intrsafe(void *); 673long ufetch_long_intrsafe(void *); 674 675u_char ufetch_uchar(void *); 676u_short ufetch_ushort(void *); 677u_int ufetch_uint(void *); 678u_long ufetch_ulong(void *); 679u_char ufetch_uchar_intrsafe(void *); 680u_short ufetch_ushort_intrsafe(void *); 681u_int ufetch_uint_intrsafe(void *); 682u_long ufetch_ulong_intrsafe(void *); 683void *ufetch_ptr(void *); 684 685int ustore_int8(void *, int8_t); 686int ustore_int16(void *, int16_t); 687int ustore_int32(void *, int32_t); 688int ustore_uint8(void *, uint8_t); 689int ustore_uint16(void *, uint16_t); 690int ustore_uint32(void *, uint32_t); 691int ustore_int8_intrsafe(void *, int8_t); 692int ustore_int16_intrsafe(void *, int16_t); 693int ustore_int32_intrsafe(void *, int32_t); 694int ustore_uint8_intrsafe(void *, uint8_t); 695int ustore_uint16_intrsafe(void *, uint16_t); 696int ustore_uint32_intrsafe(void *, uint32_t); 697#ifdef _LP64 698int ustore_int64(void *, int64_t); 699int ustore_uint64(void *, uint64_t); 700int ustore_int64_intrsafe(void *, int64_t); 701int ustore_uint64_intrsafe(void *, uint64_t); 702#endif 703int ustore_char(void *, char); 704int ustore_char_intrsafe(void *, char); 705int ustore_short(void *, short); 706int ustore_short_intrsafe(void *, short); 707int ustore_int(void *, int); 708int ustore_int_intrsafe(void *, int); 709int ustore_long(void *, long); 710int ustore_long_intrsafe(void *, long); 711int ustore_uchar(void *, u_char); 712int ustore_uchar_intrsafe(void *, u_char); 713int ustore_ushort(void *, u_short); 714int ustore_ushort_intrsafe(void *, u_short); 715int ustore_uint(void *, u_int); 716int ustore_uint_intrsafe(void *, u_int); 717int ustore_ulong(void *, u_long); 718int ustore_ulong_intrsafe(void *, u_long); 719int ustore_ptr(void *, void *); 720int ustore_ptr_intrsafe(void *, void *); 721 722int ustore_uint32_isync(void *, uint32_t); 723 724/* trap.c */ 725void netintr(void); 726int kdbpeek(vaddr_t); 727 728/* mips_dsp.c */ 729void dsp_init(void); 730void dsp_discard(lwp_t *); 731void dsp_load(void); 732void dsp_save(lwp_t *); 733bool dsp_used_p(const lwp_t *); 734extern const pcu_ops_t mips_dsp_ops; 735 736/* mips_fpu.c */ 737void fpu_init(void); 738void fpu_discard(lwp_t *); 739void fpu_load(void); 740void fpu_save(lwp_t *); 741bool fpu_used_p(const lwp_t *); 742extern const pcu_ops_t mips_fpu_ops; 743 744/* mips_machdep.c */ 745void dumpsys(void); 746int savectx(struct pcb *); 747void cpu_identify(device_t); 748 749/* locore*.S */ 750int badaddr(void *, size_t); 751int badaddr64(uint64_t, size_t); 752 753/* vm_machdep.c */ 754int ioaccess(vaddr_t, paddr_t, vsize_t); 755int iounaccess(vaddr_t, vsize_t); 756 757/* 758 * The "active" locore-function vector, and 759 */ 760extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec; 761 762extern mips_locore_atomicvec_t mips_locore_atomicvec; 763extern mips_locore_jumpvec_t mips_locore_jumpvec; 764extern struct locoresw mips_locoresw; 765 766extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 767extern struct mips_options mips_options; 768 769struct splsw; 770struct mips_vmfreelist; 771struct phys_ram_seg; 772 773void mips64r2_vector_init(const struct splsw *); 774void mips_vector_init(const struct splsw *, bool); 775void mips_init_msgbuf(void); 776void mips_init_lwp0_uarea(void); 777void mips_page_physload(vaddr_t, vaddr_t, 778 const struct phys_ram_seg *, size_t, 779 const struct mips_vmfreelist *, size_t); 780 781 782/* 783 * CPU identification, from PRID register. 784 */ 785#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 786#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 787 788/* pre-MIPS32/64 */ 789#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 790#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 791#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 792 793/* MIPS32/64 */ 794#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 795#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 796#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 797#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 798#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 799#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 800#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 801#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 802#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 803#define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */ 804#define MIPS_PRID_CID_LSI 0x08 /* LSI */ 805 /* 0x09 unannounced */ 806 /* 0x0a unannounced */ 807#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 808#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */ 809#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ 810#define MIPS_PRID_CID_INGENIC 0xe1 811#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 812 813#ifdef _KERNEL 814/* 815 * Global variables used to communicate CPU type, and parameters 816 * such as cache size, from locore to higher-level code (e.g., pmap). 817 */ 818void mips_pagecopy(register_t dst, register_t src); 819void mips_pagezero(register_t dst); 820 821#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG 822void mips_machdep_cache_config(void); 823#endif 824 825/* 826 * trapframe argument passed to trap() 827 */ 828 829#if 0 830#define TF_AST 0 /* really zero */ 831#define TF_V0 _R_V0 832#define TF_V1 _R_V1 833#define TF_A0 _R_A0 834#define TF_A1 _R_A1 835#define TF_A2 _R_A2 836#define TF_A3 _R_A3 837#define TF_T0 _R_T0 838#define TF_T1 _R_T1 839#define TF_T2 _R_T2 840#define TF_T3 _R_T3 841 842#if defined(__mips_n32) || defined(__mips_n64) 843#define TF_A4 _R_A4 844#define TF_A5 _R_A5 845#define TF_A6 _R_A6 846#define TF_A7 _R_A7 847#else 848#define TF_T4 _R_T4 849#define TF_T5 _R_T5 850#define TF_T6 _R_T6 851#define TF_T7 _R_T7 852#endif /* __mips_n32 || __mips_n64 */ 853 854#define TF_TA0 _R_TA0 855#define TF_TA1 _R_TA1 856#define TF_TA2 _R_TA2 857#define TF_TA3 _R_TA3 858 859#define TF_T8 _R_T8 860#define TF_T9 _R_T9 861 862#define TF_RA _R_RA 863#define TF_SR _R_SR 864#define TF_MULLO _R_MULLO 865#define TF_MULHI _R_MULLO 866#define TF_EPC _R_PC /* may be changed by trap() call */ 867 868#define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t)) 869#endif 870 871struct trapframe { 872 struct reg tf_registers; 873#define tf_regs tf_registers.r_regs 874 uint32_t tf_ppl; /* previous priority level */ 875 mips_reg_t tf_pad; /* for 8 byte aligned */ 876}; 877 878CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0); 879 880/* 881 * Stack frame for kernel traps. four args passed in registers. 882 * A trapframe is pointed to by the 5th arg, and a dummy sixth argument 883 * is used to avoid alignment problems 884 */ 885 886struct kernframe { 887#if defined(__mips_o32) || defined(__mips_o64) 888 register_t cf_args[4 + 1]; 889#if defined(__mips_o32) 890 register_t cf_pad; /* (for 8 byte alignment) */ 891#endif 892#endif 893#if defined(__mips_n32) || defined(__mips_n64) 894 register_t cf_pad[2]; /* for 16 byte alignment */ 895#endif 896 register_t cf_sp; 897 register_t cf_ra; 898 struct trapframe cf_frame; 899}; 900 901CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0); 902 903/* 904 * PRocessor IDentity TABle 905 */ 906 907struct pridtab { 908 int cpu_cid; 909 int cpu_pid; 910 int cpu_rev; /* -1 == wildcard */ 911 int cpu_copts; /* -1 == wildcard */ 912 int cpu_isa; /* -1 == probed (mips32/mips64) */ 913 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 914 int cpu_flags; 915 u_int cpu_cp0flags; /* presence of some cp0 regs */ 916 u_int cpu_cidflags; /* company-specific flags */ 917 const char *cpu_name; 918}; 919 920/* 921 * bitfield defines for cpu_cp0flags 922 */ 923#define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 924#define MIPS_CP0FL_ECC __BIT(1) 925#define MIPS_CP0FL_CACHE_ERR __BIT(2) 926#define MIPS_CP0FL_EIRR __BIT(3) 927#define MIPS_CP0FL_EIMR __BIT(4) 928#define MIPS_CP0FL_EBASE __BIT(5) 929#define MIPS_CP0FL_CONFIG __BIT(6) 930#define MIPS_CP0FL_CONFIG1 __BIT(7) 931#define MIPS_CP0FL_CONFIG2 __BIT(8) 932#define MIPS_CP0FL_CONFIG3 __BIT(9) 933#define MIPS_CP0FL_CONFIG4 __BIT(10) 934#define MIPS_CP0FL_CONFIG5 __BIT(11) 935#define MIPS_CP0FL_CONFIG6 __BIT(12) 936#define MIPS_CP0FL_CONFIG7 __BIT(13) 937#define MIPS_CP0FL_USERLOCAL __BIT(14) 938#define MIPS_CP0FL_HWRENA __BIT(15) 939 940/* 941 * cpu_cidflags defines, by company 942 */ 943/* 944 * RMI company-specific cpu_cidflags 945 */ 946#define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 947# define CIDFL_RMI_TYPE_XLR 0 948# define CIDFL_RMI_TYPE_XLS 1 949# define CIDFL_RMI_TYPE_XLP 2 950#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 951# define MIPS_CIDFL_RMI_THREADS_SHIFT 3 952#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 953# define MIPS_CIDFL_RMI_CORES_SHIFT 7 954# define LOG2_1 0 955# define LOG2_2 1 956# define LOG2_4 2 957# define LOG2_8 3 958# define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 959 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 960 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 961# define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 962 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 963 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 964# define MIPS_CIDFL_RMI_NCORES(cidfl) \ 965 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 966 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 967#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 968# define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 969# define RMI_L2SZ_256KB 0 970# define RMI_L2SZ_512KB 1 971# define RMI_L2SZ_1MB 2 972# define RMI_L2SZ_2MB 3 973# define RMI_L2SZ_4MB 4 974# define MIPS_CIDFL_RMI_L2(l2sz) \ 975 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 976# define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 977 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 978 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 979#endif /* !__ASSEMBLER__ */ 980#endif /* _KERNEL */ 981 982#endif /* _MIPS_LOCORE_H */ 983