x86 Move VA_SIGN_POS/NEG to machine/pte.h.

It's used by pl[1-4]_pi, also defined in machine/pte.h, and used in
libkvm without pmap_private.h.

x86: Forbid using x86/pte.h directly; use machine/pte.h.

machine/pte.h already used outside sys/arch, so let's make it the
primary thing and make sure to use x86/pte.h only as a subroutine.

amd64/pte.h, i386/pte.h: Need sys/stdint.h for uintN_t.

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Switch to the new PTE naming. The old naming is now unused, remove it.

branches: 1.31.10;
Start replacing the x86 PTE bits.

Introduce a new set of PTE bits, with a different naming convention.

PG_V -> PTE_P /* Present */
PG_RW -> PTE_W /* Write */
PG_u -> PTE_U /* User */
PG_WT -> PTE_PWT /* Write-Through */
PG_N -> PTE_PCD /* Cache-Disable */
PG_U -> PTE_A /* Accessed */
PG_M -> PTE_D /* Dirty */
PG_PAT -> PTE_PAT /* PAT on 4KB Pages */
PG_PS -> PTE_PS /* Large Page Size */
PG_G -> PTE_G /* Global Translation */
PG_AVAIL1 -> PTE_AVL1 /* Ignored by Hardware */
PG_AVAIL2 -> PTE_AVL2 /* Ignored by Hardware */
PG_AVAIL3 -> PTE_AVL3 /* Ignored by Hardware */
PG_LGPAT -> PTE_LGPAT /* PAT on Large Pages */
PG_NX -> PTE_NX /* No Execute */

Until now we were using "PG_BIT". The "BIT" part of the naming did not
follow the x86 naming convention in the spec, and was very confusing. We
don't want the "PG_" part of it either, because UVM has similar flags
(ie PG_BUSY).

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Style, and remove useless comments.

branches: 1.27.56;
udpate license clauses on my code to match the new-style BSD licenses.
based on diff that rmind@ sent me.

no functional change with this commit.

branches: 1.26.2; 1.26.4;
Update the comment for PG_PS when used with PAE.

Add ULL suffix to PG_NX when it is defined.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.

Fix typos in PAE comment.

branches: 1.21.2;
Fixes regarding paddr_t/pd_entry_t types in MD x86 code, exposed by PAE:

- NBPD_* macros are set to the types that better match their architecture
(UL for i386 and amd64, ULL for i386 PAE) - will revisit when paddr_t is
set to 64 bits for i386 non-PAE.

- type fixes in printf/printk messages (Use PRIxPADDR when printing paddr_t
values, instead of %lx - paddr_t/pd_entry_t being 64 bits with PAE)

- remove casts that are no more needed now that Xen2 support has been dropped

Some fixes are from jmorse@ patches for PAE.

Compile + tested for i386 GENERIC and XEN3 kernels. Only compile tested for
amd64.

Reviewed by bouyer@.

See also http://mail-index.netbsd.org/tech-kern/2010/02/22/msg007373.html

branches: 1.20.2;
Fix spelling in comments, s/extention/extension/.

No Execute bit is available in PAE-paging mode.
However to use it, NXE bit in EFER register must be set.

branches: 1.18.2;
Fix a comment.

branches: 1.17.6; 1.17.10; 1.17.18;
Merge the bouyer-xeni386 branch. This brings in PAE support to NetBSD xeni386
(domU only). PAE support is enabled by 'options PAE', see the new XEN3PAE_DOMU
and INSTALL_XEN3PAE_DOMU kernel config files.

See the comments in arch/i386/include/{pte.h,pmap.h} to see how it works.
In short, we still handle it as a 2-level MMU, with the second level page
directory being 4 pages in size. pmap switching is done by switching the
L2 pages in the L3 entries, instead of loading %cr3. This is almost required
by Xen, which handle the last L2 page (the one mapping 0xc0000000 - 0xffffffff)
in a very special way. But this approach should also work for native PAE
support if ever supported (in fact, the pmap should almost suport native
PAE, what's missing is bootstrap code in locore.S).

branches: 1.16.2; 1.16.8;
merge yamt-x86pmap branch.

- reduce differences between amd64 and i386. notably, share pmap.c
between them. it makes several i386 pmap improvements available to
amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option. always use large pages if available.
also, make it work on amd64.

branches: 1.15.30; 1.15.48; 1.15.50; 1.15.52; 1.15.54;
u_intN_t -> uintN_t

branches: 1.14.16;
add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.13.2;
Use PAGE_SIZE rather than NBPG.

branches: 1.12.2;
Define PG_LGFRAME, which is the page frame mask for large (4MB) pages.

branches: 1.11.14;
Allow userland access to pd_entry_t and pt_entry_t, like the old pte.h
used to do. Also, RCS ID police.

add the i386 MD portions for UVM.

LOCORE -> _LOCORE

KERNEL -> _KERNEL

new RCS ID format.

Nuke dirty().

Eliminate struct pte and struct pde.

branches: 1.4.2; 1.4.4;
Fold in most of the magnum vm changes.

branches: 1.3.4;
Re-entrancy protection.

add rcsids to everything and clean up headers

branches: 1.1.1;
Initial revision

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Switch to the new PTE naming. The old naming is now unused, remove it.

branches: 1.31.10;
Start replacing the x86 PTE bits.

Introduce a new set of PTE bits, with a different naming convention.

PG_V -> PTE_P /* Present */
PG_RW -> PTE_W /* Write */
PG_u -> PTE_U /* User */
PG_WT -> PTE_PWT /* Write-Through */
PG_N -> PTE_PCD /* Cache-Disable */
PG_U -> PTE_A /* Accessed */
PG_M -> PTE_D /* Dirty */
PG_PAT -> PTE_PAT /* PAT on 4KB Pages */
PG_PS -> PTE_PS /* Large Page Size */
PG_G -> PTE_G /* Global Translation */
PG_AVAIL1 -> PTE_AVL1 /* Ignored by Hardware */
PG_AVAIL2 -> PTE_AVL2 /* Ignored by Hardware */
PG_AVAIL3 -> PTE_AVL3 /* Ignored by Hardware */
PG_LGPAT -> PTE_LGPAT /* PAT on Large Pages */
PG_NX -> PTE_NX /* No Execute */

Until now we were using "PG_BIT". The "BIT" part of the naming did not
follow the x86 naming convention in the spec, and was very confusing. We
don't want the "PG_" part of it either, because UVM has similar flags
(ie PG_BUSY).

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Style, and remove useless comments.

branches: 1.27.56;
udpate license clauses on my code to match the new-style BSD licenses.
based on diff that rmind@ sent me.

no functional change with this commit.

branches: 1.26.2; 1.26.4;
Update the comment for PG_PS when used with PAE.

Add ULL suffix to PG_NX when it is defined.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.

Fix typos in PAE comment.

branches: 1.21.2;
Fixes regarding paddr_t/pd_entry_t types in MD x86 code, exposed by PAE:

- NBPD_* macros are set to the types that better match their architecture
(UL for i386 and amd64, ULL for i386 PAE) - will revisit when paddr_t is
set to 64 bits for i386 non-PAE.

- type fixes in printf/printk messages (Use PRIxPADDR when printing paddr_t
values, instead of %lx - paddr_t/pd_entry_t being 64 bits with PAE)

- remove casts that are no more needed now that Xen2 support has been dropped

Some fixes are from jmorse@ patches for PAE.

Compile + tested for i386 GENERIC and XEN3 kernels. Only compile tested for
amd64.

Reviewed by bouyer@.

See also http://mail-index.netbsd.org/tech-kern/2010/02/22/msg007373.html

branches: 1.20.2;
Fix spelling in comments, s/extention/extension/.

No Execute bit is available in PAE-paging mode.
However to use it, NXE bit in EFER register must be set.

branches: 1.18.2;
Fix a comment.

branches: 1.17.6; 1.17.10; 1.17.18;
Merge the bouyer-xeni386 branch. This brings in PAE support to NetBSD xeni386
(domU only). PAE support is enabled by 'options PAE', see the new XEN3PAE_DOMU
and INSTALL_XEN3PAE_DOMU kernel config files.

See the comments in arch/i386/include/{pte.h,pmap.h} to see how it works.
In short, we still handle it as a 2-level MMU, with the second level page
directory being 4 pages in size. pmap switching is done by switching the
L2 pages in the L3 entries, instead of loading %cr3. This is almost required
by Xen, which handle the last L2 page (the one mapping 0xc0000000 - 0xffffffff)
in a very special way. But this approach should also work for native PAE
support if ever supported (in fact, the pmap should almost suport native
PAE, what's missing is bootstrap code in locore.S).

branches: 1.16.2; 1.16.8;
merge yamt-x86pmap branch.

- reduce differences between amd64 and i386. notably, share pmap.c
between them. it makes several i386 pmap improvements available to
amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option. always use large pages if available.
also, make it work on amd64.

branches: 1.15.30; 1.15.48; 1.15.50; 1.15.52; 1.15.54;
u_intN_t -> uintN_t

branches: 1.14.16;
add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.13.2;
Use PAGE_SIZE rather than NBPG.

branches: 1.12.2;
Define PG_LGFRAME, which is the page frame mask for large (4MB) pages.

branches: 1.11.14;
Allow userland access to pd_entry_t and pt_entry_t, like the old pte.h
used to do. Also, RCS ID police.

add the i386 MD portions for UVM.

LOCORE -> _LOCORE

KERNEL -> _KERNEL

new RCS ID format.

Nuke dirty().

Eliminate struct pte and struct pde.

branches: 1.4.2; 1.4.4;
Fold in most of the magnum vm changes.

branches: 1.3.4;
Re-entrancy protection.

add rcsids to everything and clean up headers

branches: 1.1.1;
Initial revision

Switch to the new PTE naming. The old naming is now unused, remove it.

Start replacing the x86 PTE bits.

Introduce a new set of PTE bits, with a different naming convention.

PG_V -> PTE_P /* Present */
PG_RW -> PTE_W /* Write */
PG_u -> PTE_U /* User */
PG_WT -> PTE_PWT /* Write-Through */
PG_N -> PTE_PCD /* Cache-Disable */
PG_U -> PTE_A /* Accessed */
PG_M -> PTE_D /* Dirty */
PG_PAT -> PTE_PAT /* PAT on 4KB Pages */
PG_PS -> PTE_PS /* Large Page Size */
PG_G -> PTE_G /* Global Translation */
PG_AVAIL1 -> PTE_AVL1 /* Ignored by Hardware */
PG_AVAIL2 -> PTE_AVL2 /* Ignored by Hardware */
PG_AVAIL3 -> PTE_AVL3 /* Ignored by Hardware */
PG_LGPAT -> PTE_LGPAT /* PAT on Large Pages */
PG_NX -> PTE_NX /* No Execute */

Until now we were using "PG_BIT". The "BIT" part of the naming did not
follow the x86 naming convention in the spec, and was very confusing. We
don't want the "PG_" part of it either, because UVM has similar flags
(ie PG_BUSY).

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Style, and remove useless comments.

branches: 1.27.56;
udpate license clauses on my code to match the new-style BSD licenses.
based on diff that rmind@ sent me.

no functional change with this commit.

branches: 1.26.2; 1.26.4;
Update the comment for PG_PS when used with PAE.

Add ULL suffix to PG_NX when it is defined.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.

Fix typos in PAE comment.

branches: 1.21.2;
Fixes regarding paddr_t/pd_entry_t types in MD x86 code, exposed by PAE:

- NBPD_* macros are set to the types that better match their architecture
(UL for i386 and amd64, ULL for i386 PAE) - will revisit when paddr_t is
set to 64 bits for i386 non-PAE.

- type fixes in printf/printk messages (Use PRIxPADDR when printing paddr_t
values, instead of %lx - paddr_t/pd_entry_t being 64 bits with PAE)

- remove casts that are no more needed now that Xen2 support has been dropped

Some fixes are from jmorse@ patches for PAE.

Compile + tested for i386 GENERIC and XEN3 kernels. Only compile tested for
amd64.

Reviewed by bouyer@.

See also http://mail-index.netbsd.org/tech-kern/2010/02/22/msg007373.html

branches: 1.20.2;
Fix spelling in comments, s/extention/extension/.

No Execute bit is available in PAE-paging mode.
However to use it, NXE bit in EFER register must be set.

branches: 1.18.2;
Fix a comment.

branches: 1.17.6; 1.17.10; 1.17.18;
Merge the bouyer-xeni386 branch. This brings in PAE support to NetBSD xeni386
(domU only). PAE support is enabled by 'options PAE', see the new XEN3PAE_DOMU
and INSTALL_XEN3PAE_DOMU kernel config files.

See the comments in arch/i386/include/{pte.h,pmap.h} to see how it works.
In short, we still handle it as a 2-level MMU, with the second level page
directory being 4 pages in size. pmap switching is done by switching the
L2 pages in the L3 entries, instead of loading %cr3. This is almost required
by Xen, which handle the last L2 page (the one mapping 0xc0000000 - 0xffffffff)
in a very special way. But this approach should also work for native PAE
support if ever supported (in fact, the pmap should almost suport native
PAE, what's missing is bootstrap code in locore.S).

branches: 1.16.2; 1.16.8;
merge yamt-x86pmap branch.

- reduce differences between amd64 and i386. notably, share pmap.c
between them. it makes several i386 pmap improvements available to
amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option. always use large pages if available.
also, make it work on amd64.

branches: 1.15.30; 1.15.48; 1.15.50; 1.15.52; 1.15.54;
u_intN_t -> uintN_t

branches: 1.14.16;
add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.13.2;
Use PAGE_SIZE rather than NBPG.

branches: 1.12.2;
Define PG_LGFRAME, which is the page frame mask for large (4MB) pages.

branches: 1.11.14;
Allow userland access to pd_entry_t and pt_entry_t, like the old pte.h
used to do. Also, RCS ID police.

add the i386 MD portions for UVM.

LOCORE -> _LOCORE

KERNEL -> _KERNEL

new RCS ID format.

Nuke dirty().

Eliminate struct pte and struct pde.

branches: 1.4.2; 1.4.4;
Fold in most of the magnum vm changes.

branches: 1.3.4;
Re-entrancy protection.

add rcsids to everything and clean up headers

branches: 1.1.1;
Initial revision

Start replacing the x86 PTE bits.

Introduce a new set of PTE bits, with a different naming convention.

PG_V -> PTE_P /* Present */
PG_RW -> PTE_W /* Write */
PG_u -> PTE_U /* User */
PG_WT -> PTE_PWT /* Write-Through */
PG_N -> PTE_PCD /* Cache-Disable */
PG_U -> PTE_A /* Accessed */
PG_M -> PTE_D /* Dirty */
PG_PAT -> PTE_PAT /* PAT on 4KB Pages */
PG_PS -> PTE_PS /* Large Page Size */
PG_G -> PTE_G /* Global Translation */
PG_AVAIL1 -> PTE_AVL1 /* Ignored by Hardware */
PG_AVAIL2 -> PTE_AVL2 /* Ignored by Hardware */
PG_AVAIL3 -> PTE_AVL3 /* Ignored by Hardware */
PG_LGPAT -> PTE_LGPAT /* PAT on Large Pages */
PG_NX -> PTE_NX /* No Execute */

Until now we were using "PG_BIT". The "BIT" part of the naming did not
follow the x86 naming convention in the spec, and was very confusing. We
don't want the "PG_" part of it either, because UVM has similar flags
(ie PG_BUSY).

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Style, and remove useless comments.

udpate license clauses on my code to match the new-style BSD licenses.
based on diff that rmind@ sent me.

no functional change with this commit.

branches: 1.26.2; 1.26.4;
Update the comment for PG_PS when used with PAE.

Add ULL suffix to PG_NX when it is defined.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.

Fix typos in PAE comment.

branches: 1.21.2;
Fixes regarding paddr_t/pd_entry_t types in MD x86 code, exposed by PAE:

- NBPD_* macros are set to the types that better match their architecture
(UL for i386 and amd64, ULL for i386 PAE) - will revisit when paddr_t is
set to 64 bits for i386 non-PAE.

- type fixes in printf/printk messages (Use PRIxPADDR when printing paddr_t
values, instead of %lx - paddr_t/pd_entry_t being 64 bits with PAE)

- remove casts that are no more needed now that Xen2 support has been dropped

Some fixes are from jmorse@ patches for PAE.

Compile + tested for i386 GENERIC and XEN3 kernels. Only compile tested for
amd64.

Reviewed by bouyer@.

See also http://mail-index.netbsd.org/tech-kern/2010/02/22/msg007373.html

branches: 1.20.2;
Fix spelling in comments, s/extention/extension/.

No Execute bit is available in PAE-paging mode.
However to use it, NXE bit in EFER register must be set.

branches: 1.18.2;
Fix a comment.

branches: 1.17.6; 1.17.10; 1.17.18;
Merge the bouyer-xeni386 branch. This brings in PAE support to NetBSD xeni386
(domU only). PAE support is enabled by 'options PAE', see the new XEN3PAE_DOMU
and INSTALL_XEN3PAE_DOMU kernel config files.

See the comments in arch/i386/include/{pte.h,pmap.h} to see how it works.
In short, we still handle it as a 2-level MMU, with the second level page
directory being 4 pages in size. pmap switching is done by switching the
L2 pages in the L3 entries, instead of loading %cr3. This is almost required
by Xen, which handle the last L2 page (the one mapping 0xc0000000 - 0xffffffff)
in a very special way. But this approach should also work for native PAE
support if ever supported (in fact, the pmap should almost suport native
PAE, what's missing is bootstrap code in locore.S).

branches: 1.16.2; 1.16.8;
merge yamt-x86pmap branch.

- reduce differences between amd64 and i386. notably, share pmap.c
between them. it makes several i386 pmap improvements available to
amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option. always use large pages if available.
also, make it work on amd64.

branches: 1.15.30; 1.15.48; 1.15.50; 1.15.52; 1.15.54;
u_intN_t -> uintN_t

branches: 1.14.16;
add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default. the changes
fall into two basic catagories:

- pmap and trap-handler changes. these are all MD:
= alpha: we already track per-page execute permission with the (software)
PG_EXEC bit, so just have the trap handler pay attention to it.
= i386: use a new GDT segment for %cs for processes that have no
executable mappings above a certain threshold (currently the
bottom of the stack). track per-page execute permission with
the last unused PTE bit.
= powerpc/ibm4xx: just use the hardware exec bit.
= powerpc/oea: we already track per-page exec bits, but the hardware only
implements non-exec mappings at the segment level. so track the
number of executable mappings in each segment and turn on the no-exec
segment bit iff the count is 0. adjust the trap handler to deal.
= sparc (sun4m): fix our use of the hardware protection bits.
fix the trap handler to recognize text faults.
= sparc64: split the existing unified TSB into data and instruction TSBs,
and only load TTEs into the appropriate TSB(s) for the permissions.
fix the trap handler to check for execute permission.
= not yet implemented: amd64, hppa, sh5

- changes in all the emulations that put a signal trampoline on the stack.
instead, we now put the trampoline into a uvm_aobj and map that into
the process separately.

originally from openbsd, adapted for netbsd by me.

branches: 1.13.2;
Use PAGE_SIZE rather than NBPG.

branches: 1.12.2;
Define PG_LGFRAME, which is the page frame mask for large (4MB) pages.

branches: 1.11.14;
Allow userland access to pd_entry_t and pt_entry_t, like the old pte.h
used to do. Also, RCS ID police.

add the i386 MD portions for UVM.

LOCORE -> _LOCORE

KERNEL -> _KERNEL

new RCS ID format.

Nuke dirty().

Eliminate struct pte and struct pde.

branches: 1.4.2; 1.4.4;
Fold in most of the magnum vm changes.

branches: 1.3.4;
Re-entrancy protection.

add rcsids to everything and clean up headers

branches: 1.1.1;
Initial revision