malloc(9) -> kmem(9)

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.34.30;
kill sprintf.

Unused variable police

branches: 1.32.2;
defer evcnt attachment correctly.

branches: 1.31.2;
move evcnt_attach_dynamic() calls later to avoid assertions.

Remove irqframe and replace with identical trapframe.

branches: 1.29.2; 1.29.8;
#include <sys/bus.h> instead of <machine/bus.h>.

Correct __HAVE_FAST_SOFTINTRS typos, use only __HAVE_FAST_SOFTINTS.

branches: 1.27.2; 1.27.4;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.26.22;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.25.6; 1.25.8; 1.25.10;
Cleanup softint lossage.

branches: 1.24.24; 1.24.28; 1.24.34; 1.24.42;
s/heirarchy/hierarchy/, from Zafer.

branches: 1.23.20; 1.23.22;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Follow up the type change of i80200_extirq_dispatch which now takes
an irqframe* and not a clockframe* as argument.

branches: 1.20.16;
__KERNEL_RCSID()

branches: 1.19.2;
Rename IPL_IMP -> IPL_VM.

Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

Don't need to frob CPSR in _splraise().

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

#if 0 the stray interrupt messages -- we tend to get them "a lot"
during normal activity on some IOP310-based designs.

Report stray interrupts.

branches: 1.12.2; 1.12.4;
Fix typo in last (luckily, search/replace makes the same typo everywhere).

iq80310_do_pending -> iq80310_do_soft, to accurately describe what's
actually going on there.

Processing pending interrupts before reenabling external interrupts in splx().

branches: 1.9.4;
* The Npwr only has 5 interrupt sources, all in XINT3, so don't bother
reading XINT0 (which isn't even implemented by the CPLD on Npwr).
* Adjust the mask of valid IRQ bits for the Npwr.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

Some prototype cleanup.

branches: 1.6.2;
- Don't enable FIQs; nothing uses them (yet).
- Steer i80200 PMU and BCU interrupts to IRQ# (for lack of a better
place, at the moment).
- Disable all interrupts other than external-IRQ# in the i80200 ICU;
we don't deal with any of the others, yet.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.4.2; 1.4.4;
When we read the interrupt status bits, mask it with the shadow copy
of the "currently enabled interrupts" -- the CPLD appears to light
up the status bit even if it doesn't cause the CPU IRQ line to be
asserted.

We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

* Pass the IRQ number to stray_irqhandler() and display it in
the panic message.
* Mask off undefined bits from the XINT3 and XINT0 registers in the CPLD.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

kill sprintf.

Unused variable police

branches: 1.32.2;
defer evcnt attachment correctly.

branches: 1.31.2;
move evcnt_attach_dynamic() calls later to avoid assertions.

Remove irqframe and replace with identical trapframe.

branches: 1.29.2; 1.29.8;
#include <sys/bus.h> instead of <machine/bus.h>.

Correct __HAVE_FAST_SOFTINTRS typos, use only __HAVE_FAST_SOFTINTS.

branches: 1.27.2; 1.27.4;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.26.22;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.25.6; 1.25.8; 1.25.10;
Cleanup softint lossage.

branches: 1.24.24; 1.24.28; 1.24.34; 1.24.42;
s/heirarchy/hierarchy/, from Zafer.

branches: 1.23.20; 1.23.22;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Follow up the type change of i80200_extirq_dispatch which now takes
an irqframe* and not a clockframe* as argument.

branches: 1.20.16;
__KERNEL_RCSID()

branches: 1.19.2;
Rename IPL_IMP -> IPL_VM.

Clean up some bad interaction between the spl inlining stuff and
strict-prototypes.

Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.

Don't need to frob CPSR in _splraise().

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

#if 0 the stray interrupt messages -- we tend to get them "a lot"
during normal activity on some IOP310-based designs.

Report stray interrupts.

branches: 1.12.2; 1.12.4;
Fix typo in last (luckily, search/replace makes the same typo everywhere).

iq80310_do_pending -> iq80310_do_soft, to accurately describe what's
actually going on there.

Processing pending interrupts before reenabling external interrupts in splx().

branches: 1.9.4;
* The Npwr only has 5 interrupt sources, all in XINT3, so don't bother
reading XINT0 (which isn't even implemented by the CPLD on Npwr).
* Adjust the mask of valid IRQ bits for the Npwr.

New interrupt framework for NetBSD/evbarm, and accompanying new
interrupt code for the IQ80310 board support package.

XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.

Some prototype cleanup.

branches: 1.6.2;
- Don't enable FIQs; nothing uses them (yet).
- Steer i80200 PMU and BCU interrupts to IRQ# (for lack of a better
place, at the moment).
- Disable all interrupts other than external-IRQ# in the i80200 ICU;
we don't deal with any of the others, yet.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.4.2; 1.4.4;
When we read the interrupt status bits, mask it with the shadow copy
of the "currently enabled interrupts" -- the CPLD appears to light
up the status bit even if it doesn't cause the CPU IRQ line to be
asserted.

We were already cheating w/ CPLD register access, so cheat all the
way and use pointer derefs rather than bus_space to access them.

* Pass the IRQ number to stray_irqhandler() and display it in
the panic message.
* Mask off undefined bits from the XINT3 and XINT0 registers in the CPLD.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.