iq80310_intr.c revision 1.20 
1/*	$NetBSD: iq80310_intr.c,v 1.20 2003/07/15 00:25:02 lukem Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include <sys/cdefs.h>
39__KERNEL_RCSID(0, "$NetBSD: iq80310_intr.c,v 1.20 2003/07/15 00:25:02 lukem Exp $");
40
41#ifndef EVBARM_SPL_NOINLINE
42#define	EVBARM_SPL_NOINLINE
43#endif
44
45/*
46 * Interrupt support for the Intel IQ80310.
47 */
48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/malloc.h>
52
53#include <uvm/uvm_extern.h>
54
55#include <machine/bus.h>
56#include <machine/intr.h>
57
58#include <arm/cpufunc.h>
59
60#include <arm/xscale/i80200reg.h>
61#include <arm/xscale/i80200var.h>
62
63#include <evbarm/iq80310/iq80310reg.h>
64#include <evbarm/iq80310/iq80310var.h>
65#include <evbarm/iq80310/obiovar.h>
66
67/* Interrupt handler queues. */
68struct intrq intrq[NIRQ];
69
70/* Interrupts to mask at each level. */
71int iq80310_imask[NIPL];
72
73/* Current interrupt priority level. */
74__volatile int current_spl_level;
75
76/* Interrupts pending. */
77__volatile int iq80310_ipending;
78
79/* Software copy of the IRQs we have enabled. */
80uint32_t intr_enabled;
81
82/*
83 * Map a software interrupt queue index (at the top of the word, and
84 * highest priority softintr is encountered first in an ffs()).
85 */
86#define	SI_TO_IRQBIT(si)	(1U << (31 - (si)))
87
88/*
89 * Map a software interrupt queue to an interrupt priority level.
90 */
91static const int si_to_ipl[SI_NQUEUES] = {
92	IPL_SOFT,		/* SI_SOFT */
93	IPL_SOFTCLOCK,		/* SI_SOFTCLOCK */
94	IPL_SOFTNET,		/* SI_SOFTNET */
95	IPL_SOFTSERIAL,		/* SI_SOFTSERIAL */
96};
97
98void	iq80310_intr_dispatch(struct clockframe *frame);
99
100static __inline uint32_t
101iq80310_intstat_read(void)
102{
103	uint32_t intstat;
104
105	intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f;
106#if defined(IRQ_READ_XINT0)
107	if (IRQ_READ_XINT0)
108		intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5;
109#endif
110
111	/* XXX Why do we have to mask off? */
112	return (intstat & intr_enabled);
113}
114
115static __inline void
116iq80310_set_intrmask(void)
117{
118	uint32_t disabled;
119
120	intr_enabled |= IRQ_BITS_ALWAYS_ON;
121
122	/* The XINT_MASK register sets a bit to *disable*. */
123	disabled = (~intr_enabled) & IRQ_BITS;
124
125	CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f);
126}
127
128static __inline void
129iq80310_enable_irq(int irq)
130{
131
132	intr_enabled |= (1U << irq);
133	iq80310_set_intrmask();
134}
135
136static __inline void
137iq80310_disable_irq(int irq)
138{
139
140	intr_enabled &= ~(1U << irq);
141	iq80310_set_intrmask();
142}
143
144/*
145 * NOTE: This routine must be called with interrupts disabled in the CPSR.
146 */
147static void
148iq80310_intr_calculate_masks(void)
149{
150	struct intrq *iq;
151	struct intrhand *ih;
152	int irq, ipl;
153
154	/* First, figure out which IPLs each IRQ has. */
155	for (irq = 0; irq < NIRQ; irq++) {
156		int levels = 0;
157		iq = &intrq[irq];
158		iq80310_disable_irq(irq);
159		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
160		     ih = TAILQ_NEXT(ih, ih_list))
161			levels |= (1U << ih->ih_ipl);
162		iq->iq_levels = levels;
163	}
164
165	/* Next, figure out which IRQs are used by each IPL. */
166	for (ipl = 0; ipl < NIPL; ipl++) {
167		int irqs = 0;
168		for (irq = 0; irq < NIRQ; irq++) {
169			if (intrq[irq].iq_levels & (1U << ipl))
170				irqs |= (1U << irq);
171		}
172		iq80310_imask[ipl] = irqs;
173	}
174
175	iq80310_imask[IPL_NONE] = 0;
176
177	/*
178	 * Initialize the soft interrupt masks to block themselves.
179	 */
180	iq80310_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
181	iq80310_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
182	iq80310_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
183	iq80310_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
184
185	/*
186	 * splsoftclock() is the only interface that users of the
187	 * generic software interrupt facility have to block their
188	 * soft intrs, so splsoftclock() must also block IPL_SOFT.
189	 */
190	iq80310_imask[IPL_SOFTCLOCK] |= iq80310_imask[IPL_SOFT];
191
192	/*
193	 * splsoftnet() must also block splsoftclock(), since we don't
194	 * want timer-driven network events to occur while we're
195	 * processing incoming packets.
196	 */
197	iq80310_imask[IPL_SOFTNET] |= iq80310_imask[IPL_SOFTCLOCK];
198
199	/*
200	 * Enforce a heirarchy that gives "slow" device (or devices with
201	 * limited input buffer space/"real-time" requirements) a better
202	 * chance at not dropping data.
203	 */
204	iq80310_imask[IPL_BIO] |= iq80310_imask[IPL_SOFTNET];
205	iq80310_imask[IPL_NET] |= iq80310_imask[IPL_BIO];
206	iq80310_imask[IPL_SOFTSERIAL] |= iq80310_imask[IPL_NET];
207	iq80310_imask[IPL_TTY] |= iq80310_imask[IPL_SOFTSERIAL];
208
209	/*
210	 * splvm() blocks all interrupts that use the kernel memory
211	 * allocation facilities.
212	 */
213	iq80310_imask[IPL_VM] |= iq80310_imask[IPL_TTY];
214
215	/*
216	 * Audio devices are not allowed to perform memory allocation
217	 * in their interrupt routines, and they have fairly "real-time"
218	 * requirements, so give them a high interrupt priority.
219	 */
220	iq80310_imask[IPL_AUDIO] |= iq80310_imask[IPL_VM];
221
222	/*
223	 * splclock() must block anything that uses the scheduler.
224	 */
225	iq80310_imask[IPL_CLOCK] |= iq80310_imask[IPL_AUDIO];
226
227	/*
228	 * No separate statclock on the IQ80310.
229	 */
230	iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK];
231
232	/*
233	 * splhigh() must block "everything".
234	 */
235	iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK];
236
237	/*
238	 * XXX We need serial drivers to run at the absolute highest priority
239	 * in order to avoid overruns, so serial > high.
240	 */
241	iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH];
242
243	/*
244	 * Now compute which IRQs must be blocked when servicing any
245	 * given IRQ.
246	 */
247	for (irq = 0; irq < NIRQ; irq++) {
248		int irqs = (1U << irq);
249		iq = &intrq[irq];
250		if (TAILQ_FIRST(&iq->iq_list) != NULL)
251			iq80310_enable_irq(irq);
252		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
253		     ih = TAILQ_NEXT(ih, ih_list))
254			irqs |= iq80310_imask[ih->ih_ipl];
255		iq->iq_mask = irqs;
256	}
257}
258
259void
260iq80310_do_soft(void)
261{
262	static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
263	int new, oldirqstate;
264
265	if (__cpu_simple_lock_try(&processing) == 0)
266		return;
267
268	new = current_spl_level;
269
270	oldirqstate = disable_interrupts(I32_bit);
271
272#define	DO_SOFTINT(si)							\
273	if ((iq80310_ipending & ~new) & SI_TO_IRQBIT(si)) {		\
274		iq80310_ipending &= ~SI_TO_IRQBIT(si);			\
275		current_spl_level |= iq80310_imask[si_to_ipl[(si)]];	\
276		restore_interrupts(oldirqstate);			\
277		softintr_dispatch(si);					\
278		oldirqstate = disable_interrupts(I32_bit);		\
279		current_spl_level = new;				\
280	}
281
282	DO_SOFTINT(SI_SOFTSERIAL);
283	DO_SOFTINT(SI_SOFTNET);
284	DO_SOFTINT(SI_SOFTCLOCK);
285	DO_SOFTINT(SI_SOFT);
286
287	__cpu_simple_unlock(&processing);
288
289	restore_interrupts(oldirqstate);
290}
291
292int
293_splraise(int ipl)
294{
295
296	return (iq80310_splraise(ipl));
297}
298
299__inline void
300splx(int new)
301{
302
303	return (iq80310_splx(new));
304}
305
306int
307_spllower(int ipl)
308{
309
310	return (iq80310_spllower(ipl));
311}
312
313void
314_setsoftintr(int si)
315{
316	int oldirqstate;
317
318	oldirqstate = disable_interrupts(I32_bit);
319	iq80310_ipending |= SI_TO_IRQBIT(si);
320	restore_interrupts(oldirqstate);
321
322	/* Process unmasked pending soft interrupts. */
323	if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level)
324		iq80310_do_soft();
325}
326
327void
328iq80310_intr_init(void)
329{
330	struct intrq *iq;
331	int i;
332
333	/*
334	 * The Secondary PCI interrupts INTA, INTB, and INTC
335	 * area always enabled, since they cannot be masked
336	 * in the CPLD.
337	 */
338	intr_enabled |= IRQ_BITS_ALWAYS_ON;
339
340	for (i = 0; i < NIRQ; i++) {
341		iq = &intrq[i];
342		TAILQ_INIT(&iq->iq_list);
343
344		sprintf(iq->iq_name, "irq %d", i);
345		evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
346		    NULL, "iq80310", iq->iq_name);
347	}
348
349	iq80310_intr_calculate_masks();
350
351	/* Enable external interrupts on the i80200. */
352	i80200_extirq_dispatch = iq80310_intr_dispatch;
353	i80200_intr_enable(INTCTL_IM | INTCTL_PM);
354
355	/* Enable IRQs (don't yet use FIQs). */
356	enable_interrupts(I32_bit);
357}
358
359void *
360iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
361{
362	struct intrq *iq;
363	struct intrhand *ih;
364	u_int oldirqstate;
365
366	if (irq < 0 || irq > NIRQ)
367		panic("iq80310_intr_establish: IRQ %d out of range", irq);
368
369	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
370	if (ih == NULL)
371		return (NULL);
372
373	ih->ih_func = func;
374	ih->ih_arg = arg;
375	ih->ih_ipl = ipl;
376	ih->ih_irq = irq;
377
378	iq = &intrq[irq];
379
380	/* All IQ80310 interrupts are level-triggered. */
381	iq->iq_ist = IST_LEVEL;
382
383	oldirqstate = disable_interrupts(I32_bit);
384
385	TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
386
387	iq80310_intr_calculate_masks();
388
389	restore_interrupts(oldirqstate);
390
391	return (ih);
392}
393
394void
395iq80310_intr_disestablish(void *cookie)
396{
397	struct intrhand *ih = cookie;
398	struct intrq *iq = &intrq[ih->ih_irq];
399	int oldirqstate;
400
401	oldirqstate = disable_interrupts(I32_bit);
402
403	TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
404
405	iq80310_intr_calculate_masks();
406
407	restore_interrupts(oldirqstate);
408}
409
410void
411iq80310_intr_dispatch(struct clockframe *frame)
412{
413	struct intrq *iq;
414	struct intrhand *ih;
415	int oldirqstate, pcpl, irq, ibit, hwpend, rv, stray;
416
417	stray = 1;
418
419	/* First, disable external IRQs. */
420	i80200_intr_disable(INTCTL_IM | INTCTL_PM);
421
422	pcpl = current_spl_level;
423
424	for (hwpend = iq80310_intstat_read(); hwpend != 0;) {
425		irq = ffs(hwpend) - 1;
426		ibit = (1U << irq);
427
428		stray = 0;
429
430		hwpend &= ~ibit;
431
432		if (pcpl & ibit) {
433			/*
434			 * IRQ is masked; mark it as pending and check
435			 * the next one.  Note: external IRQs are already
436			 * disabled.
437			 */
438			iq80310_ipending |= ibit;
439			continue;
440		}
441
442		iq80310_ipending &= ~ibit;
443		rv = 0;
444
445		iq = &intrq[irq];
446		iq->iq_ev.ev_count++;
447		uvmexp.intrs++;
448		current_spl_level |= iq->iq_mask;
449		oldirqstate = enable_interrupts(I32_bit);
450		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
451		     ih = TAILQ_NEXT(ih, ih_list)) {
452			rv |= (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
453		}
454		restore_interrupts(oldirqstate);
455
456		current_spl_level = pcpl;
457
458#if 0 /* XXX */
459		if (rv == 0)
460			printf("Stray interrupt: IRQ %d\n", irq);
461#endif
462	}
463
464#if 0 /* XXX */
465	if (stray)
466		printf("Stray external interrupt\n");
467#endif
468
469	/* Check for pendings soft intrs. */
470	if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level) {
471		oldirqstate = enable_interrupts(I32_bit);
472		iq80310_do_soft();
473		restore_interrupts(oldirqstate);
474	}
475
476	/*
477	 * If no hardware interrupts are masked, re-enable external
478	 * interrupts.
479	 */
480	if ((iq80310_ipending & IRQ_BITS) == 0)
481		i80200_intr_enable(INTCTL_IM | INTCTL_PM);
482}
483