Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP
rather than per-CPU. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this.

XXX untested

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.17.28; 1.17.30;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.16.34; 1.16.44; 1.16.50;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.15.6; 1.15.8; 1.15.10;
Truly kill current_intr_depth once and for all.

branches: 1.14.8; 1.14.16; 1.14.20; 1.14.22; 1.14.28; 1.14.34;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.13.26;
merge ktrace-lwp.

branches: 1.12.2;
remove vestigal {,e}intr{names,cnt} symbols now that vmstat doesn't need them.

Enable/Restore alignment fault state on interrupt handler entry/exit.

branches: 1.10.2;
Garbage-collect prev_intr_depth; nothing uses it.

Restore .Lpmc_intr_return -- ben only removed one of two references to it.

Pull down rev 1.7.2.1 [must be careful which branch I commit to!]:
Reinstate .Lextirq_return: it was used in two places, and I only removed one
of them.

branches: 1.7.2;
Continue the " - . - 8" purge. Specifically:

add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

Use correct-for-ELF local labels.

Use cpsr_c rather then cpsr_all where appropriate.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

Clean up some comments.

* Interrupt status is in cp13.4, not cp13.1 (D'oh!)
* Fix an inverted test.

branches: 1.1.2; 1.1.4; 1.1.12; 1.1.14;
Add an IRQ vector to be shared by all i80200 applications. This
consults the interrupt source bits in the i80200 ICU and calls
a board-specific external IRQ dispatcher if an external IRQ is
pending.

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.17.28;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.16.34; 1.16.44; 1.16.50;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.15.6; 1.15.8; 1.15.10;
Truly kill current_intr_depth once and for all.

branches: 1.14.8; 1.14.16; 1.14.20; 1.14.22; 1.14.28; 1.14.34;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.13.26;
merge ktrace-lwp.

branches: 1.12.2;
remove vestigal {,e}intr{names,cnt} symbols now that vmstat doesn't need them.

Enable/Restore alignment fault state on interrupt handler entry/exit.

branches: 1.10.2;
Garbage-collect prev_intr_depth; nothing uses it.

Restore .Lpmc_intr_return -- ben only removed one of two references to it.

Pull down rev 1.7.2.1 [must be careful which branch I commit to!]:
Reinstate .Lextirq_return: it was used in two places, and I only removed one
of them.

branches: 1.7.2;
Continue the " - . - 8" purge. Specifically:

add rd, pc, #foo - . - 8 -> adr rd, foo
ldr rd, [pc, #foo - . - 8] -> ldr rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

Use correct-for-ELF local labels.

Use cpsr_c rather then cpsr_all where appropriate.

Implement pmc(9) -- An interface to hardware performance monitoring
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.

Clean up some comments.

* Interrupt status is in cp13.4, not cp13.1 (D'oh!)
* Fix an inverted test.

branches: 1.1.2; 1.1.4; 1.1.12; 1.1.14;
Add an IRQ vector to be shared by all i80200 applications. This
consults the interrupt source bits in the i80200 ICU and calls
a board-specific external IRQ dispatcher if an external IRQ is
pending.