i80200_irq.S revision 1.7 
1/*	$NetBSD: i80200_irq.S,v 1.7 2002/10/14 22:32:53 bjh21 Exp $	*/
2
3/*
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "assym.h"
39#include "opt_perfctrs.h"
40
41#include <machine/asm.h>
42#include <machine/cpu.h>
43#include <machine/frame.h>
44
45#include <arm/xscale/i80200reg.h>
46
47/*
48 * irq_entry:
49 *
50 *	Main entry point for the IRQ vector on i80200 CPUs.  Calls
51 *	board-specific external interrupt dispatch routine.
52 */
53
54	.text
55	.align	0
56
57.Lcurrent_intr_depth:
58	.word	_C_LABEL(current_intr_depth)
59	.word	_C_LABEL(prev_intr_depth)
60
61.Lintr_dispatch:
62	.word	_C_LABEL(i80200_extirq_dispatch)
63
64#if defined(PERFCTRS)
65.Lpmc_dispatch:
66	.word	_C_LABEL(xscale_pmc_dispatch)
67#endif
68
69.Lastpending:
70	.word	_C_LABEL(astpending)
71
72ASENTRY_NP(irq_entry)
73	sub	lr, lr, #0x00000004	/* Adjust the lr */
74
75	PUSHFRAMEINSVC			/* Push an interrupt frame */
76
77	/*
78	 * Note that we have entered the IRQ handler.  We are
79	 * in SVC mode so we cannot use the processor mode to
80	 * determine if we are in an IRQ.  Instead, we will
81	 * count each time the interrupt handler is nested.
82	 */
83	ldr	r0, .Lcurrent_intr_depth
84	ldr	r2, .Lcurrent_intr_depth+4
85	ldr	r1, [r0]
86	str	r1, [r2]
87	add	r1, r1, #1
88	str	r1, [r0]
89
90	/*
91	 * Get the interrupt status into a callee-save register.
92	 */
93	mrc	p13, 0, r4, c4, c0, 0
94
95#if defined(PERFCTRS)
96	/*
97	 * Check for PMU interrupts.
98	 * If we have one, call the routine to handle it.
99	 */
100	tst	r4, #(INTSRC_PI)
101	beq	.Lpmc_intr_return
102	mov	r1, r4
103	mov	r0, sp
104	mov	lr, pc
105	ldr	pc, .Lpmc_dispatch
106#endif
107
108	/*
109	 * XXX - any need to handle BMU interrupts?
110	 */
111
112	/*
113	 * Check for external IRQs.  If we have one, call the
114	 * external IRQ dispatcher.  The argument is a pointer
115	 * to the stack frame.  This function will be called with
116	 * interrupts disabled, and will return with interrupts
117	 * disabled.
118	 */
119	tst	r4, #(INTSRC_II)
120	beq	.Lextirq_return		/* no external IRQ pending */
121	ldr	r1, .Lintr_dispatch
122	mov	r0, sp
123	mov	lr, pc
124	ldr	pc, [r1]
125
126	/* Decremement the nest count. */
127	ldr	r0, .Lcurrent_intr_depth
128	ldr	r2, .Lcurrent_intr_depth+4
129	ldr	r1, [r0]
130	str	r1, [r2]
131	sub	r1, r1, #1
132	str	r1, [r0]
133
134	/*
135	 * If we're returning to user mode, check for pending ASTs.
136	 */
137	ldr	r0, [sp]		/* Get the SPSR from stack */
138	and	r0, r0, #(PSR_MODE)	/* Test for USR32 mode before the IRQ */
139	teq	r0, #(PSR_USR32_MODE)
140	bne	.Lirqout		/* Nope, get out now */
141
142.Lastloop:
143	ldr	r0, .Lastpending	/* Do we have an AST pending? */
144	ldr	r1, [r0]
145	teq	r1, #0x00000000
146	beq	.Lirqout		/* Nope, get out now */
147
148	mov	r1, #0x00000000
149	str	r1, [r0]		/* Clear astpending */
150
151	mrs	r4, cpsr		/* save CPSR */
152	bic	r0, r4, #(I32_bit)	/* Enable IRQs */
153	msr	cpsr_c, r0
154
155	mov	r0, sp
156	bl	_C_LABEL(ast)		/* ast(frame) */
157
158	msr	cpsr_c, r4		/* Disable IRQs */
159	b	.Lastloop		/* Check for more ASTs */
160
161.Lirqout:
162	PULLFRAMEFROMSVCANDEXIT
163	movs	pc, lr			/* Exit */
164
165	.bss
166	.align	0
167
168	.global _C_LABEL(astpending)
169_C_LABEL(astpending):
170	.word	0
171
172	.global	_C_LABEL(current_intr_depth)
173_C_LABEL(current_intr_depth):
174	.word	0
175
176	.global	_C_LABEL(prev_intr_depth)
177_C_LABEL(prev_intr_depth):
178	.word	0
179
180	/*
181	 * XXX Provide intrnames/intrcnt for legacy code, but
182	 * don't actually use them.
183	 */
184
185	.global _C_LABEL(intrnames), _C_LABEL(eintrnames)
186	.global _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
187_C_LABEL(intrnames):
188_C_LABEL(eintrnames):
189
190	.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
191_C_LABEL(intrcnt):
192_C_LABEL(eintrcnt):
193