History log of /netbsd-current/sys/arch/arm/cortex/gic_splfuncs.c
Revision Date Author Comments
# 1.5 30-Oct-2021 jmcneill

Implement gic_splraise and the gic_splx fast path in asm (armv8).


# 1.4 26-Sep-2021 jmcneill

Add missing insn barrier


# 1.3 20-Sep-2021 jmcneill

Make _splraise/_spllower/splx functions available to modules again.


# 1.2 18-Sep-2021 jmcneill

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.


# 1.1 10-Aug-2021 jmcneill

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.


# 1.4 26-Sep-2021 jmcneill

Add missing insn barrier


# 1.3 20-Sep-2021 jmcneill

Make _splraise/_spllower/splx functions available to modules again.


# 1.2 18-Sep-2021 jmcneill

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.


# 1.1 10-Aug-2021 jmcneill

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.


# 1.3 20-Sep-2021 jmcneill

Make _splraise/_spllower/splx functions available to modules again.


# 1.2 18-Sep-2021 jmcneill

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.


# 1.1 10-Aug-2021 jmcneill

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.


# 1.2 18-Sep-2021 jmcneill

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.


# 1.1 10-Aug-2021 jmcneill

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.


# 1.1 10-Aug-2021 jmcneill

Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.