gic_splfuncs.c revision 1.4
1/* $NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $"); 31 32#include <sys/param.h> 33#include <sys/atomic.h> 34#include <sys/kernel.h> 35#include <sys/lwp.h> 36 37#include <arm/pic/picvar.h> 38#include <arm/cpu.h> 39#include <arm/cpufunc.h> 40#include <arm/locore.h> 41 42#include <arm/cortex/gic_splfuncs.h> 43 44static int 45gic_splraise(int newipl) 46{ 47 struct cpu_info * const ci = curcpu(); 48 const int oldipl = ci->ci_cpl; 49 if (__predict_true(newipl > oldipl)) { 50 ci->ci_cpl = newipl; 51 } 52 return oldipl; 53} 54 55static int 56gic_spllower(int newipl) 57{ 58 struct cpu_info * const ci = curcpu(); 59 const int oldipl = ci->ci_cpl; 60 KASSERT(panicstr || newipl <= ci->ci_cpl); 61 if (newipl < ci->ci_cpl) { 62 register_t psw = DISABLE_INTERRUPT_SAVE(); 63 ci->ci_intr_depth++; 64 pic_do_pending_ints(psw, newipl, NULL); 65 ci->ci_intr_depth--; 66 if ((psw & I32_bit) == 0 || newipl == IPL_NONE) { 67 ENABLE_INTERRUPT(); 68 } 69 cpu_dosoftints(); 70 } 71 72 return oldipl; 73} 74 75static void 76gic_splx(int newipl) 77{ 78 struct cpu_info *ci = curcpu(); 79 register_t psw; 80 81 if (newipl >= ci->ci_cpl) { 82 return; 83 } 84 85 /* 86 * Try to avoid touching any hardware registers (DAIF, PMR) as an 87 * optimization for the common case of splraise followed by splx 88 * with no interrupts in between. 89 * 90 * If an interrupt fires in this critical section, the vector 91 * handler is responsible for returning to the address pointed 92 * to by ci_splx_restart to restart the sequence. 93 */ 94 if (__predict_true(ci->ci_intr_depth == 0)) { 95 ci->ci_splx_savedipl = newipl; 96 __insn_barrier(); 97 ci->ci_splx_restart = &&restart; 98 __insn_barrier(); 99checkhwpl: 100 if (ci->ci_hwpl <= newipl) { 101 ci->ci_cpl = newipl; 102 __insn_barrier(); 103 ci->ci_splx_restart = NULL; 104 goto dosoft; 105 } else { 106 ci->ci_splx_restart = NULL; 107 goto dohard; 108 } 109restart: 110 ci = curcpu(); 111 newipl = ci->ci_splx_savedipl; 112 goto checkhwpl; 113 } 114 115dohard: 116 psw = DISABLE_INTERRUPT_SAVE(); 117 ci->ci_intr_depth++; 118 pic_do_pending_ints(psw, newipl, NULL); 119 ci->ci_intr_depth--; 120 if ((psw & I32_bit) == 0) { 121 ENABLE_INTERRUPT(); 122 } 123 124dosoft: 125 cpu_dosoftints(); 126} 127 128void 129gic_spl_init(void) 130{ 131 pic_splraise = gic_splraise; 132 pic_spllower = gic_spllower; 133 pic_splx = gic_splx; 134} 135