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35921910 |
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03-Dec-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGE Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-3-dmitry.baryshkov@linaro.org
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#
08e49af5 |
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14-Aug-2023 |
Varadarajan Narayanan <quic_varada@quicinc.com> |
phy: qcom: Introduce M31 USB PHY driver Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
e464a318 |
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30-May-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
phy: qcom-qmp-usb: split off the legacy USB+dp_com support When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230531023415.1209301-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
601d0627 |
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19-Jun-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
phy: qcom: add the SGMII SerDes PHY driver Implement support for the SGMII/SerDes PHY present on various Qualcomm platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230619091336.194914-4-brgl@bgdev.pl Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
1904c3f5 |
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14-May-2023 |
Bjorn Andersson <quic_bjorande@quicinc.com> |
phy: qcom-qmp-combo: Introduce drm_bridge The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
2851117f |
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14-May-2023 |
Bjorn Andersson <quic_bjorande@quicinc.com> |
phy: qcom-qmp-combo: Introduce orientation switching The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/ Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-6-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
56d77c9a |
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08-Feb-2023 |
Abel Vesa <abel.vesa@linaro.org> |
phy: qcom: Add QCOM SNPS eUSB2 repeater driver PM8550B contains a eUSB2 repeater used for making the eUSB2 from SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy. So add a new phy driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208190200.2966723-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
80090810 |
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08-Feb-2023 |
Abel Vesa <abel.vesa@linaro.org> |
phy: qcom: Add QCOM SNPS eUSB2 driver The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
d1abd695 |
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02-Feb-2023 |
Stephen Boyd <swboyd@chromium.org> |
phy: qcom-qmp: Introduce Kconfig symbols for discrete drivers Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
6c37a02b |
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05-Nov-2022 |
Johan Hovold <johan+linaro@kernel.org> |
phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYs The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as PCIe2A and PCIe2B). Add support for fetching the 4-lane configuration from the TCSR and programming the lane registers of the second port when in 4-lane mode. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20221105145939.20318-17-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
f199223c |
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03-Nov-2021 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
phy: qcom: Introduce new eDP PHY driver Many recent Qualcomm platforms comes with native DP and eDP support. This consists of a controller in the MDSS and a QMP-like PHY. While similar to the well known QMP block, the eDP PHY only has TX lanes and the programming sequences are slightly different. Rather than continuing the trend of parameterize the QMP driver to pieces, this introduces the support as a new driver. The registration of link and pixel clocks are borrowed from the QMP driver. The non-DP link frequencies are omitted for now. The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only the prior is supported for now. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20211103234410.1352424-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
14839107 |
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13-Nov-2020 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
phy: qualcomm: Fix 28 nm Hi-Speed USB PHY OF dependency This Kconfig entry should declare a dependency on OF Fixes: 67b27dbeac4d ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-3-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
44786a26 |
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13-Nov-2020 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
phy: qualcomm: usb: Fix SuperSpeed PHY OF dependency This Kconfig entry should declare a dependency on OF Fixes: 6076967a500c ("phy: qualcomm: usb: Add SuperSpeed PHY driver") Reported-by: kernel test robot <lkp@intel.com> Link: https://lkml.org/lkml/2020/11/13/414 Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-2-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
ef19b117 |
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17-Jul-2020 |
Ansuel Smith <ansuelsmth@gmail.com> |
phy: qualcomm: add qcom ipq806x dwc usb phy driver This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Tested-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
02dca8c9 |
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29-Jun-2020 |
Vinod Koul <vkoul@kernel.org> |
phy: qcom: remove ufs qmp phy driver The UFS specific QMP PHY driver started off supporting the 14nm and 20nm hardware. With the 20nm support marked broken for a long time and the 14nm support added to the common QMP PHY, this driver has not been used in a while. So delete it Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200629145452.123035-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
51e8114f |
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04-May-2020 |
Wesley Cheng <wcheng@codeaurora.org> |
phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Philipp Zabel <pza@pengutronix.de> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
3c9d8f6c |
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03-May-2020 |
Robert Marko <robert.marko@sartura.hr> |
phy: add driver for Qualcomm IPQ40xx USB PHY Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
6076967a |
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11-Mar-2020 |
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
phy: qualcomm: usb: Add SuperSpeed PHY driver Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: Sriharsha Allenki's <sallenki@codeaurora.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
67b27dbe |
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11-Mar-2020 |
Shawn Guo <shawn.guo@linaro.org> |
phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
6ef72bc0 |
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01-May-2019 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
phy: qcom: Add Qualcomm PCIe2 PHY driver The Qualcomm PCIe2 PHY is based on design from Synopsys and found in several different platforms where the QMP PHY isn't used. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
ec8f24b7 |
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19-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
82af0932 |
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04-Sep-2018 |
Vivek Gautam <vivek.gautam@codeaurora.org> |
phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as Broken Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
cd3bf368 |
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24-Mar-2018 |
Alban Bedel <albeu@free.fr> |
phy: Add a driver for the ATH79 USB phy The ATH79 USB phy is very simple, it only have a reset. On some SoC a second reset is used to force the phy in suspend mode regardless of the USB controller status. This driver is added to the qualcom directory as atheros is now part of qualcom and newer SoC of this familly are marketed under the qualcom name. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
0b56e9a7 |
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10-May-2017 |
Vivek Gautam <vivek.gautam@codeaurora.org> |
phy: Group vendor specific phy drivers Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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