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6f12bca8 |
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14-Sep-2018 |
Ruchira Ravoori <ravoorir@google.com> |
[zircon][sdio]Perform tuning when setting ultra high speed Currently on VIM2, at times, the wifi chipset does not run all the way. This is mainly being attributed to power issues. Although not related, switching to ultra-high speed in sdio is disabled as a safety measure until the wifi stack is more stable. This changeset adds tuning procedure when switching to ultra-high speed. Tuning procedure helps determine any read delays required and the right frequency when the ultra-high speed is re-enabled. Test: On vim2, enabled ultra high speed and verified the wifi functionality. Change-Id: I32f0dbafbcdde32c7d220e38a1c43fc57e492284
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522cbc50 |
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08-Jun-2018 |
Ruchira Ravoori <ravoorir@google.com> |
[zircon][sdio]Add support for core sdio This changeset probes and initializes the sdio functions. It also implements the rw commands(CMD52 and CMD53) for control/IO operations on SDIO Change-Id: I8585c064602cae6256acc3074371d887aa014252
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e8a1ea40 |
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03-May-2018 |
Payam Moradshahi <payamm@google.com> |
[block][sdmmc] Correct current state flags for DATA and RCV Change-Id: I39b07f434bf296a00b7b377e9d0e696d6298aa98
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68a37251 |
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20-Apr-2018 |
Ruchira Ravoori <ravoorir@rodete-desktop-imager.corp.google.com> |
[zircon][aml-sd-emmc]Get read/write blocks working on emmc This is part 2 of emmc work on vim2. Together with https://fuchsia-review.googlesource.com/c/zircon/+/144353 I am able to read and write multiple blocks on emmc on vim2. Verified things work as expected on pixel. Change-Id: I950d299c850292ab2ac060e53a0dc0656a3ca442
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ce63421f |
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08-Apr-2018 |
Ruchira Ravoori <ravoorir@rodete-laptop-imager.corp.google.com> |
[zircon][sdhci] Move sdhci hardware details from sdmmc to sdhci layer sdmmc code is being reused for amlogic's sdhci which does not follow the sdhci spec. This changeset relocates the cmd info specific to sdchi from sdmmc layer to sdhci layer. Change-Id: I6640056e6c06ee51946f0b8be6a5b07a7beb1fd2
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829e5f88 |
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02-Apr-2018 |
Ruchira Ravoori <ravoorir@rodete-desktop-imager.corp.google.com> |
[zircon][sdhci] Modify sdmmc code to support amlogic sd controller Amlogic sdhci controller does not implement sdhci spec. However it can reuse the layers up and above sdmmc. This changeset does the following to support amlogic sdhci: 1. Introduce a quirk which takes care of command response being off by one for pcie sdhci controllers. 2. Move command semantics that are specific to sdhci controller from sdmmc to sdhci layer Change-Id: Ic5a00b537575dc7933c06561350f712578fd89b7
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4459d6f8 |
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10-Jan-2018 |
Yvonne Yip <yky@google.com> |
[dev][sdhci][sdmmc] remove iotxn and cleanup * switch to new block protocol * remove iotxn usage * introduce SDMMC protocol instead of device_ioctl() * fix PIO mode * make tuning command less special * fix various issues where we did not conform to the spec * comment out bit rotted SD card support for now Change-Id: I7b8e96d326cfe010d1a8e1355453ac89790d5498
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f3e2126c |
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12-Sep-2017 |
Roland McGrath <mcgrathr@google.com> |
[zx] Magenta -> Zircon The Great Renaming is here! Change-Id: I3229bdeb2a3d0e40fb4db6fec8ca7d971fbffb94
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7dbc3396 |
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26-Jun-2017 |
Yvonne Yip <yky@google.com> |
[dev][sdmmc][sdhci] enable HS timing and wide bus Change-Id: Ifaa1026da40ae1555693134a1109ff31e7f6a051
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e1b3aedc |
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12-Jun-2017 |
Yvonne Yip <yky@google.com> |
[dev][block] enable pci-sdhci and mmc Supports generic sdhci device on pci, and add basic mmc support to sdmmc driver. Currently the mmc driver initializes the card to legacy timing @ 26mhz, 1-bit data width. Transfers are done in poll mode only. Change-Id: I51979e02490e62010033cd3384635614a6570ba8
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