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267654 |
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19-Jun-2014 |
gjb |
Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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225736 |
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22-Sep-2011 |
kensmith |
Copy head to stable/9 as part of 9.0-RELEASE release cycle.
Approved by: re (implicit)
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222813 |
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07-Jun-2011 |
attilio |
etire the cpumask_t type and replace it with cpuset_t usage.
This is intended to fix the bug where cpu mask objects are capped to 32. MAXCPU, then, can now arbitrarely bumped to whatever value. Anyway, as long as several structures in the kernel are statically allocated and sized as MAXCPU, it is suggested to keep it as low as possible for the time being.
Technical notes on this commit itself: - More functions to handle with cpuset_t objects are introduced. The most notable are cpusetobj_ffs() (which calculates a ffs(3) for a cpuset_t object), cpusetobj_strprint() (which prepares a string representing a cpuset_t object) and cpusetobj_strscan() (which creates a valid cpuset_t starting from a string representation). - pc_cpumask and pc_other_cpus are target to be removed soon. With the moving from cpumask_t to cpuset_t they are now inefficient and not really useful. Anyway, for the time being, please note that access to pcpu datas is protected by sched_pin() in order to avoid migrating the CPU while reading more than one (possible) word - Please note that size of cpuset_t objects may differ between kernel and userland. While this is not directly related to the patch itself, it is good to understand that concept and possibly use the patch as a reference on how to deal with cpuset_t objects in userland, when accessing kernland members. - KTR_CPUMASK is changed and now is represented through a string, to be set as the example reported in NOTES.
Please additively note that no MAXCPU is bumped in this patch, but private testing has been done until to MAXCPU=128 on a real 8x8x2(htt) machine (amd64).
Please note that the FreeBSD version is not yet bumped because of the upcoming pcpu changes. However, note that this patch is not targeted for MFC.
People to thank for the time spent on this patch: - sbruno, pluknet and Nicholas Esborn (nick AT desert DOT net) tested several revision of the patches and really helped in improving stability of this work. - marius fixed several bugs in the sparc64 implementation and reviewed patches related to ktr. - jeff and jhb discussed the basic approach followed. - kib and marcel made targeted review on some specific part of the patch. - marius, art, nwhitehorn and andreast reviewed MD specific part of the patch. - marius, andreast, gonzo, nwhitehorn and jceel tested MD specific implementations of the patch. - Other people have made contributions on other patches that have been already committed and have been listed separately.
Companies that should be mentioned for having participated at several degrees: - Yahoo! for having offered the machines used for testing on big count of CPUs. - The FreeBSD Foundation for having sponsored my devsummit attendance, which has been instrumental. - Sandvine for having offered offices and infrastructure during development.
(I really hope I didn't forget anyone, if it happened I apologize in advance).
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218075 |
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29-Jan-2011 |
marcel |
Fix the interrupt code, broken 7 months ago. The interrupt framework already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken.
This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months...
Sponsored by: Juniper Networks
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209726 |
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06-Jul-2010 |
nwhitehorn |
It does not actually make sense to provide an IPI facility on non-root PICs, so replace cpuid logic with an assert.
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209725 |
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06-Jul-2010 |
nwhitehorn |
Fix interrupt distribution to multiple CPUs on systems with cascaded PICs. Because slave PICs send all interrupts to their CPU 0 output line (which is routed to a pin on the master PIC), changes to per-CPU register banks like EOI on the slave PIC must be accessed for CPU 0, instead of the CPU actually processing the interrupt.
Submitted by: Andreas Tobler
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209724 |
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06-Jul-2010 |
nwhitehorn |
Move the EOI logic when starting ithreads into intr_machdep instead of relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
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209639 |
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02-Jul-2010 |
marcel |
Remove the unneeded header <machine/intr.h>.
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209486 |
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23-Jun-2010 |
nwhitehorn |
Configure interrupts on SMP systems to be distributed among all online CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
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209485 |
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23-Jun-2010 |
marcel |
In the attach method, refactor to take into account that BUS_GET_RESOURCE_LIST() can return a NULL pointer -- and will for MPC85xx kernels.
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209299 |
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18-Jun-2010 |
nwhitehorn |
Change the default interrupt polarity on PowerPC systems from high to low. On Apple systems at least, all the level interrupts are wired active low. Before this change, our PIC programming only worked because Apple hardware ignores the interrupt polarity bit on all interrupts except IRQ 0.
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209298 |
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18-Jun-2010 |
nwhitehorn |
Provide for multiple, cascaded PICs on PowerPC systems, and extend the OFW interrupt map interface to also return the device's interrupt parent.
MFC after: 8.1-RELEASE
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208149 |
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16-May-2010 |
nwhitehorn |
Add support for the U4 PCI-Express bridge chipset used in late-generation Powermac G5 systems. MSI and several other things are not presently supported.
The U3/U4 internal device support portions of this change were contributed by Andreas Tobler.
MFC after: 1 week
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193909 |
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10-Jun-2009 |
grehan |
Get the gdb/psim emulator functioning again.
aim/machdep.c: - the RI status register bit needs to be set when doing the mtmsrd 64-bit instruction test - psim doesn't implement the dcbz instruction so the run-time cacheline test fails. Set the cachline size to 32 to avoid infinite loops in future calls to __syncicache()
aim/platform_chrp.c: - if after iterating through / and a name property of "cpus" still isn't found, just search directly for '/cpus'. - psim doesn't put a "reg" property on it's cpu nodes, so assume 0 since it is uniprocessor-only at this point
powerpc/openpic.c - the number of CPUs reported is 1 too many on psim's openpic
Reviewed by: nwhitehorn MFC after: 1 week (openpic part)
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192532 |
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21-May-2009 |
raj |
Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.
Obtained from: Freescale, Semihalf
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183028 |
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14-Sep-2008 |
marcel |
Remove debugging code.
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178628 |
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27-Apr-2008 |
marcel |
MFp4: SMP support
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176918 |
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07-Mar-2008 |
marcel |
Add support for the BUS_CONFIG_INTR() method to the platform and to openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
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176208 |
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12-Feb-2008 |
marcel |
Add PIC support for IPIs. When registering an interrupt handler, the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
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171805 |
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11-Aug-2007 |
marcel |
Revamp the interrupt handling in support of INTR_FILTER. This includes: o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware.
Approved by: re (blanket)
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166901 |
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23-Feb-2007 |
piso |
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr()
o add an int return code to all fast handlers
o retire INTR_FAST/IH_FAST
For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current
Reviewed by: many Approved by: re@
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157895 |
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20-Apr-2006 |
imp |
Set the rid for any resource obtained from rman_resource_reserve.
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139825 |
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07-Jan-2005 |
imp |
/* -> /*- for license, minor formatting changes
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133521 |
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11-Aug-2004 |
marius |
- Use the rman_get_* functions instead of reaching into struct resource. - Remove __RMAN_RESORUCE_VISIBLE again. It's no longer required either because of the above change or because struct rman is no longer hidden.
Reviewed by: grehan Tested by: cross-compile on i386
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131400 |
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01-Jul-2004 |
grehan |
Catch up with __RMAN_RESOURCE_VISIBLE change
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124469 |
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13-Jan-2004 |
grehan |
Make the OpenPic driver bus-independent, with attachments for the MacIO chip and PSIM's IOBus. Bus-specific drivers should use the identify method to attach themselves to nexus so interrupt can be allocated before the h/w is probed. The 'early attach' routine in openpic is used for this stage of boot. When h/w is probed, the openpic can be attached properly. It will enable interrupts allocated prior to this.
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122841 |
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17-Nov-2003 |
peter |
Widen the enable/disable helper function's argument in line with the ithread_create() changes etc. This should be mostly a NOP.
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111156 |
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19-Feb-2003 |
grehan |
Adjust IRQ count for psim's OpenPIC model - it seems to be off by 1.
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110167 |
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31-Jan-2003 |
benno |
Make nirq mean 'number of irqs' and not 'last irq'.
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109920 |
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27-Jan-2003 |
benno |
Back out some changes that snuck in with the last commit.
Pointy hat to: benno
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109919 |
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27-Jan-2003 |
benno |
Flesh out bus_dmamap_sync.
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109156 |
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13-Jan-2003 |
benno |
Correct an off-by-one error in the calculation of the number of interrupt resources we're managing.
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103603 |
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19-Sep-2002 |
grehan |
- psim device support - comment out re-enabling of interrupts until problems are sorted
Approved by: benno
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99723 |
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10-Jul-2002 |
benno |
Remove some unused includes.
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99654 |
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09-Jul-2002 |
benno |
Driver for OpenPIC compatible interrupt controllers. It's fairly PowerMac specific at the moment, but that should be fixable.
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