openpic.c revision 209639 
1/*-
2 * Copyright (C) 2002 Benno Rice.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: head/sys/powerpc/powerpc/openpic.c 209639 2010-07-02 02:17:39Z marcel $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/bus.h>
31#include <sys/conf.h>
32#include <sys/kernel.h>
33#include <sys/proc.h>
34#include <sys/rman.h>
35#include <sys/sched.h>
36
37#include <machine/bus.h>
38#include <machine/intr_machdep.h>
39#include <machine/md_var.h>
40#include <machine/pio.h>
41#include <machine/resource.h>
42
43#include <vm/vm.h>
44#include <vm/pmap.h>
45
46#include <machine/openpicreg.h>
47#include <machine/openpicvar.h>
48
49#include "pic_if.h"
50
51devclass_t openpic_devclass;
52
53/*
54 * Local routines
55 */
56static int openpic_intr(void *arg);
57
58static __inline uint32_t
59openpic_read(struct openpic_softc *sc, u_int reg)
60{
61	return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
62}
63
64static __inline void
65openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
66{
67	bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
68}
69
70static __inline void
71openpic_set_priority(struct openpic_softc *sc, int pri)
72{
73	u_int tpr;
74	uint32_t x;
75
76	sched_pin();
77	tpr = OPENPIC_PCPU_TPR(PCPU_GET(cpuid));
78	x = openpic_read(sc, tpr);
79	x &= ~OPENPIC_TPR_MASK;
80	x |= pri;
81	openpic_write(sc, tpr, x);
82	sched_unpin();
83}
84
85int
86openpic_attach(device_t dev)
87{
88	struct openpic_softc *sc;
89	u_int     cpu, ipi, irq;
90	u_int32_t x;
91
92	sc = device_get_softc(dev);
93	sc->sc_dev = dev;
94
95	sc->sc_rid = 0;
96	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
97	    RF_ACTIVE);
98
99	if (sc->sc_memr == NULL) {
100		device_printf(dev, "Could not alloc mem resource!\n");
101		return (ENXIO);
102	}
103
104	sc->sc_bt = rman_get_bustag(sc->sc_memr);
105	sc->sc_bh = rman_get_bushandle(sc->sc_memr);
106
107	/* Reset the PIC */
108	x = openpic_read(sc, OPENPIC_CONFIG);
109	x |= OPENPIC_CONFIG_RESET;
110	openpic_write(sc, OPENPIC_CONFIG, x);
111
112	while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
113		powerpc_sync();
114		DELAY(100);
115	}
116
117	/* Check if this is a cascaded PIC */
118	sc->sc_irq = 0;
119	sc->sc_intr = NULL;
120	do {
121		struct resource_list *rl;
122
123		rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
124		if (rl == NULL)
125			break;
126		if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
127			break;
128
129		sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
130		    &sc->sc_irq, RF_ACTIVE);
131
132		/* XXX Cascaded PICs pass NULL trapframes! */
133		bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
134		    openpic_intr, NULL, dev, &sc->sc_icookie);
135	} while (0);
136
137	/* Reset the PIC */
138	x = openpic_read(sc, OPENPIC_CONFIG);
139	x |= OPENPIC_CONFIG_RESET;
140	openpic_write(sc, OPENPIC_CONFIG, x);
141
142	while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
143		powerpc_sync();
144		DELAY(100);
145	}
146
147	x = openpic_read(sc, OPENPIC_FEATURE);
148	switch (x & OPENPIC_FEATURE_VERSION_MASK) {
149	case 1:
150		sc->sc_version = "1.0";
151		break;
152	case 2:
153		sc->sc_version = "1.2";
154		break;
155	case 3:
156		sc->sc_version = "1.3";
157		break;
158	default:
159		sc->sc_version = "unknown";
160		break;
161	}
162
163	sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
164	    OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
165	sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
166	    OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
167
168	/*
169	 * PSIM seems to report 1 too many IRQs and CPUs
170	 */
171	if (sc->sc_psim) {
172		sc->sc_nirq--;
173		sc->sc_ncpu--;
174	}
175
176	if (bootverbose)
177		device_printf(dev,
178		    "Version %s, supports %d CPUs and %d irqs\n",
179		    sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
180
181	for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
182		openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
183
184	/* Reset and disable all interrupts. */
185	for (irq = 0; irq < sc->sc_nirq; irq++) {
186		x = irq;                /* irq == vector. */
187		x |= OPENPIC_IMASK;
188		x |= OPENPIC_POLARITY_NEGATIVE;
189		x |= OPENPIC_SENSE_LEVEL;
190		x |= 8 << OPENPIC_PRIORITY_SHIFT;
191		openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
192	}
193
194	/* Reset and disable all IPIs. */
195	for (ipi = 0; ipi < 4; ipi++) {
196		x = sc->sc_nirq + ipi;
197		x |= OPENPIC_IMASK;
198		x |= 15 << OPENPIC_PRIORITY_SHIFT;
199		openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
200	}
201
202	/* we don't need 8259 passthrough mode */
203	x = openpic_read(sc, OPENPIC_CONFIG);
204	x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
205	openpic_write(sc, OPENPIC_CONFIG, x);
206
207	/* send all interrupts to cpu 0 */
208	for (irq = 0; irq < sc->sc_nirq; irq++)
209		openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
210
211	/* clear all pending interrupts */
212	for (irq = 0; irq < sc->sc_nirq; irq++) {
213		(void)openpic_read(sc, OPENPIC_PCPU_IACK(PCPU_GET(cpuid)));
214		openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0);
215	}
216
217	for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
218		openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
219
220	powerpc_register_pic(dev, sc->sc_nirq);
221
222	/* If this is not a cascaded PIC, it must be the root PIC */
223	if (sc->sc_intr == NULL)
224		root_pic = dev;
225
226	return (0);
227}
228
229/*
230 * PIC I/F methods
231 */
232
233void
234openpic_bind(device_t dev, u_int irq, cpumask_t cpumask)
235{
236	struct openpic_softc *sc;
237
238	/* If we aren't directly connected to the CPU, this won't work */
239	if (dev != root_pic)
240		return;
241
242	sc = device_get_softc(dev);
243	openpic_write(sc, OPENPIC_IDEST(irq), cpumask);
244}
245
246void
247openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
248    enum intr_polarity pol)
249{
250	struct openpic_softc *sc;
251	uint32_t x;
252
253	sc = device_get_softc(dev);
254	x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
255	if (pol == INTR_POLARITY_LOW)
256		x &= ~OPENPIC_POLARITY_POSITIVE;
257	else
258		x |= OPENPIC_POLARITY_POSITIVE;
259	if (trig == INTR_TRIGGER_EDGE)
260		x &= ~OPENPIC_SENSE_LEVEL;
261	else
262		x |= OPENPIC_SENSE_LEVEL;
263	openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
264}
265
266static int
267openpic_intr(void *arg)
268{
269	device_t dev = (device_t)(arg);
270
271	/* XXX Cascaded PICs do not pass non-NULL trapframes! */
272	openpic_dispatch(dev, NULL);
273
274	return (FILTER_HANDLED);
275}
276
277void
278openpic_dispatch(device_t dev, struct trapframe *tf)
279{
280	struct openpic_softc *sc;
281	u_int cpuid, vector;
282
283	CTR1(KTR_INTR, "%s: got interrupt", __func__);
284
285	cpuid = PCPU_GET(cpuid);
286	sc = device_get_softc(dev);
287
288	while (1) {
289		vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
290		vector &= OPENPIC_VECTOR_MASK;
291		if (vector == 255)
292			break;
293		powerpc_dispatch_intr(vector, tf);
294	}
295}
296
297void
298openpic_enable(device_t dev, u_int irq, u_int vector)
299{
300	struct openpic_softc *sc;
301	uint32_t x;
302
303	sc = device_get_softc(dev);
304	if (irq < sc->sc_nirq) {
305		x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
306		x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
307		x |= vector;
308		openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
309	} else {
310		x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
311		x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
312		x |= vector;
313		openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
314	}
315}
316
317void
318openpic_eoi(device_t dev, u_int irq __unused)
319{
320	struct openpic_softc *sc;
321
322	sc = device_get_softc(dev);
323	openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0);
324}
325
326void
327openpic_ipi(device_t dev, u_int cpu)
328{
329	struct openpic_softc *sc;
330
331	sc = device_get_softc(dev);
332	sched_pin();
333	openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
334	    1u << cpu);
335	sched_unpin();
336}
337
338void
339openpic_mask(device_t dev, u_int irq)
340{
341	struct openpic_softc *sc;
342	uint32_t x;
343
344	sc = device_get_softc(dev);
345	if (irq < sc->sc_nirq) {
346		x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
347		x |= OPENPIC_IMASK;
348		openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
349	} else {
350		x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
351		x |= OPENPIC_IMASK;
352		openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
353	}
354	openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0);
355}
356
357void
358openpic_unmask(device_t dev, u_int irq)
359{
360	struct openpic_softc *sc;
361	uint32_t x;
362
363	sc = device_get_softc(dev);
364	if (irq < sc->sc_nirq) {
365		x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
366		x &= ~OPENPIC_IMASK;
367		openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
368	} else {
369		x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
370		x &= ~OPENPIC_IMASK;
371		openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
372	}
373}
374