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267654 |
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19-Jun-2014 |
gjb |
Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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256272 |
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10-Oct-2013 |
jhb |
MFC 253450: Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions.
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#
253273 |
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12-Jul-2013 |
marius |
MFC: r253120
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers.
Submitted by: jhb (mostly) Approved by: re (hrs), jhb
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225736 |
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22-Sep-2011 |
kensmith |
Copy head to stable/9 as part of 9.0-RELEASE release cycle.
Approved by: re (implicit)
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#
224069 |
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15-Jul-2011 |
jhb |
Respect the BIOS/firmware's notion of acceptable address ranges for PCI resource allocation on x86 platforms: - Add a new helper API that Host-PCI bridge drivers can use to restrict resource allocation requests to a set of address ranges for different resource types. - For the ACPI Host-PCI bridge driver, use Producer address range resources in _CRS to enumerate valid address ranges for a given Host-PCI bridge. This can be disabled by including "hostres" in the debug.acpi.disabled tunable. - For the MPTable Host-PCI bridge driver, use entries in the extended MPTable to determine the valid address ranges for a given Host-PCI bridge. This required adding code to parse extended table entries.
Similar to the new PCI-PCI bridge driver, these changes are only enabled if the NEW_PCIB kernel option is enabled (which is enabled by default on amd64 and i386).
Approved by: re (kib)
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#
221393 |
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03-May-2011 |
jhb |
Reimplement how PCI-PCI bridges manage their I/O windows. Previously the driver would verify that requests for child devices were confined to any existing I/O windows, but the driver relied on the firmware to initialize the windows and would never grow the windows for new requests. Now the driver actively manages the I/O windows.
This is implemented by allocating a bus resource for each I/O window from the parent PCI bus and suballocating that resource to child devices. The suballocations are managed by creating an rman for each I/O window. The suballocated resources are mapped by passing the bus_activate_resource() call up to the parent PCI bus. Windows are grown when needed by using bus_adjust_resource() to adjust the resource allocated from the parent PCI bus. If the adjust request succeeds, the window is adjusted and the suballocation request for the child device is retried.
When growing a window, the rman_first_free_region() and rman_last_free_region() routines are used to determine if the front or end of the existing I/O window is free. From using that, the smallest ranges that need to be added to either the front or back of the window are computed. The driver will first try to grow the window in whichever direction requires the smallest growth first followed by the other direction if that fails.
Subtractive bridges will first attempt to satisfy requests for child resources from I/O windows (including attempts to grow the windows). If that fails, the request is passed up to the parent PCI bus directly however.
The PCI-PCI bridge driver will try to use firmware-assigned ranges for child BARs first and only allocate a "fresh" range if that specific range cannot be accommodated in the I/O window. This allows systems where the firmware assigns resources during boot but later wipes the I/O windows (some ACPI BIOSen are known to do this) to "rediscover" the original I/O window ranges.
The ACPI Host-PCI bridge driver has been adjusted to correctly honor hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge makes a wildcard request for an I/O window range.
The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option is enabled. This is a transition aide to allow platforms that do not yet support bus_activate_resource() and bus_adjust_resource() in their Host-PCI bridge drivers (and possibly other drivers as needed) to use the old driver for now. Once all platforms support the new driver, the kernel option and old driver will be removed.
PR: kern/143874 kern/149306 Tested by: mav
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#
210864 |
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05-Aug-2010 |
jhb |
- Retire acpi_pcib_resume(). It is has just been an alias for bus_generic_resume() since the pci_link(4) driver was added. - Change the ACPI PCI-PCI bridge driver to inherit most of its methods from the generic PCI-PCI bridge driver. In particular, this will now restore PCI config registers for ACPI PCI-PCI bridges.
Tested by: Oleg Sharoyko osharoiko of gmail
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#
189792 |
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14-Mar-2009 |
imp |
Two fixes: (1) Fix pcib_read/write_config prototypes. (2) When contrainting a resource request for a 'subtractive' bridge, it is important to select a range outside the base/limit registers, since those are the only values known to not possibly work. On my HP laptop, the base bridge excludes I/O ports 0xa000-0xafff, however that was the range we were passing up the tree. Instead, when a range spans the "hole" we now arbitrarily pick the range just above the hole to allocate from.
All of my rl and xl cards, at a minimum, started working again on this laptop with those fixes.
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#
181789 |
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16-Aug-2008 |
imp |
Add some sysctl reporting for most pci_pci bridges. We now report domain, pribus (the primary bus, eg the bus that this chip is on), secbus (the secondary bus, eg the bus immediately behind this chip) and subbus (the number of the highest bus behind this chip). Normally, this information is reported via bootverbose parameters, but that's hard to use for debugging in some cases.
This adds reading of pribus to make this happen. In addition, change the narrow types to u_int to allow for easier reporting via sysctl for domain, secbus and subbus. This should have no effect, but if it does, please let me know.
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#
172394 |
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30-Sep-2007 |
marius |
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled.
Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
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#
169221 |
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02-May-2007 |
jhb |
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage.
The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system.
MFC after: 1 month
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#
166176 |
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22-Jan-2007 |
jhb |
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ.
Tested by: scottl
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#
165995 |
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13-Jan-2007 |
jhb |
- Add a new flag to the PCI-PCI driver to disable MSI on devices behind the bridge if it doesn't pass MSI messages up correctly. We set the flag in pcib_attach() if the device ID is disabled via a PCI quirk. - Disable MSI for devices behind the AMD 8131 HT-PCIX bridge. Linux has the same quirk.
Tested by: no one despite repeated calls for testers
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#
165217 |
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14-Dec-2006 |
jhb |
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
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#
164264 |
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13-Nov-2006 |
jhb |
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
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#
154079 |
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06-Jan-2006 |
jhb |
- Make pcib_devclass private to sys/dev/pci/pci_pci.c and change all the various pcib drivers to use their own private devclass_t variables for their modules. - Use the DEFINE_CLASS_0() macro to declare drivers for the various pcib drivers while I'm here.
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#
124365 |
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11-Jan-2004 |
imp |
Add support for subtractive decoding bridges. These bridges pass all signals to addresses to the child busses. Typically, ProgIf of 1 means a subtractive bridge. However, Intel has a whole lot of ones with a ProgIf of 80 that are also subtractive. We cope with these bridges too. This eliminates hw.pci.allow_unsupported_io_range because that had almost the same effect as these patches (almost means 'buggy'). Remove the bogus checks for ISA bus locations: these cycles aren't special and are only passed by transparent bridges.
We allow any range to succeed. If the range is a superset of the range that's decoded, trim the resource to that range. Otherwise, pass the range unchanged. This will change the location that PC Card and CardBus cards are attached. This might bogusly cause some overlapping allocation that wasn't present before, but the overlapping fixes need to be in the pci level.
There's also a few formatting changes here.
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#
119266 |
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22-Aug-2003 |
imp |
Prefer the uintXX_t to the u_intXX_t names.
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#
109229 |
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14-Jan-2003 |
benno |
Make the base pcib_route_interrupt method available to other pci-pci bridge sub-classes.
This allows the powerpc kernel to build again.
Forgotten by: benno Spotted by: grehan
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#
107172 |
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22-Nov-2002 |
jhb |
Add a function host_pcib_get_bnsno() that attempts to determine the bus number of the child bus of a host to PCI bridge by reading from proprietary configuration registers in the host to PCI bridge devices.
Approved by: re
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#
103042 |
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06-Sep-2002 |
jhb |
Export pcib_attach() as a "protected" for use in subclasses of the PCI-PCI bridge driver.
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#
102441 |
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26-Aug-2002 |
jhb |
Export a few symbols as globals to allow subclassing of this driver. In OOP speak, you would mark these as 'protected' members. Specifically: - Make the pcib_softc struct public so it can be used by subclasses. - Make pcib_{read,write}_ivar(), pcib_alloc_resource(), pcib_maxslots(), and pcib_{read,write}_config() globals that can be used by subclasses. - Make the pcib devclass a global variable. - Move most of the pcib_attach() function into a global pcib_attach_common() function that can be called by the attach routines of subclasses.
Tested on: i386, alpha, sparc64, ia64
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