#
303975 |
|
11-Aug-2016 |
gjb |
Copy stable/11@r303970 to releng/11.0 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, and rename it to RC1.
Update __FreeBSD_version.
Use the quarterly branch for the default FreeBSD.conf pkg(8) repo and the dvd1.iso packages population.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
302408 |
|
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle. Prune svn:mergeinfo from the new branch, as nothing has been merged here.
Additional commits post-branch will follow.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
|
#
302373 |
|
06-Jul-2016 |
ngie |
Fix CTASSERT issue in a more clean way
- Replace all CTASSERT macro instances with static_assert's. - Remove the WRAPPED_CTASSERT macro; it's now an unnecessary obfuscation. - Localize all static_assert's to the structures being tested. - Sort some headers per-style(9).
Approved by: re (hrs) Differential Revision: https://reviews.freebsd.org/D7130 MFC after: 1 week X-MFC with: r302364 Reviewed by: ed, grehan (maintainer) Submitted by: ed Sponsored by: EMC / Isilon Storage Division
|
#
302364 |
|
06-Jul-2016 |
ngie |
Fix gcc warnings
Add `WRAPPED_CTASSERT` macro by annotating CTASSERTs with __unused to deal with -Wunused-local-typedefs warnings from gcc 4.8+. All other compilers (clang, etc) use CTASSERT as-is. A more generic solution for this issue will be proposed after ^/stable/11 is forked.
Consolidate all CTASSERTs under one block instead of inlining them in functions.
Approved by: re (gjb) Differential Revision: https://reviews.freebsd.org/D7119 MFC after: 1 week Reported by: Jenkins Reviewed by: grehan (maintainer) Sponsored by: EMC / Isilon Storage Division
|
#
299676 |
|
13-May-2016 |
pfg |
bhyve: consider the bogus case of a negative bar idx.
This is a followup to r297472 to squelch Coverity.
CID: 1194319
|
#
297472 |
|
31-Mar-2016 |
pfg |
pci_emul_dior(): fix uninitialized scalar variable.
Prevent from returning an unitialized value in case the ior size is unknown.
CID: 1194319 Reviewed by: grehan
|
#
292970 |
|
31-Dec-2015 |
araujo |
Clean up unused-but-set-variable spotted by gcc-4.9.
Reviewed by: grehan Approved by: bapt (mentor) Differential Revision: https://reviews.freebsd.org/D4735
|
#
289677 |
|
21-Oct-2015 |
eadler |
Fix a ton of speelling errors
arc lint is helpful
Reviewed By: allanjude, wblock, #manpages, chris@bsdjunk.com Differential Revision: https://reviews.freebsd.org/D3337
|
#
282335 |
|
02-May-2015 |
neel |
Advertise an additional memory BAR in the "dummy" device emulation.
This is useful for testing the MOVS emulation when both the source and destination addresses are in the MMIO space.
MFC after: 1 week
|
#
281946 |
|
24-Apr-2015 |
neel |
Don't allow guest to modify readonly bits in the PCI config 'status' register.
Reported by: Leon Dang (ldang@nahannisys.com) MFC after: 2 weeks
|
#
269700 |
|
08-Aug-2014 |
neel |
Support PCI extended config space in bhyve.
Add the ACPI MCFG table to advertise the extended config memory window.
Introduce a new flag MEM_F_IMMUTABLE for memory ranges that cannot be deleted or moved in the guest's address space. The PCI extended config space is an example of an immutable memory range.
Add emulation for the "movzw" instruction. This instruction is used by FreeBSD to read a 16-bit extended config space register.
CR: https://phabric.freebsd.org/D505 Reviewed by: jhb, grehan Requested by: tychon
|
#
267811 |
|
24-Jun-2014 |
neel |
Provide APIs to directly get 'lowmem' and 'highmem' size directly.
Previously the sizes were inferred indirectly based on the size of the mappings at 0 and 4GB respectively. This works fine as long as size of the allocation is identical to the size of the mapping in the guest's address space. However, if the mapping is disjoint then this assumption falls apart (e.g., due to the legacy BIOS hole between 640KB and 1MB).
|
#
267294 |
|
09-Jun-2014 |
tychon |
r267169 should apply to 64-bit BARs as well.
Reviewed by: neel
|
#
267169 |
|
06-Jun-2014 |
tychon |
Some devices (e.g. Intel AHCI and NICs) support quad-word access to register pairs where two 32-bit registers make up a larger logical size. Support those access by splitting the quad-word into two double-words.
Reviewed by: grehan
|
#
266125 |
|
15-May-2014 |
jhb |
Implement a PCI interrupt router to route PCI legacy INTx interrupts to the legacy 8259A PICs. - Implement an ICH-comptabile PCI interrupt router on the lpc device with 8 steerable pins configured via config space access to byte-wide registers at 0x60-63 and 0x68-6b. - For each configured PCI INTx interrupt, route it to both an I/O APIC pin and a PCI interrupt router pin. When a PCI INTx interrupt is asserted, ensure that both pins are asserted. - Provide an initial routing of PCI interrupt router (PIRQ) pins to 8259A pins (ISA IRQs) and initialize the interrupt line config register for the corresponding PCI function with the ISA IRQ as this matches existing hardware. - Add a global _PIC method for OSPM to select the desired interrupt routing configuration. - Update the _PRT methods for PCI bridges to provide both APIC and legacy PRT tables and return the appropriate table based on the configured routing configuration. Note that if the lpc device is not configured, no routing information is provided. - When the lpc device is enabled, provide ACPI PCI link devices corresponding to each PIRQ pin. - Add a VMM ioctl to adjust the trigger mode (edge vs level) for 8259A pins via the ELCR. - Mark the power management SCI as level triggered. - Don't hardcode the number of elements in Packages in the source for the DSDT. iasl(8) will fill in the actual number of elements, and this makes it simpler to generate a Package with a variable number of elements.
Reviewed by: tycho
|
#
265211 |
|
02-May-2014 |
neel |
Don't allow MPtable generation if there are multiple PCI hierarchies. This is because there isn't a standard way to relay this information to the guest OS.
Add a command line option "-Y" to bhyve(8) to inhibit MPtable generation.
If the virtual machine is using PCI devices on buses other than 0 then it can still use ACPI tables to convey this information to the guest.
Discussed with: grehan@
|
#
264921 |
|
25-Apr-2014 |
grehan |
Respect and track the enable bit in the PCI configuration address word. Ignore writes, and return 0xff's, on config accesses when not set. Behaviour now matches that seen on h/w.
Found with a NetBSD/amd64 guest.
Reviewed by: tychon MFC after: 3 weeks
|
#
264770 |
|
22-Apr-2014 |
delphij |
Use calloc() in favor of malloc + memset.
Reviewed by: neel
|
#
262184 |
|
18-Feb-2014 |
neel |
Add a check to validate that memory BARs of passthru devices are 4KB aligned.
Also, the MSI-x table offset is not required to be 4KB aligned so take this into account when computing the pages occupied by the MSI-x tables.
|
#
262143 |
|
18-Feb-2014 |
jhb |
Tweak the handling of PCI capabilities in emulated devices to remove the non-standard zero capability list terminator. Instead, track the start and end of the most recently added capability and use that to adjust the previous capability's next pointer when a capability is added and to determine the range of config registers belonging to PCI capability registers.
Reviewed by: neel
|
#
261904 |
|
14-Feb-2014 |
neel |
Allow PCI devices to be configured on all valid bus numbers from 0 to 255.
This is done by representing each bus as root PCI device in ACPI. The device implements the _BBN method to return the PCI bus number to the guest OS.
Each PCI bus keeps track of the resources that is decodes for devices configured on the bus: i/o, mmio (32-bit) and mmio (64-bit). These windows are advertised to the guest via the _CRS object of the root device.
Bus 0 is treated specially since it consumes the I/O ports to access the PCI config space [0xcf8-0xcff]. It also decodes the legacy I/O ports that are consumed by devices on the LPC bus. For this reason the LPC bridge can be configured only on bus 0.
The bus number can be specified using the following command line option to bhyve(8): "-s <bus>:<slot>:<func>,<emul>[,<config>]"
Discussed with: grehan@ Reviewed by: jhb@
|
#
261268 |
|
29-Jan-2014 |
jhb |
Enhance the support for PCI legacy INTx interrupts and enable them in the virtio backends. - Add a new ioctl to export the count of pins on the I/O APIC from vmm to the hypervisor. - Use pins on the I/O APIC >= 16 for PCI interrupts leaving 0-15 for ISA interrupts. - Populate the MP Table with I/O interrupt entries for any PCI INTx interrupts. - Create a _PRT table under the PCI root bridge in ACPI to route any PCI INTx interrupts appropriately. - Track which INTx interrupts are in use per-slot so that functions that share a slot attempt to distribute their INTx interrupts across the four available pins. - Implicitly mask INTx interrupts if either MSI or MSI-X is enabled and when the INTx DIS bit is set in a function's PCI command register. Either assert or deassert the associated I/O APIC pin when the state of one of those conditions changes. - Add INTx support to the virtio backends. - Always advertise the MSI capability in the virtio backends.
Submitted by: neel (7) Reviewed by: neel MFC after: 2 weeks
|
#
261217 |
|
27-Jan-2014 |
jhb |
Remove support for legacy PCI devices. These haven't been needed since support for LPC uart devices was added and it conflicts with upcoming patches to add PCI INTx support.
Reviewed by: neel
|
#
260206 |
|
02-Jan-2014 |
jhb |
Rework the DSDT generation code a bit to generate more accurate info about LPC devices. Among other things, the LPC serial ports now appear as ACPI devices. - Move the info for the top-level PCI bus into the PCI emulation code and add ResourceProducer entries for the memory ranges decoded by the bus for memory BARs. - Add a framework to allow each PCI emulation driver to optionally write an entry into the DSDT under the \_SB_.PCI0 namespace. The LPC driver uses this to write a node for the LPC bus (\_SB_.PCI0.ISA). - Add a linker set to allow any LPC devices to write entries into the DSDT below the LPC node. - Move the existing DSDT block for the RTC to the RTC driver. - Add DSDT nodes for the AT PIC, the 8254 ISA timer, and the LPC UART devices. - Add a "SuperIO" device under the LPC node to claim "system resources" aling with a linker set to allow various drivers to add IO or memory ranges that should be claimed as a system resource. - Add system resource entries for the extended RTC IO range, the registers used for ACPI power management, the ELCR, PCI interrupt routing register, and post data register. - Add various helper routines for generating DSDT entries.
Reviewed by: neel (earlier version)
|
#
259482 |
|
16-Dec-2013 |
neel |
Add an API to deliver message signalled interrupts to vcpus. This allows callers treat the MSI 'addr' and 'data' fields as opaque and also lets bhyve implement multiple destination modes: physical, flat and clustered.
Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com) Reviewed by: grehan@
|
#
258494 |
|
23-Nov-2013 |
neel |
Add an ioctl to assert and deassert an ioapic pin atomically. This will be used to inject edge triggered legacy interrupts into the guest.
Start using the new API in device models that use edge triggered interrupts: viz. the 8254 timer and the LPC/uart device emulation.
Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
|
#
258075 |
|
12-Nov-2013 |
neel |
Move the ioapic device model from userspace into vmm.ko. This is needed for upcoming in-kernel device emulations like the HPET.
The ioctls VM_IOAPIC_ASSERT_IRQ and VM_IOAPIC_DEASSERT_IRQ are used to manipulate the ioapic pin state.
Discussed with: grehan@ Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
|
#
257767 |
|
06-Nov-2013 |
neel |
Fix an off-by-one error when iterating over the emulated PCI BARs.
Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
|
#
257293 |
|
29-Oct-2013 |
neel |
Add support for PCI-to-ISA LPC bridge emulation. If the LPC bus is attached to a virtual machine then we implicitly create COM1 and COM2 ISA devices.
Prior to this change the only way of attaching a COM port to the virtual machine was by presenting it as a PCI device that is mapped at the legacy I/O address 0x3F8 or 0x2F8.
There were some issues with the original approach: - It did not work at all with UEFI because UEFI will reprogram the PCI device BARs and remap the COM1/COM2 ports at non-legacy addresses. - OpenBSD GENERIC kernel does not create a /dev/console because it expects the uart device at the legacy 0x3F8/0x2F8 address to be an ISA device. - It was functional with a FreeBSD guest but caused the console to appear on /dev/ttyu2 which was not intuitive.
The uart emulation is now independent of the bus on which it resides. Thus it is possible to have uart devices on the PCI bus in addition to the legacy COM1/COM2 devices behind the LPC bus.
The command line option to attach ISA COM1/COM2 ports to a virtual machine is "-s <bus>,lpc -l com1,stdio".
The command line option to create a PCI-attached uart device is: "-s <bus>,uart[,stdio]"
The command line option to create PCI-attached COM1/COM2 device is: "-S <bus>,uart[,stdio]". This style of creating COM ports is deprecated.
Discussed with: grehan Reviewed by: grehan Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
M share/examples/bhyve/vmrun.sh AM usr.sbin/bhyve/legacy_irq.c AM usr.sbin/bhyve/legacy_irq.h M usr.sbin/bhyve/Makefile AM usr.sbin/bhyve/uart_emul.c M usr.sbin/bhyve/bhyverun.c AM usr.sbin/bhyve/uart_emul.h M usr.sbin/bhyve/pci_uart.c M usr.sbin/bhyve/pci_emul.c M usr.sbin/bhyve/inout.c M usr.sbin/bhyve/pci_emul.h M usr.sbin/bhyve/inout.h AM usr.sbin/bhyve/pci_lpc.c AM usr.sbin/bhyve/pci_lpc.h
|
#
256248 |
|
10-Oct-2013 |
grehan |
Allow a 4-byte write to PCI config space to overlap the 2 read-only bytes at the start of a PCI capability. This is the sequence that OpenBSD uses when enabling MSI interrupts, and works fine on real h/w.
In bhyve, convert the 4 byte write to a 2-byte write to the r/w area past the first 2 r/o bytes of a capability.
Reviewed by: neel Approved by: re@ (blanket)
|
#
256072 |
|
05-Oct-2013 |
neel |
Merge projects/bhyve_npt_pmap into head.
Make the amd64/pmap code aware of nested page table mappings used by bhyve guests. This allows bhyve to associate each guest with its own vmspace and deal with nested page faults in the context of that vmspace. This also enables features like accessed/dirty bit tracking, swapping to disk and transparent superpage promotions of guest memory.
Guest vmspace: Each bhyve guest has a unique vmspace to represent the physical memory allocated to the guest. Each memory segment allocated by the guest is mapped into the guest's address space via the 'vmspace->vm_map' and is backed by an object of type OBJT_DEFAULT.
pmap types: The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT.
The PT_X86 pmap type is used by the vmspace associated with the host kernel as well as user processes executing on the host. The PT_EPT pmap is used by the vmspace associated with a bhyve guest.
Page Table Entries: The EPT page table entries as mostly similar in functionality to regular page table entries although there are some differences in terms of what bits are used to express that functionality. For e.g. the dirty bit is represented by bit 9 in the nested PTE as opposed to bit 6 in the regular x86 PTE. Therefore the bitmask representing the dirty bit is now computed at runtime based on the type of the pmap. Thus PG_M that was previously a macro now becomes a local variable that is initialized at runtime using 'pmap_modified_bit(pmap)'.
An additional wrinkle associated with EPT mappings is that older Intel processors don't have hardware support for tracking accessed/dirty bits in the PTE. This means that the amd64/pmap code needs to emulate these bits to provide proper accounting to the VM subsystem. This is achieved by using the following mapping for EPT entries that need emulation of A/D bits: Bit Position Interpreted By PG_V 52 software (accessed bit emulation handler) PG_RW 53 software (dirty bit emulation handler) PG_A 0 hardware (aka EPT_PG_RD) PG_M 1 hardware (aka EPT_PG_WR)
The idea to use the mapping listed above for A/D bit emulation came from Alan Cox (alc@).
The final difference with respect to x86 PTEs is that some EPT implementations do not support superpage mappings. This is recorded in the 'pm_flags' field of the pmap.
TLB invalidation: The amd64/pmap code has a number of ways to do invalidation of mappings that may be cached in the TLB: single page, multiple pages in a range or the entire TLB. All of these funnel into a single EPT invalidation routine called 'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and sends an IPI to the host cpus that are executing the guest's vcpus. On a subsequent entry into the guest it will detect that the EPT has changed and invalidate the mappings from the TLB.
Guest memory access: Since the guest memory is no longer wired we need to hold the host physical page that backs the guest physical page before we can access it. The helper functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose.
PCI passthru: Guest's with PCI passthru devices will wire the entire guest physical address space. The MMIO BAR associated with the passthru device is backed by a vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that have one or more PCI passthru devices attached to them.
Limitations: There isn't a way to map a guest physical page without execute permissions. This is because the amd64/pmap code interprets the guest physical mappings as user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U shares the same bit position as EPT_PG_EXECUTE all guest mappings become automatically executable.
Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews as well as their support and encouragement.
Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing object for pci passthru mmio regions.
Special thanks to Peter Holm for testing the patch on short notice.
Approved by: re Discussed with: grehan Reviewed by: alc, kib Tested by: pho
|
#
254965 |
|
27-Aug-2013 |
neel |
Allow single byte reads of the emulated MSI-X tables. This is not required by the PCI specification but needed to dump MMIO space from "ddb" in the guest.
|
#
254395 |
|
16-Aug-2013 |
grehan |
Fix ordering of legacy IRQ reservations.
Submitted by: Jeremiah Lott jlott at averesystems dot com
|
#
252682 |
|
04-Jul-2013 |
grehan |
Support an optional "mac=" parameter to virtio-net config, to allow users to set the MAC address for a device.
Clean up some obsolete code in pci_virtio_net.c
Allow an error return from a PCI device emulation's init routine to be propagated all the way back to the top-level and result in the process exiting.
Submitted by: Dinakar Medavaram dinnu sun at gmail (original version)
|
#
252494 |
|
02-Jul-2013 |
grehan |
Fix up option parsing to allow a colon in the config section. Clean up some other unnecessary code.
Submitted by: Dinakar Medavaram dinnu sun at gmail Reviewed by: neel
|
#
252331 |
|
28-Jun-2013 |
grehan |
Allow the PCI config address register to be read. The Linux kernel does this. Also remove an unused header file.
Submitted by: tycho nightingale at pluribusnetworks com Reviewed by: neel
|
#
249916 |
|
26-Apr-2013 |
neel |
Gripe if some <slot,function> tuple is specified more than once instead of silently overwriting the previous assignment.
Gripe if the emulation is not recognized instead of silently ignoring the emulated device.
If an error is detected by pci_parse_slot() then exit from the command line parsing loop in main().
Submitted by (initial version): Chris Torek (chris.torek@gmail.com)
|
#
249572 |
|
17-Apr-2013 |
neel |
Setup accesses to the memory hole below 4GB to return all 1's on read and consume all writes without any side effects.
Obtained from: NetApp
|
#
249321 |
|
10-Apr-2013 |
neel |
Improve PCI BAR emulation: - Respect the MEMEN and PORTEN bits in the command register - Allow the guest to reprogram the address decoded by the BAR
Submitted by: Gopakumar T Obtained from: NetApp
|
#
248477 |
|
18-Mar-2013 |
neel |
Simplify the assignment of memory to virtual machines by requiring a single command line option "-m <memsize in MB>" to specify the memory size.
Prior to this change the user needed to explicitly specify the amount of memory allocated below 4G (-m <lowmem>) and the amount above 4G (-M <highmem>).
The "-M" option is no longer supported by 'bhyveload' and 'bhyve'.
The start of the PCI hole is fixed at 3GB and cannot be directly changed using command line options. However it is still possible to change this in special circumstances via the 'vm_set_lowmem_limit()' API provided by libvmmapi.
Submitted by: Dinakar Medavaram (initial version) Reviewed by: grehan Obtained from: NetApp
|
#
247144 |
|
22-Feb-2013 |
grehan |
Add the ability to have a 'fallback' search for memory ranges. These set of ranges will be looked at if a standard memory range isn't found, and won't be installed in the cache. Use this to implement the memory behaviour of the PCI hole on x86 systems, where writes are ignored and reads always return -1. This allows breakpoints to be set when issuing a 'boot -d', which has the side effect of accessing the PCI hole when changing the PTE protection on kernel code, since the pmap layer hasn't been initialized (a bug, but present in existing FreeBSD releases so has to be handled).
Reviewed by: neel Obtained from: NetApp
|
#
246846 |
|
15-Feb-2013 |
neel |
Advertise PCI-E capability in the hostbridge device presented to the guest.
FreeBSD wants to see this capability in at least one device in the PCI hierarchy before it allows use of MSI or MSI-X.
Obtained from: NetApp
|
#
246190 |
|
01-Feb-2013 |
neel |
Fix a bug in the passthru implementation where it would assume that all devices are MSI-X capable. This in turn would lead it to treat bar 0 as the MSI-X table bar even if the underlying device did not support MSI-X.
Fix this by providing an API to query the MSI-X table index of the emulated device. If the underlying device does not support MSI-X then this API will return -1.
Obtained from: NetApp
|
#
246109 |
|
30-Jan-2013 |
neel |
Add support for MSI-X interrupts in the virtio network device and make that the default.
The current behavior of advertising a single MSI vector can be requested by setting the environment variable "BHYVE_USE_MSI" to "true". The use of MSI is not compliant with the virtio specification and will be eventually phased out.
Submitted by: Gopakumar T Obtained from: NetApp
|
#
245678 |
|
20-Jan-2013 |
neel |
Add svn properties to the recently merged bhyve source files.
The pre-commit hook will not allow any commits without the svn:keywords property in head.
|
#
245652 |
|
19-Jan-2013 |
neel |
Merge projects/bhyve to head.
'bhyve' was developed by grehan@ and myself at NetApp (thanks!).
Special thanks to Peter Snyder, Joe Caradonna and Michael Dexter for their support and encouragement.
Obtained from: NetApp
|
#
244167 |
|
13-Dec-2012 |
grehan |
Rename fbsdrun.* -> bhyverun.*
bhyve is intended to be a generic hypervisor, and not FreeBSD-specific.
(renaming internal routines will come later)
Reviewed by: neel Obtained from: NetApp
|
#
242170 |
|
27-Oct-2012 |
neel |
Ignore PCI configuration accesses to all bus numbers other than PCI bus 0.
Obtained from: NetApp
|
#
242131 |
|
26-Oct-2012 |
grehan |
Remove mptable generation code from libvmmapi and move it to bhyve. Firmware tables require too much knowledge of system configuration, and it's difficult to pass that information in general terms to a library. The upcoming ACPI work exposed this - it will also livein bhyve.
Also, remove code specific to NetApp from the mptable name, and remove the -n option from bhyve.
Reviewed by: neel Obtained from: NetApp
|
#
241744 |
|
19-Oct-2012 |
grehan |
Rework how guest MMIO regions are dealt with.
- New memory region interface. An RB tree holds the regions, with a last-found per-vCPU cache to deal with the common case of repeated guest accesses to MMIO registers in the same page.
- Support memory-mapped BARs in PCI emulation.
mem.c/h - memory region interface
instruction_emul.c/h - remove old region interface. Use gpa from EPT exit to avoid a tablewalk to determine operand address. Determine operand size and use when calling through to region handler.
fbsdrun.c - call into region interface on paging exit. Distinguish between instruction emul error and region not found
pci_emul.c/h - implement new BAR callback api. Split BAR alloc routine into routines that require/don't require the BAR phys address.
ioapic.c pci_passthru.c pci_virtio_block.c pci_virtio_net.c pci_uart.c - update to new BAR callback i/f
Reviewed by: neel Obtained from: NetApp
|
#
239086 |
|
06-Aug-2012 |
neel |
Fix a bug in how a 64-bit bar in a pci passthru device would be presented to the guest. Prior to the fix it was possible for such a bar to appear as a 32-bit bar as long as it was allocated from the region below 4GB.
This had the potential to confuse some drivers that were particular about the size of the bars.
Obtained from: NetApp
|
#
239085 |
|
06-Aug-2012 |
neel |
Add support for emulating PCI multi-function devices.
These function number is specified by an optional [:<func>] after the slot number: -s 1:0,virtio-net,tap0
Ditto for the mptable naming: -n 1:0,e0a
Obtained from: NetApp
|
#
239045 |
|
05-Aug-2012 |
neel |
Device model for ioapic emulation.
With this change the uart emulation is entirely interrupt driven.
Obtained from: NetApp
|
#
239029 |
|
04-Aug-2012 |
neel |
Use the correct variable to index into the 'lirq[]' array to check the legacy IRQ ownership.
|
#
234938 |
|
03-May-2012 |
grehan |
Add 16550 uart emulation as a PCI device. This allows it to be activated as part of the slot config options. The syntax is:
-s <slotnum>,uart[,stdio]
The stdio parameter instructs the code to perform i/o using stdin/stdout. It can only be used for one instance. To allow legacy i/o ports/irqs to be used, a new variant of the slot command, -S, is introduced. When used to specify a slot, the device will use legacy resources if it supports them; otherwise it will be treated the same as the '-s' option. Specifying the -S option with the uart will first use the 0x3f8/irq 4 config, and the second -S will use 0x2F8/irq 3.
Interrupt delivery is awaiting the arrival of the i/o apic code, but this works fine in uart(4)'s polled mode.
This code was written by Cynthia Lu @ MIT while an intern at NetApp, with further work from neel@ and grehan@.
Obtained from: NetApp
|
#
234761 |
|
28-Apr-2012 |
grehan |
MSI-x interrupt support for PCI pass-thru devices.
Includes instruction emulation for memory r/w access. This opens the door for io-apic, local apic, hpet timer, and legacy device emulation.
Submitted by: ryan dot berryhill at sandvine dot com Reviewed by: grehan Obtained from: Sandvine
|
#
221942 |
|
15-May-2011 |
jhb |
First cut to port bhyve, vmmctl, and libvmmapi to HEAD.
|
#
221828 |
|
13-May-2011 |
grehan |
Import of bhyve hypervisor and utilities, part 1. vmm.ko - kernel module for VT-x, VT-d and hypervisor control bhyve - user-space sequencer and i/o emulation vmmctl - dump of hypervisor register state libvmm - front-end to vmm.ko chardev interface
bhyve was designed and implemented by Neel Natu.
Thanks to the following folk from NetApp who helped to make this available: Joe CaraDonna Peter Snyder Jeff Heller Sandeep Mann Steve Miller Brian Pawlowski
|