| #
303975 |
|
11-Aug-2016 |
gjb |
Copy stable/11@r303970 to releng/11.0 as part of the 11.0-RELEASE
cycle.
Prune svn:mergeinfo from the new branch, and rename it to RC1.
Update __FreeBSD_version.
Use the quarterly branch for the default FreeBSD.conf pkg(8) repo and
the dvd1.iso packages population.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation |
| #
302408 |
|
08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.
Additional commits post-branch will follow.
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation
|
| #
301621 |
|
08-Jun-2016 |
br |
Remove duplicate define.
|
| #
300618 |
|
24-May-2016 |
br |
Add initial DTrace support for RISC-V.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| #
298636 |
|
26-Apr-2016 |
br |
Add the non-standard "IO interrupt" vector used by lowRISC.
For now they provide UART irq only.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| #
296614 |
|
10-Mar-2016 |
br |
Add support for ddb(4).
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| #
295972 |
|
24-Feb-2016 |
br |
Add support for symmetric multiprocessing (SMP).
Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.
This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).
Invalidate entire TLB cache as it is the only way yet.
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
|
| #
294282 |
|
18-Jan-2016 |
br |
Correct RISC-V exception types.
|
| #
292407 |
|
17-Dec-2015 |
br |
Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.
Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4554
|