riscvreg.h revision 292407
1/*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/riscv/include/riscvreg.h 292407 2015-12-17 18:44:30Z br $ 35 */ 36 37#ifndef _MACHINE_RISCVREG_H_ 38#define _MACHINE_RISCVREG_H_ 39 40/* Machine mode requests */ 41#define ECALL_MTIMECMP 0x1 42#define ECALL_CLEAR_PENDING 0x2 43#define ECALL_HTIF_CMD 0x3 44#define ECALL_HTIF_GET_ENTRY 0x4 45#define ECALL_MCPUID_GET 0x5 46#define ECALL_MIMPID_GET 0x6 47 48#define EXCP_SHIFT 0 49#define EXCP_MASK (0xf << EXCP_SHIFT) 50#define EXCP_INSTR_ADDR_MISALIGNED 0 51#define EXCP_INSTR_ACCESS_FAULT 1 52#define EXCP_INSTR_ILLEGAL 2 53#define EXCP_INSTR_BREAKPOINT 3 54#define EXCP_RESERVED_0 4 55#define EXCP_LOAD_ACCESS_FAULT 5 56#define EXCP_AMO_ADDR_MISALIGNED 6 57#define EXCP_STORE_ACCESS_FAULT 7 58#define EXCP_ENV_CALL 8 59#define EXCP_RESERVED_1 9 60#define EXCP_INTR (1 << 31) 61#define EXCP_INTR_SOFTWARE 0 62#define EXCP_INTR_TIMER 1 63#define EXCP_INTR_HTIF 2 64 65#define SSTATUS_IE (1 << 0) 66#define SSTATUS_PIE (1 << 3) 67#define SSTATUS_PS (1 << 4) 68 69#define MSTATUS_MPRV (1 << 16) 70#define MSTATUS_PRV_SHIFT 1 71#define MSTATUS_PRV1_SHIFT 4 72#define MSTATUS_PRV2_SHIFT 7 73#define MSTATUS_PRV_MASK (0x3 << MSTATUS_PRV_SHIFT) 74#define MSTATUS_PRV_U 0 /* user */ 75#define MSTATUS_PRV_S 1 /* supervisor */ 76#define MSTATUS_PRV_H 2 /* hypervisor */ 77#define MSTATUS_PRV_M 3 /* machine */ 78 79#define MSTATUS_VM_SHIFT 17 80#define MSTATUS_VM_MASK 0x1f 81#define MSTATUS_VM_MBARE 0 82#define MSTATUS_VM_MBB 1 83#define MSTATUS_VM_MBBID 2 84#define MSTATUS_VM_SV32 8 85#define MSTATUS_VM_SV39 9 86#define MSTATUS_VM_SV48 10 87 88#define MIE_SSIE (1 << 1) 89#define MIE_HSIE (1 << 2) 90#define MIE_MSIE (1 << 3) 91#define MIE_STIE (1 << 5) 92#define MIE_HTIE (1 << 6) 93#define MIE_MTIE (1 << 7) 94 95#define MIP_SSIP (1 << 1) 96#define MIP_HSIP (1 << 2) 97#define MIP_MSIP (1 << 3) 98#define MIP_STIP (1 << 5) 99#define MIP_HTIP (1 << 6) 100#define MIP_MTIP (1 << 7) 101 102#define SR_IE (1 << 0) 103#define SR_IE1 (1 << 3) 104#define SR_IE2 (1 << 6) 105#define SR_IE3 (1 << 9) 106 107#define SIE_SSIE (1 << 1) 108#define SIE_STIE (1 << 5) 109 110/* Note: sip register is not yet implement in Spike simulator */ 111#define SIP_STIP (1 << 5) 112 113#define CSR_ZIMM(val) \ 114 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 115 116#define csr_swap(csr, val) \ 117({ if (CSR_ZIMM(val)) \ 118 __asm __volatile("csrrwi %0, " #csr ", %1" \ 119 : "=r" (val) : "i" (val)); \ 120 else \ 121 __asm __volatile("csrrw %0, " #csr ", %1" \ 122 : "=r" (val) : "r" (val)); \ 123 val; \ 124}) 125 126#define csr_write(csr, val) \ 127({ if (CSR_ZIMM(val)) \ 128 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 129 else \ 130 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 131}) 132 133#define csr_set(csr, val) \ 134({ if (CSR_ZIMM(val)) \ 135 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 136 else \ 137 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 138}) 139 140#define csr_clear(csr, val) \ 141({ if (CSR_ZIMM(val)) \ 142 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 143 else \ 144 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 145}) 146 147#define csr_read(csr) \ 148({ u_long val; \ 149 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 150 val; \ 151}) 152 153#endif /* !_MACHINE_RISCVREG_H_ */ 154