Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.

ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.

Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.

Loves it: imp

sys/arm: Minor spelling fixes.

Only affects comments: no functional change.

ARM: Convert spaces to tabs, fix formatting.
Not a functional change.

ARM: Next round of cleanup in swtch-v*.S.
- remove now useless #if __ARM_ARCH conditional
- use macro for accessing CP15 registers
- remove unused PCPU_SIZE

Pointed by: kib

ARM: Split swtch.S into common, ARMv4 and ARMv6 parts. Cleanup them.

ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.

This patch only removes old code from tree. Cleanups will follow asap.

Stop checking for ARM_TP_ADDRESS when we mean to check if building for
ARMv6 or later.

Remove trailing whitespace from sys/arm/arm

Retire pmap_lazyfix(). This function only existed in the new armv6 pmap
because the i386 pmap on which the new armv6 pmap is based had it, and in
r281707 pmap_lazyfix() was removed from the i386 pmap.

Discussed with: kib
Submitted by: Michal Meloun (via Svatopluk Kraus)

Use the ACLE spelling of _ARM_ARCH_6: "__ARM_ARCH >= 6"

New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.

This is pretty much a complete rewrite based on the existing i386 code. The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.

After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>

Do not save/restore the TLS pointer on context switch for armv6. The
pointer cannot be changed directly by userland code on armv6 (it can be on
armv4), so there's no need to save/restore.

Submitted by: Michal Meloun

Cleanup up ARM *frame structures...

- Eliminate unused irqframe
- Eliminate unused saframe
- Instead of splitting r4-sp storage between the stack and switchframe,
just put all the registers in switchframe and eliminate the un_32 struct.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>

Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros. That means that now all references
to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S,
so move the macros themselves into there and remove them from asmacros.h

Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

Always call vfp_discard() on thread death, not just when the VFP is
enabled. In vfp_discard(), if the state in the VFP hardware belongs to
the thread which is dying, NULL out pcpu fpcurthread to indicate the
state currently in the hardware belongs to nobody.

Submitted by: Juergen Weiss
Pointy hat to: me

Remove all dregs of a per-thread undefined-exception-mode stack. This is
a leftover from the days when a low-level debugger had hooks in the
undefined exception vector and needed stack space to function. These days
it effectively isn't used because we switch immediately to the svc32 mode
stack on exception entry. For that, the single undef mode stack per core
that gets set up at init time works fine.

The stack wasn't necessary but it was harmful, because the space for it
was carved out of the normal per-thread svc32 stack, in effect cutting
that 8K stack in half. If svc32 mode used more than 4k of stack space it
wandered down into the undef mode stack, and then an undef exception would
overwrite a couple words on the stack while switching to svc32 mode,
corrupting the scv32 stack. Having another stack abut the bottom of the
svc32 stack also effectively mooted the guard page below the stack.

This work is based on analysis and patches submitted by Juergen Weiss.

Rework the VFP code that handles demand-based save and restore of state.

The old code was full of complexity that would only matter if the
kernel itself used the VFP hardware. Now that's reduced to either killing
the userland process or panicking the kernel on an illegal VFP instruction.

This removes most of the complexity from the assembler code, reducing it
to just calling the save code if the outgoing thread used the VFP.

The routine that stores the VFP state now takes a flag that indicates
whether the hardware should be disabled after saving state. Right now it
always is, but this makes the code ready to be used by get/set_mcontext()
(doing so will be addressed in a future commit).

Remove the arm-specific pc_vfpcthread from struct pcpu and use the MI
field pc_fpcurthread instead.

Reviewed by: cognet

Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu,
such as the one found in the RPi, don't have it, and just hang when we try
to access it.

Change the way pcpu and curthread are stored per-core:
the old way was to store pcpu in a register, and get curthread from pcpu,
which is not very atomic, and led to issues if the thread was migrated
to another core between the time we got the pcpu address and the time we
got curthread.
Instead, we now store curthread where pcpu used to be store, and we
calculate the pcpu address based on the cpu id.

Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.

Approved by: stas (mentor)

Add the frame information to cpu_switch to allow us to unwind out of it,
for example when dumping threads in the kernel debugger.

Rename device vfp to option VFP and retire the ARM_VFP_SUPPORT option. This
simplifies enabling as previously both options were required to be enabled,
now we only need a single option.

While here enable VFP on the PandaBoard.

Remove the ARMFPE option. It is unsupported, and appears to be broken as
arm_fpe_core_changecontext is not a function.

Insert STOP_UNWINDING directives in the _start (kernel entry point) and
fork_trampoline (thread entry point) assembler routines, because it's
not possible to unwind beyond those points.

Also insert STOP_UNWINDING in the exception_exit routine, to prevent an
unwind-loop at that point. This is just a stopgap until we get around
to instrumenting all assembler functions with proper unwind metadata.

Add an END macro to ARM. This is mostly used to tell gas where the bounds
of the functions are when creating the EABI unwind tables.

Fix stack alignment in the kernel to be on an 8 byte boundary as required
by AAPCS.

Only spin on the blocked_lock for SCHED_ULE+SMP, as it's done on the other
arches.

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms

Final whitespace trim.

Oops. ARM_RAS_END is ARM_TP_ADDRESS + 8, not 4.

Spotted out by: Mark Tinguely <tinguely at casselton d0t net>

To prevent various race conditions in the RAS code, store and restore the
values in ARM_RAS_START and ARM_RAS_END at context switch time.

MFC after: 1 week

Eliminate flushing of L2 cache in ARM context switch routines.

With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.

Pointed out by: cognet

Provide L2 cache synchronization (write back + invalidation) on ARM.

Note the cpu_l2cache_wbinv_* routines are no-ops on systems not populated with
L2 caches.

Obtained from: Marvell, Semihalf

Store the PC while context switching, for the benefits of DDB.

Improve ARM_TP_ADDRESS and RAS area.

De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this
special purpose page to a more convenient place i.e. after the vectors high
page, more towards the end of address space. Previous location (0xe000_0000)
caused grief if KVA was to go beyond the default limit.

Note that ARM world rebuilding is required after this change since the
location of ARM_TP_ADDRESS is shared between kernel and userland.

Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com)
Reviewed by: imp
Approved by: cognet (mentor)

Do not use __XSCALE__ to detect if pld/strd/ldrd is available, use
_ARM_ARCH_5E instead.

MFC After: 3 days

Use the third argument of cpu_switch(), as done for i386/amd63, as it is
required for ULE.

Approved by: re (blanket)

Not only disable/enable interrupts, do it for FIQs as well, when needed.

Remove a never reached RET.

strd needs the destination to be double-word aligned, but the pointer passed
to savectx isn't always, so always use stmia, savectx isn't called enough
to need that kind of optimization.

Implement savectx().

Obtained from: NetBSD

Write back affected pages in pmap_qremove() as well. This removes the need
to change the DACR when switching to a kernel thread, thus making
userland thread => kernel thread => same userland thread switch cheaper by
totally avoiding data cache and TLB invalidation.

Use [ldr|str]t instead of [ldr|str] when accessing ARM_TP_ADDRESS.

In cpu_throw(), correctly calculate td->td_md.md_tp.
In cpu_switch(), set the DACR even if we're switching to a kernel thread.

Instead of using sysarch() to store-retrieve the tp, add a magic address,
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache
line will be allocated and locked for this address, so that it will never go
to RAM. On CPUs that does not, a page is allocated for it (it will be a bit
slower, and is wrong for SMP, but should be fine for UP).
The tp is still stored in the mdthread struct, and at each context switch,
ARM_TP_ADDRESS gets updated.

Suggested by: davidxu

Start all license statements with /*-

Update the sp after popping the regs.
This is a good candidate for the golden pointy hat awards.

Save a few more cycles in cpu_switch() and cpu_throw().

Do not change the page directory and do not flush the TLB when switching to
a kernel thread.

Set the frame pointer to 0 in fork_trampoline().

Use the RET macro.

Remove useless code.

Save a few cycles in context switch.
Update comments to reflect reality.

Remove dead code.

Implement cpu_throw().

Obtained from: NetBSD

Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.