swtch-v4.S revision 295090
1/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2 3/*- 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/*- 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 * 79 */ 80 81#include "assym.s" 82#include "opt_sched.h" 83 84#include <machine/acle-compat.h> 85#include <machine/asm.h> 86#include <machine/asmacros.h> 87#include <machine/armreg.h> 88#include <machine/vfp.h> 89 90__FBSDID("$FreeBSD: head/sys/arm/arm/swtch-v4.S 295090 2016-01-31 08:53:53Z mmel $"); 91 92 93#define GET_PCPU(tmp, tmp2) \ 94 ldr tmp, .Lcurpcpu 95 96#ifdef VFP 97 .fpu vfp /* allow VFP instructions */ 98#endif 99 100.Lcurpcpu: 101 .word _C_LABEL(__pcpu) 102.Lblocked_lock: 103 .word _C_LABEL(blocked_lock) 104 105 106#define DOMAIN_CLIENT 0x01 107 108.Lcpufuncs: 109 .word _C_LABEL(cpufuncs) 110 111/* 112 * cpu_throw(oldtd, newtd) 113 * 114 * Remove current thread state, then select the next thread to run 115 * and load its state. 116 * r0 = oldtd 117 * r1 = newtd 118 */ 119ENTRY(cpu_throw) 120 mov r5, r1 121 122 /* 123 * r0 = oldtd 124 * r5 = newtd 125 */ 126 127#ifdef VFP /* This thread is dying, disable */ 128 bl _C_LABEL(vfp_discard) /* VFP without preserving state. */ 129#endif 130 131 GET_PCPU(r7, r9) 132 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 133 134 /* Switch to lwp0 context */ 135 136 ldr r9, .Lcpufuncs 137 mov lr, pc 138 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 139 ldr r0, [r7, #(PCB_PL1VEC)] 140 ldr r1, [r7, #(PCB_DACR)] 141 /* 142 * r0 = Pointer to L1 slot for vector_page (or NULL) 143 * r1 = lwp0's DACR 144 * r5 = lwp0 145 * r7 = lwp0's PCB 146 * r9 = cpufuncs 147 */ 148 149 /* 150 * Ensure the vector table is accessible by fixing up lwp0's L1 151 */ 152 cmp r0, #0 /* No need to fixup vector table? */ 153 ldrne r3, [r0] /* But if yes, fetch current value */ 154 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 155 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 156 cmpne r3, r2 /* Stuffing the same value? */ 157 strne r2, [r0] /* Store if not. */ 158 159#ifdef PMAP_INCLUDE_PTE_SYNC 160 /* 161 * Need to sync the cache to make sure that last store is 162 * visible to the MMU. 163 */ 164 movne r1, #4 165 movne lr, pc 166 ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 167#endif /* PMAP_INCLUDE_PTE_SYNC */ 168 169 /* 170 * Note: We don't do the same optimisation as cpu_switch() with 171 * respect to avoiding flushing the TLB if we're switching to 172 * the same L1 since this process' VM space may be about to go 173 * away, so we don't want *any* turds left in the TLB. 174 */ 175 176 /* Switch the memory to the new process */ 177 ldr r0, [r7, #(PCB_PAGEDIR)] 178 mov lr, pc 179 ldr pc, [r9, #CF_CONTEXT_SWITCH] 180 181 GET_PCPU(r6, r4) 182 /* Hook in a new pcb */ 183 str r7, [r6, #PC_CURPCB] 184 /* We have a new curthread now so make a note it */ 185 str r5, [r6, #PC_CURTHREAD] 186 187 /* Set the new tp */ 188 ldr r6, [r5, #(TD_MD + MD_TP)] 189 ldr r4, =ARM_TP_ADDRESS 190 str r6, [r4] 191 ldr r6, [r5, #(TD_MD + MD_RAS_START)] 192 str r6, [r4, #4] /* ARM_RAS_START */ 193 ldr r6, [r5, #(TD_MD + MD_RAS_END)] 194 str r6, [r4, #8] /* ARM_RAS_END */ 195 196 /* Restore all the saved registers and exit */ 197 add r3, r7, #PCB_R4 198 ldmia r3, {r4-r12, sp, pc} 199END(cpu_throw) 200 201/* 202 * cpu_switch(oldtd, newtd, lock) 203 * 204 * Save the current thread state, then select the next thread to run 205 * and load its state. 206 * r0 = oldtd 207 * r1 = newtd 208 * r2 = lock (new lock for old thread) 209 */ 210ENTRY(cpu_switch) 211 /* Interrupts are disabled. */ 212 /* Save all the registers in the old thread's pcb. */ 213 ldr r3, [r0, #(TD_PCB)] 214 215 /* Restore all the saved registers and exit */ 216 add r3, #(PCB_R4) 217 stmia r3, {r4-r12, sp, lr, pc} 218 219 mov r6, r2 /* Save the mutex */ 220 221 /* rem: r0 = old lwp */ 222 /* rem: interrupts are disabled */ 223 224 /* Process is now on a processor. */ 225 /* We have a new curthread now so make a note it */ 226 GET_PCPU(r7, r2) 227 str r1, [r7, #PC_CURTHREAD] 228 229 /* Hook in a new pcb */ 230 ldr r2, [r1, #TD_PCB] 231 str r2, [r7, #PC_CURPCB] 232 233 /* Stage two : Save old context */ 234 235 /* Get the user structure for the old thread. */ 236 ldr r2, [r0, #(TD_PCB)] 237 mov r4, r0 /* Save the old thread. */ 238 239 /* Store the old tp; userland can change it on armv4. */ 240 ldr r3, =ARM_TP_ADDRESS 241 ldr r9, [r3] 242 str r9, [r0, #(TD_MD + MD_TP)] 243 ldr r9, [r3, #4] 244 str r9, [r0, #(TD_MD + MD_RAS_START)] 245 ldr r9, [r3, #8] 246 str r9, [r0, #(TD_MD + MD_RAS_END)] 247 248 /* Set the new tp */ 249 ldr r9, [r1, #(TD_MD + MD_TP)] 250 str r9, [r3] 251 ldr r9, [r1, #(TD_MD + MD_RAS_START)] 252 str r9, [r3, #4] 253 ldr r9, [r1, #(TD_MD + MD_RAS_END)] 254 str r9, [r3, #8] 255 256 /* Get the user structure for the new process in r9 */ 257 ldr r9, [r1, #(TD_PCB)] 258 259 /* rem: r2 = old PCB */ 260 /* rem: r9 = new PCB */ 261 /* rem: interrupts are enabled */ 262 263#ifdef VFP 264 fmrx r0, fpexc /* If the VFP is enabled */ 265 tst r0, #(VFPEXC_EN) /* the current thread has */ 266 movne r1, #1 /* used it, so go save */ 267 addne r0, r2, #(PCB_VFPSTATE) /* the state into the PCB */ 268 blne _C_LABEL(vfp_store) /* and disable the VFP. */ 269#endif 270 271 /* r0-r3 now free! */ 272 273 /* Third phase : restore saved context */ 274 275 /* rem: r2 = old PCB */ 276 /* rem: r9 = new PCB */ 277 278 ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 279 mov r2, #DOMAIN_CLIENT 280 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 281 beq .Lcs_context_switched /* Yup. Don't flush cache */ 282 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 283 /* 284 * Get the new L1 table pointer into r11. If we're switching to 285 * an LWP with the same address space as the outgoing one, we can 286 * skip the cache purge and the TTB load. 287 * 288 * To avoid data dep stalls that would happen anyway, we try 289 * and get some useful work done in the mean time. 290 */ 291 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 292 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 293 294 teq r10, r11 /* Same L1? */ 295 cmpeq r0, r5 /* Same DACR? */ 296 beq .Lcs_context_switched /* yes! */ 297 298 /* 299 * Definately need to flush the cache. 300 */ 301 302 ldr r1, .Lcpufuncs 303 mov lr, pc 304 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 305 306.Lcs_cache_purge_skipped: 307 /* rem: r6 = lock */ 308 /* rem: r9 = new PCB */ 309 /* rem: r10 = old L1 */ 310 /* rem: r11 = new L1 */ 311 312 mov r2, #0x00000000 313 ldr r7, [r9, #(PCB_PL1VEC)] 314 315 /* 316 * Ensure the vector table is accessible by fixing up the L1 317 */ 318 cmp r7, #0 /* No need to fixup vector table? */ 319 ldrne r2, [r7] /* But if yes, fetch current value */ 320 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 321 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 322 cmpne r2, r0 /* Stuffing the same value? */ 323#ifndef PMAP_INCLUDE_PTE_SYNC 324 strne r0, [r7] /* Nope, update it */ 325#else 326 beq .Lcs_same_vector 327 str r0, [r7] /* Otherwise, update it */ 328 329 /* 330 * Need to sync the cache to make sure that last store is 331 * visible to the MMU. 332 */ 333 ldr r2, .Lcpufuncs 334 mov r0, r7 335 mov r1, #4 336 mov lr, pc 337 ldr pc, [r2, #CF_DCACHE_WB_RANGE] 338 339.Lcs_same_vector: 340#endif /* PMAP_INCLUDE_PTE_SYNC */ 341 342 cmp r10, r11 /* Switching to the same L1? */ 343 ldr r10, .Lcpufuncs 344 beq .Lcs_same_l1 /* Yup. */ 345 /* 346 * Do a full context switch, including full TLB flush. 347 */ 348 mov r0, r11 349 mov lr, pc 350 ldr pc, [r10, #CF_CONTEXT_SWITCH] 351 352 b .Lcs_context_switched 353 354 /* 355 * We're switching to a different process in the same L1. 356 * In this situation, we only need to flush the TLB for the 357 * vector_page mapping, and even then only if r7 is non-NULL. 358 */ 359.Lcs_same_l1: 360 cmp r7, #0 361 movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 362 movne lr, pc 363 ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 364 365.Lcs_context_switched: 366 367 /* Release the old thread */ 368 str r6, [r4, #TD_LOCK] 369 370 /* XXXSCW: Safe to re-enable FIQs here */ 371 372 /* rem: r9 = new PCB */ 373 374 /* Restore all the saved registers and exit */ 375 add r3, r9, #PCB_R4 376 ldmia r3, {r4-r12, sp, pc} 377END(cpu_switch) 378