Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

MFC r320387:

[arm] Use correct index value when checking range validity

Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D9145

MFC r317428 (cognet): fix arm64 MSI

In arm_gicv2m_alloc_msi(), if we found a suitable irq range, leave the loop
before we increase irq again, or we'd end up choosing an irq, and then
really using the next one, even if it's not available.
Also in the inner loop, correct the end check so that we check every irq,
even the last one.
This makes the msk(4) adapter able to use MSI on Softiron Overdrive 1000.

PR: 219956
Approved by: re (gjb)

MFC r306899, r307059, r307151

r306899:
Fix release MSI method for ARM GIC

r307059:
INTRNG - fix MSI/MSIX release path

Use isrc in attached MSI data structure instead of using map's
isrc directly. map's isrc is set to NULL on IRQ deactivation
which happens prior to pci_release_msi so MSI_RELEASE_MSI
receives array of NULLs

Reviewed by: mmel
Differential Revision: https://reviews.freebsd.org/D8206

r307151:
INTRNG: Propagate IRQ activation error to API consumer

Keep resource state consistent with INTRNG state - if intr_activate_irq
fails - deactivate resource and propagate error to calling function

Reviewed by: mmel

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Define irq variable only in the block where used.

arm_gic_map is a mask not the CPUs ID, there is no need to shift it.

Pointy-hat to: andrew
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Bin interrupts to the correct CPU when we boot on a non-zero CPU.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

ARM GIC: Allow to setup interrupt without configuration data.
In some cases, like for PCI devices, only interrupt numbers are enumerated
from HW. In this case, use INTR_foo_CONFORM as level and trigger values.

Return the struct intr_pic pointer from intr_pic_register. This will be
needed in later changes where we may not be able to lock the pic list lock
to perform a lookup, e.g. from within interrupt context.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

The GIC (v2 at least) has a bit in the TYPER register to indicate whether the GIC
supports the Security Extensions or not. This bit is not the same as the CPU one.
Currently we are not checking for either before trying to write to the special
registers. This can lead to problems on hardware or simulators that do not
provide the security extensions. Add the missing checks. Their interactions with
the CPU flag is not entirely clear to me but using a macro will make it easier
to quickly adjust the condition once the CPU bits are sorted as well.

Reviewed by: br
Sponsored by: DARPA/AFRL
Differential Revision: https://reviews.freebsd.org/D6397

Introduce MSI and MSI-X support to intrng. This adds a new msi device
interface with 5 methods to mirror the 5 MSI/MSI-X methods in the pcib
interface. The pcib driver will need to perform a device specific lookup
to find the MSI controller and pass this to intrng as the xref. Intrng
will finally find the controller and have it handle the requested operation.

Obtained from: ABT Systems Ltd
MFH: yes
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5985

INTRNG - redefine struct intr_map_data to avoid headers pollution. Each
struct associated with some type defined in enum intr_map_data_type
must have struct intr_map_data on the top of its own definition now.
When such structs are used, correct type and size must be filled in.

There are three such structs defined in sys/intr.h now. Their
definitions should be moved to corresponding headers by follow-up
commits.

While this change was propagated to all INTRNG like PICs,
pic_map_intr() method implementations were corrected on some places.
For this specific method, it's ensured by a caller that the 'data'
argument passed to this method is never NULL. Also, the return error
values were standardized there.

sys/arm: Minor spelling fixes.

Only affects comments: no functional change.

Make the GIC SGI global variables static, they are only ever used within
within this file.

Approved by: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Add a flag field to struct gic_irqsrc and use it to mark when we should
write to the End of Interrupt (EOI) register before handling the interrupt.
This should be a noop as it will be set for all edge triggered interrupts,
however this will not be the case for MSI interrupts. These are also edge
triggered, however we should not write to the EOI register until later in
arm_gic_pre_ithread.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Add initial GICv2m support to the arm GIC driver. This will be used to
support MSI and MSI-X interrupts, however intrng needs updates before this
can happen.

For now we just attach the driver until the MSI API is ready.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5950

Properly initialize isrc_cpu field of ISRC which is setup for an IPI.

Implement intr_isrc_init_on_cpu() and use it to replace very same
code implemented in every interrupt controller driver running SMP.
This function returns true, if provided ISRC should be enabled on
given cpu.

Add a table to map from the FreeBSD CPUID space to the GIC CPUID space. On
many SoCs these two are the same, however there is no requirement for this
to be the case, e.g. on the ARM Juno we boot on what the GIC thinks of as
CPU 2, but FreeBSD numbers it CPU 0.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Remove FDT specific parts from INTRNG. Change its interface to make it
universal.

(1) New struct intr_map_data is defined as a container for arbitrary
description of an interrupt used by a device. Typically, an interrupt
number and configuration relevant to an interrupt controller is encoded
in such description. However, any additional information may be encoded
too like a set of cpus on which an interrupt should be enabled or vendor
specific data needed for setup of an interrupt in controller. The struct
intr_map_data itself is meant to be opaque for INTRNG.

(2) An intr_map_irq() function is created which takes an interrupt
controller identification and struct intr_map_data as arguments and
returns global interrupt number which identifies an interrupt.

(3) A set of functions to be used by bus drivers is created as well as
a corresponding set of methods for interrupt controller drivers. These
sets take both struct resource and struct intr_map_data as one of the
arguments. There is a goal to keep struct intr_map_data in struct
resource, however, this way a final solution is not limited to that.

(4) Other small changes are done to reflect new situation.

This is only first step aiming to create stable interface for interrupt
controller drivers. Thus, some temporary solution is taken. Interrupt
descriptions for devices are stored in INTRNG and two specific mapping
function are created to be temporary used by bus drivers. That's why
the struct intr_map_data is not opaque for INTRNG now. This temporary
solution will be replaced by final one in next step.

Differential Revision: https://reviews.freebsd.org/D5730

Read the CPU ID for the current CPU from the GIC. The GIC may have a
different ID space than the kernel. Because of this we need to read the
ID from the hardware. The hardware will provide this value to the CPU by
reading any of the first 8 Interrupt Processor Targets Registers.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5706

Generalize IPI support for ARM intrng and use it for interrupt
controller IPI provider.

New struct intr_ipi is defined which keeps all info about an IPI:
its name, counter, send and dispatch methods. Generic intr_ipi_setup(),
intr_ipi_send() and intr_ipi_dispatch() functions are implemented.

An IPI provider must implement two functions:
(1) an intr_ipi_send_t function which is able to send an IPI,
(2) a setup function which initializes itself for an IPI and
calls intr_ipi_setup() with appropriate arguments.

Differential Revision: https://reviews.freebsd.org/D5700

Fix GIC interrupt decoding in INTRNG code

Bug was already fixed in not-INTRNG code, it needs to be corrected
here as well. Source: https://reviews.freebsd.org/rS294422

Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: cognet, wma
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D5029

Fix GIC FDT interrupts decoding

Interrupt type in FDT was interpreted incorrectly.
Patch taken from freebsd-arm thread 'GIC - interrupts interpretation in
DTS/FDT':
https://lists.freebsd.org/pipermail/freebsd-arm/2015-August/012145.html

Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4215

[intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.

The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.

* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.

Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.

Tested:

* make universe

TODO:

* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)

Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.

* Kan has requested I make the PIC based IPI stuff optional.

ARM: Fix of detection of root interrupt controller.
This fixes detection of root interrupt controller for cases,
when interrupt parent is not defined at all or it's not defined directly
in controller node.

Approved by: kib (mentor)

ARM: Cumulative fixes for GIC
- fix detection of interrupt root controller
- allow (but warn) unsupported configuration bits
- dont send EOI for spurious interrupts
- print more informations for spurious interrupts
- use device_printf() where appropriate

Reviewed by: ian (earlier version)
Approved by: kib (mentor)

Move arm_gic_bind() out of the #ifdef SMP block to fix compile errors in
the not-SMP case. This is safe because arm_irq_next_cpu() will return
the cpuid of the current/only core in the not-SMP case.

Submitted by: Bartosz Szczepanek @ semihalf

Uncomment some rather important code that was commented out for benchmarking.
Normally this routine is supposed to loop until the PIC returns a "no more
interrupts pending" indication. I had commented that out to do just one
interrupt per invokation to do some timing tests.

Spotted by: Svata Kraus
Pointy Hat: ian

Only decode fdt data which belongs to the GIC controller.

The interrupts-extended property is a list of controller-specific
interrupt tuples for more than one controller. The decode routine of
every PIC gets called in the pre-INTRNG code (nexus doesn't know which
device instance belongs to which fdt node), so the GIC code has to
check each FDT node it is asked to decode to ensure it is the owner.

Because in the pre-INTRNG world there can only be one instance of a GIC,
it's safe to cache the results of a positive lookup in a static variable
to avoid the expensive lookups on subsequent calls.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Differential Revision: https://reviews.freebsd.org/D2345

Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt). The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.

Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code. In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.

This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012. That didn't get committed right away and
the source base evolved out from under it to some degree. In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while. Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges. Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC. The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.

Differential Revision: https://reviews.freebsd.org/D2047

Rename arm_init_secondary_ic() -> arm_pic_init_secondary(). The latter is
the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.

Remove trailing whitespace from sys/arm/arm

Add necessary changes to support various Amlogic SoC devices
specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.

The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer

Submitted by: John Wehle
Approved by: stas (mentor)

Fix endianness on FDT read in ARM GIC

Submitted by: Jakub Palider <jpa@semihalf.com>
Reviewed by: ian, nwhitehorn
Obtained from: Semihalf

Rename gic_init_secondary to arm_init_secondary_ic to help with the merge
of the arm_intrng project branch.

Rework the GIC driver to ease the import of the arm_intrng branch. The
common code has been pulled out to static functions.

Rename pic_ipi_get to pic_ipi_read for intrng.

Further reduce the diff between the arm_intrng gic driver and the version
in head.

Reduce the diff to the arm_intrng project branch by having the read/write
macros take the softc they are accessing.

Fix typo in ARM GIC device_printf()

Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation

The private peripheral interrupts start at offset 16, not 0. Also, use
names rather than inline mystery constants for these offsets.

Pointed out by: andrew

Add a common routine for parsing FDT data describing an ARM GIC interrupt.

In the fdt data we've written for ourselves, the interrupt properties
for GIC interrupts have just been a bare interrupt number. In standard
data that conforms to the published bindings, GIC interrupt properties
contain 3-tuples that describe the interrupt as shared vs private, the
interrupt number within the shared/private address space, and configuration
info such as level vs edge triggered.

The new gic_decode_fdt() function parses both types of data, based on the
#interrupt-cells property. Previously, each platform implemented a decode
routine and put a pointer to it into fdt_pic_table. Now they can just
list this function in their table instead if they use arm/gic.c.

Add compat strings for all the flavors of GIC this driver should support.
Also allow the driver to attach to ofwbus as well as simplebus, some FDT
data puts the root interrupt controller on the root bus.

Add the virtual timer irq to the list of interrupts we enable on secondary
cores.

Attach arm generic interrupt and timer drivers in the middle of
BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.

Activate IRQ 30 (non-secure private timer IRQ) for case we are running
in non-secure state.

Eliminate one of the causes of spurious interrupts on armv6. The arm weak
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.

This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.

Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after: 3 days

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.

Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.

Add polarity and level support to ARM GIC

Add suport for setting triggering level and polarity in GIC.
New function pointer was added to nexus which corresponds
to the function which sets level/sense in the hardware (GIC).

Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf

Do not EOI an interrupt until the point after the filter handlers / before
threaded handlers.

It's not easy to see from the diffs of this change exactly how it
accomplishes the above. The arm_mask_irq() and arm_unmask_irq() functions
are, respectively, the pre_thread and post_thread hooks. Not seen in
these diffs, the arm_post_filter() routine also EOIs. The post_filter
routine runs after filter handlers if there will be no threaded handlers,
so it just EOIs. The pre_thread routine masks the interrupt (at the
controller, not the source) and EOIs. So one way or another, the EOI
happens at the point where filter handlers are done.

Only receive the interrupts on the first core, to avoid duplicate interrupts.

o Initialize interrupt groups as Group 0 (secure interrupts).
o Minor cleanup.

Submitted by: Ruslan Bukin <br@bsdpad.com>

Initialize GIC_PMRR register on ARM GIC.

Provided by: Thomas Skibo

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms