gic.c revision 297539
1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Damjan Marion <damjan.marion@gmail.com> 6 * 7 * Based on OMAP4 GIC code by Ben Gray 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the company nor the name of the author may be used to 18 * endorse or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/arm/arm/gic.c 297539 2016-04-04 09:15:25Z skra $"); 36 37#include "opt_platform.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/bus.h> 42#include <sys/kernel.h> 43#include <sys/ktr.h> 44#include <sys/module.h> 45#include <sys/malloc.h> 46#include <sys/rman.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/cpuset.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/smp.h> 53#ifdef ARM_INTRNG 54#include <sys/sched.h> 55#endif 56#include <machine/bus.h> 57#include <machine/intr.h> 58#include <machine/smp.h> 59 60#include <dev/fdt/fdt_common.h> 61#include <dev/ofw/openfirm.h> 62#include <dev/ofw/ofw_bus.h> 63#include <dev/ofw/ofw_bus_subr.h> 64 65#ifdef ARM_INTRNG 66#include "pic_if.h" 67#endif 68 69#define GIC_DEBUG_SPURIOUS 70 71/* We are using GICv2 register naming */ 72 73/* Distributor Registers */ 74#define GICD_CTLR 0x000 /* v1 ICDDCR */ 75#define GICD_TYPER 0x004 /* v1 ICDICTR */ 76#define GICD_IIDR 0x008 /* v1 ICDIIDR */ 77#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */ 78#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */ 79#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */ 80#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */ 81#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */ 82#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */ 83#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */ 84#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */ 85#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */ 86#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */ 87 88/* CPU Registers */ 89#define GICC_CTLR 0x0000 /* v1 ICCICR */ 90#define GICC_PMR 0x0004 /* v1 ICCPMR */ 91#define GICC_BPR 0x0008 /* v1 ICCBPR */ 92#define GICC_IAR 0x000C /* v1 ICCIAR */ 93#define GICC_EOIR 0x0010 /* v1 ICCEOIR */ 94#define GICC_RPR 0x0014 /* v1 ICCRPR */ 95#define GICC_HPPIR 0x0018 /* v1 ICCHPIR */ 96#define GICC_ABPR 0x001C /* v1 ICCABPR */ 97#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ 98 99#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */ 100#define GIC_LAST_SGI 15 101#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ 102#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ 103#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ 104 105/* First bit is a polarity bit (0 - low, 1 - high) */ 106#define GICD_ICFGR_POL_LOW (0 << 0) 107#define GICD_ICFGR_POL_HIGH (1 << 0) 108#define GICD_ICFGR_POL_MASK 0x1 109/* Second bit is a trigger bit (0 - level, 1 - edge) */ 110#define GICD_ICFGR_TRIG_LVL (0 << 1) 111#define GICD_ICFGR_TRIG_EDGE (1 << 1) 112#define GICD_ICFGR_TRIG_MASK 0x2 113 114#ifndef GIC_DEFAULT_ICFGR_INIT 115#define GIC_DEFAULT_ICFGR_INIT 0x00000000 116#endif 117 118#ifdef ARM_INTRNG 119struct gic_irqsrc { 120 struct intr_irqsrc gi_isrc; 121 uint32_t gi_irq; 122 enum intr_polarity gi_pol; 123 enum intr_trigger gi_trig; 124}; 125 126static u_int gic_irq_cpu; 127static int arm_gic_intr(void *); 128static int arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc); 129 130#ifdef SMP 131u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1]; 132u_int sgi_first_unused = GIC_FIRST_SGI; 133#endif 134#endif 135 136struct arm_gic_softc { 137 device_t gic_dev; 138#ifdef ARM_INTRNG 139 void * gic_intrhand; 140 struct gic_irqsrc * gic_irqs; 141#endif 142 struct resource * gic_res[3]; 143 bus_space_tag_t gic_c_bst; 144 bus_space_tag_t gic_d_bst; 145 bus_space_handle_t gic_c_bsh; 146 bus_space_handle_t gic_d_bsh; 147 uint8_t ver; 148 struct mtx mutex; 149 uint32_t nirqs; 150#ifdef GIC_DEBUG_SPURIOUS 151 uint32_t last_irq[MAXCPU]; 152#endif 153}; 154 155#ifdef ARM_INTRNG 156#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 157#endif 158 159static struct resource_spec arm_gic_spec[] = { 160 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ 161 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ 162#ifdef ARM_INTRNG 163 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */ 164#endif 165 { -1, 0 } 166}; 167 168static struct arm_gic_softc *gic_sc = NULL; 169 170#define gic_c_read_4(_sc, _reg) \ 171 bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) 172#define gic_c_write_4(_sc, _reg, _val) \ 173 bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val)) 174#define gic_d_read_4(_sc, _reg) \ 175 bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg)) 176#define gic_d_write_1(_sc, _reg, _val) \ 177 bus_space_write_1((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val)) 178#define gic_d_write_4(_sc, _reg, _val) \ 179 bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val)) 180 181#ifndef ARM_INTRNG 182static int gic_config_irq(int irq, enum intr_trigger trig, 183 enum intr_polarity pol); 184static void gic_post_filter(void *); 185#endif 186 187static struct ofw_compat_data compat_data[] = { 188 {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */ 189 {"arm,gic-400", true}, 190 {"arm,cortex-a15-gic", true}, 191 {"arm,cortex-a9-gic", true}, 192 {"arm,cortex-a7-gic", true}, 193 {"arm,arm11mp-gic", true}, 194 {"brcm,brahma-b15-gic", true}, 195 {NULL, false} 196}; 197 198static int 199arm_gic_probe(device_t dev) 200{ 201 202 if (!ofw_bus_status_okay(dev)) 203 return (ENXIO); 204 205 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 206 return (ENXIO); 207 device_set_desc(dev, "ARM Generic Interrupt Controller"); 208 return (BUS_PROBE_DEFAULT); 209} 210 211#ifdef ARM_INTRNG 212static inline void 213gic_irq_unmask(struct arm_gic_softc *sc, u_int irq) 214{ 215 216 gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F))); 217} 218 219static inline void 220gic_irq_mask(struct arm_gic_softc *sc, u_int irq) 221{ 222 223 gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F))); 224} 225#endif 226 227#ifdef SMP 228#ifdef ARM_INTRNG 229static void 230arm_gic_init_secondary(device_t dev) 231{ 232 struct arm_gic_softc *sc = device_get_softc(dev); 233 struct intr_irqsrc *isrc; 234 u_int irq; 235 236 for (irq = 0; irq < sc->nirqs; irq += 4) 237 gic_d_write_4(sc, GICD_IPRIORITYR(irq >> 2), 0); 238 239 /* Set all the interrupts to be in Group 0 (secure) */ 240 for (irq = 0; irq < sc->nirqs; irq += 32) { 241 gic_d_write_4(sc, GICD_IGROUPR(irq >> 5), 0); 242 } 243 244 /* Enable CPU interface */ 245 gic_c_write_4(sc, GICC_CTLR, 1); 246 247 /* Set priority mask register. */ 248 gic_c_write_4(sc, GICC_PMR, 0xff); 249 250 /* Enable interrupt distribution */ 251 gic_d_write_4(sc, GICD_CTLR, 0x01); 252 253 /* Unmask attached SGI interrupts. */ 254 for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) { 255 isrc = GIC_INTR_ISRC(sc, irq); 256 if (isrc != NULL && isrc->isrc_handlers != 0) { 257 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); 258 gic_irq_unmask(sc, irq); 259 } 260 } 261 262 /* Unmask attached PPI interrupts. */ 263 for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) { 264 isrc = GIC_INTR_ISRC(sc, irq); 265 if (isrc == NULL || isrc->isrc_handlers == 0) 266 continue; 267 if (isrc->isrc_flags & INTR_ISRCF_BOUND) { 268 if (CPU_ISSET(PCPU_GET(cpuid), &isrc->isrc_cpu)) 269 gic_irq_unmask(sc, irq); 270 } else { 271 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); 272 gic_irq_unmask(sc, irq); 273 } 274 } 275} 276#else 277static void 278arm_gic_init_secondary(device_t dev) 279{ 280 struct arm_gic_softc *sc = device_get_softc(dev); 281 int i; 282 283 for (i = 0; i < sc->nirqs; i += 4) 284 gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); 285 286 /* Set all the interrupts to be in Group 0 (secure) */ 287 for (i = 0; i < sc->nirqs; i += 32) { 288 gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); 289 } 290 291 /* Enable CPU interface */ 292 gic_c_write_4(sc, GICC_CTLR, 1); 293 294 /* Set priority mask register. */ 295 gic_c_write_4(sc, GICC_PMR, 0xff); 296 297 /* Enable interrupt distribution */ 298 gic_d_write_4(sc, GICD_CTLR, 0x01); 299 300 /* 301 * Activate the timer interrupts: virtual, secure, and non-secure. 302 */ 303 gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F))); 304 gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F))); 305 gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F))); 306} 307#endif /* ARM_INTRNG */ 308#endif /* SMP */ 309 310#ifndef ARM_INTRNG 311int 312gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 313 int *trig, int *pol) 314{ 315 static u_int num_intr_cells; 316 static phandle_t self; 317 struct ofw_compat_data *ocd; 318 319 if (self == 0) { 320 for (ocd = compat_data; ocd->ocd_str != NULL; ocd++) { 321 if (fdt_is_compatible(iparent, ocd->ocd_str)) { 322 self = iparent; 323 break; 324 } 325 } 326 } 327 if (self != iparent) 328 return (ENXIO); 329 330 if (num_intr_cells == 0) { 331 if (OF_searchencprop(OF_node_from_xref(iparent), 332 "#interrupt-cells", &num_intr_cells, 333 sizeof(num_intr_cells)) == -1) { 334 num_intr_cells = 1; 335 } 336 } 337 338 if (num_intr_cells == 1) { 339 *interrupt = fdt32_to_cpu(intr[0]); 340 *trig = INTR_TRIGGER_CONFORM; 341 *pol = INTR_POLARITY_CONFORM; 342 } else { 343 if (fdt32_to_cpu(intr[0]) == 0) 344 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI; 345 else 346 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI; 347 /* 348 * In intr[2], bits[3:0] are trigger type and level flags. 349 * 1 = low-to-high edge triggered 350 * 2 = high-to-low edge triggered 351 * 4 = active high level-sensitive 352 * 8 = active low level-sensitive 353 * The hardware only supports active-high-level or rising-edge 354 * for SPIs 355 */ 356 if (*interrupt >= GIC_FIRST_SPI && 357 fdt32_to_cpu(intr[2]) & 0x0a) { 358 printf("unsupported trigger/polarity configuration " 359 "0x%02x\n", fdt32_to_cpu(intr[2]) & 0x0f); 360 } 361 *pol = INTR_POLARITY_CONFORM; 362 if (fdt32_to_cpu(intr[2]) & 0x03) 363 *trig = INTR_TRIGGER_EDGE; 364 else 365 *trig = INTR_TRIGGER_LEVEL; 366 } 367 return (0); 368} 369#endif 370 371#ifdef ARM_INTRNG 372static inline intptr_t 373gic_xref(device_t dev) 374{ 375#ifdef FDT 376 return (OF_xref_from_node(ofw_bus_get_node(dev))); 377#else 378 return (0); 379#endif 380} 381 382static int 383arm_gic_register_isrcs(struct arm_gic_softc *sc, uint32_t num) 384{ 385 int error; 386 uint32_t irq; 387 struct gic_irqsrc *irqs; 388 struct intr_irqsrc *isrc; 389 const char *name; 390 391 irqs = malloc(num * sizeof(struct gic_irqsrc), M_DEVBUF, 392 M_WAITOK | M_ZERO); 393 394 name = device_get_nameunit(sc->gic_dev); 395 for (irq = 0; irq < num; irq++) { 396 irqs[irq].gi_irq = irq; 397 irqs[irq].gi_pol = INTR_POLARITY_CONFORM; 398 irqs[irq].gi_trig = INTR_TRIGGER_CONFORM; 399 400 isrc = &irqs[irq].gi_isrc; 401 if (irq <= GIC_LAST_SGI) { 402 error = intr_isrc_register(isrc, sc->gic_dev, 403 INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI); 404 } else if (irq <= GIC_LAST_PPI) { 405 error = intr_isrc_register(isrc, sc->gic_dev, 406 INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI); 407 } else { 408 error = intr_isrc_register(isrc, sc->gic_dev, 0, 409 "%s,s%u", name, irq - GIC_FIRST_SPI); 410 } 411 if (error != 0) { 412 /* XXX call intr_isrc_deregister() */ 413 free(irqs, M_DEVBUF); 414 return (error); 415 } 416 } 417 sc->gic_irqs = irqs; 418 sc->nirqs = num; 419 return (0); 420} 421#endif 422 423static int 424arm_gic_attach(device_t dev) 425{ 426 struct arm_gic_softc *sc; 427 int i; 428 uint32_t icciidr, mask, nirqs; 429#ifdef ARM_INTRNG 430 phandle_t pxref; 431 intptr_t xref = gic_xref(dev); 432#endif 433 434 if (gic_sc) 435 return (ENXIO); 436 437 sc = device_get_softc(dev); 438 439 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) { 440 device_printf(dev, "could not allocate resources\n"); 441 return (ENXIO); 442 } 443 444 sc->gic_dev = dev; 445 gic_sc = sc; 446 447 /* Initialize mutex */ 448 mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN); 449 450 /* Distributor Interface */ 451 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]); 452 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]); 453 454 /* CPU Interface */ 455 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]); 456 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]); 457 458 /* Disable interrupt forwarding to the CPU interface */ 459 gic_d_write_4(sc, GICD_CTLR, 0x00); 460 461 /* Get the number of interrupts */ 462 nirqs = gic_d_read_4(sc, GICD_TYPER); 463 nirqs = 32 * ((nirqs & 0x1f) + 1); 464 465#ifdef ARM_INTRNG 466 if (arm_gic_register_isrcs(sc, nirqs)) { 467 device_printf(dev, "could not register irqs\n"); 468 goto cleanup; 469 } 470#else 471 sc->nirqs = nirqs; 472 473 /* Set up function pointers */ 474 arm_post_filter = gic_post_filter; 475 arm_config_irq = gic_config_irq; 476#endif 477 478 icciidr = gic_c_read_4(sc, GICC_IIDR); 479 device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n", 480 icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf, 481 (icciidr & 0xfff), sc->nirqs); 482 483 /* Set all global interrupts to be level triggered, active low. */ 484 for (i = 32; i < sc->nirqs; i += 16) { 485 gic_d_write_4(sc, GICD_ICFGR(i >> 4), GIC_DEFAULT_ICFGR_INIT); 486 } 487 488 /* Disable all interrupts. */ 489 for (i = 32; i < sc->nirqs; i += 32) { 490 gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF); 491 } 492 493 /* Read the current cpuid mask by reading ITARGETSR{0..7} */ 494 for (i = 0; i < 8; i++) { 495 mask = gic_d_read_4(sc, GICD_ITARGETSR(i)); 496 if (mask != 0) 497 break; 498 } 499 /* No mask found, assume we are on CPU interface 0 */ 500 if (mask == 0) 501 mask = 1; 502 503 /* Collect the mask in the lower byte */ 504 mask |= mask >> 16; 505 mask |= mask >> 8; 506 /* Distribute this back to the upper bytes */ 507 mask |= mask << 8; 508 mask |= mask << 16; 509 510 for (i = 0; i < sc->nirqs; i += 4) { 511 gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); 512 if (i > 32) { 513 gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), mask); 514 } 515 } 516 517 /* Set all the interrupts to be in Group 0 (secure) */ 518 for (i = 0; i < sc->nirqs; i += 32) { 519 gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); 520 } 521 522 /* Enable CPU interface */ 523 gic_c_write_4(sc, GICC_CTLR, 1); 524 525 /* Set priority mask register. */ 526 gic_c_write_4(sc, GICC_PMR, 0xff); 527 528 /* Enable interrupt distribution */ 529 gic_d_write_4(sc, GICD_CTLR, 0x01); 530#ifndef ARM_INTRNG 531 return (0); 532#else 533 /* 534 * Now, when everything is initialized, it's right time to 535 * register interrupt controller to interrupt framefork. 536 */ 537 if (intr_pic_register(dev, xref) != 0) { 538 device_printf(dev, "could not register PIC\n"); 539 goto cleanup; 540 } 541 542 /* 543 * Controller is root if: 544 * - doesn't have interrupt parent 545 * - his interrupt parent is this controller 546 */ 547 pxref = ofw_bus_find_iparent(ofw_bus_get_node(dev)); 548 if (pxref == 0 || xref == pxref) { 549 if (intr_pic_claim_root(dev, xref, arm_gic_intr, sc, 550 GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) { 551 device_printf(dev, "could not set PIC as a root\n"); 552 intr_pic_deregister(dev, xref); 553 goto cleanup; 554 } 555 } else { 556 if (sc->gic_res[2] == NULL) { 557 device_printf(dev, 558 "not root PIC must have defined interrupt\n"); 559 intr_pic_deregister(dev, xref); 560 goto cleanup; 561 } 562 if (bus_setup_intr(dev, sc->gic_res[2], INTR_TYPE_CLK, 563 arm_gic_intr, NULL, sc, &sc->gic_intrhand)) { 564 device_printf(dev, "could not setup irq handler\n"); 565 intr_pic_deregister(dev, xref); 566 goto cleanup; 567 } 568 } 569 570 OF_device_register_xref(xref, dev); 571 return (0); 572 573cleanup: 574 /* 575 * XXX - not implemented arm_gic_detach() should be called ! 576 */ 577 if (sc->gic_irqs != NULL) 578 free(sc->gic_irqs, M_DEVBUF); 579 bus_release_resources(dev, arm_gic_spec, sc->gic_res); 580 return(ENXIO); 581#endif 582} 583 584#ifdef ARM_INTRNG 585static int 586arm_gic_intr(void *arg) 587{ 588 struct arm_gic_softc *sc = arg; 589 struct gic_irqsrc *gi; 590 uint32_t irq_active_reg, irq; 591 struct trapframe *tf; 592 593 irq_active_reg = gic_c_read_4(sc, GICC_IAR); 594 irq = irq_active_reg & 0x3FF; 595 596 /* 597 * 1. We do EOI here because recent read value from active interrupt 598 * register must be used for it. Another approach is to save this 599 * value into associated interrupt source. 600 * 2. EOI must be done on same CPU where interrupt has fired. Thus 601 * we must ensure that interrupted thread does not migrate to 602 * another CPU. 603 * 3. EOI cannot be delayed by any preemption which could happen on 604 * critical_exit() used in MI intr code, when interrupt thread is 605 * scheduled. See next point. 606 * 4. IPI_RENDEZVOUS assumes that no preemption is permitted during 607 * an action and any use of critical_exit() could break this 608 * assumption. See comments within smp_rendezvous_action(). 609 * 5. We always return FILTER_HANDLED as this is an interrupt 610 * controller dispatch function. Otherwise, in cascaded interrupt 611 * case, the whole interrupt subtree would be masked. 612 */ 613 614 if (irq >= sc->nirqs) { 615#ifdef GIC_DEBUG_SPURIOUS 616 device_printf(sc->gic_dev, 617 "Spurious interrupt detected: last irq: %d on CPU%d\n", 618 sc->last_irq[PCPU_GET(cpuid)], PCPU_GET(cpuid)); 619#endif 620 return (FILTER_HANDLED); 621 } 622 623 tf = curthread->td_intr_frame; 624dispatch_irq: 625 gi = sc->gic_irqs + irq; 626 /* 627 * Note that GIC_FIRST_SGI is zero and is not used in 'if' statement 628 * as compiler complains that comparing u_int >= 0 is always true. 629 */ 630 if (irq <= GIC_LAST_SGI) { 631#ifdef SMP 632 /* Call EOI for all IPI before dispatch. */ 633 gic_c_write_4(sc, GICC_EOIR, irq_active_reg); 634 intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf); 635 goto next_irq; 636#else 637 device_printf(sc->gic_dev, "SGI %u on UP system detected\n", 638 irq - GIC_FIRST_SGI); 639 gic_c_write_4(sc, GICC_EOIR, irq_active_reg); 640 goto next_irq; 641#endif 642 } 643 644#ifdef GIC_DEBUG_SPURIOUS 645 sc->last_irq[PCPU_GET(cpuid)] = irq; 646#endif 647 if (gi->gi_trig == INTR_TRIGGER_EDGE) 648 gic_c_write_4(sc, GICC_EOIR, irq_active_reg); 649 650 if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) { 651 gic_irq_mask(sc, irq); 652 if (gi->gi_trig != INTR_TRIGGER_EDGE) 653 gic_c_write_4(sc, GICC_EOIR, irq_active_reg); 654 device_printf(sc->gic_dev, "Stray irq %u disabled\n", irq); 655 } 656 657next_irq: 658 arm_irq_memory_barrier(irq); 659 irq_active_reg = gic_c_read_4(sc, GICC_IAR); 660 irq = irq_active_reg & 0x3FF; 661 if (irq < sc->nirqs) 662 goto dispatch_irq; 663 664 return (FILTER_HANDLED); 665} 666 667static void 668gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig, 669 enum intr_polarity pol) 670{ 671 uint32_t reg; 672 uint32_t mask; 673 674 if (irq < GIC_FIRST_SPI) 675 return; 676 677 mtx_lock_spin(&sc->mutex); 678 679 reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4)); 680 mask = (reg >> 2*(irq % 16)) & 0x3; 681 682 if (pol == INTR_POLARITY_LOW) { 683 mask &= ~GICD_ICFGR_POL_MASK; 684 mask |= GICD_ICFGR_POL_LOW; 685 } else if (pol == INTR_POLARITY_HIGH) { 686 mask &= ~GICD_ICFGR_POL_MASK; 687 mask |= GICD_ICFGR_POL_HIGH; 688 } 689 690 if (trig == INTR_TRIGGER_LEVEL) { 691 mask &= ~GICD_ICFGR_TRIG_MASK; 692 mask |= GICD_ICFGR_TRIG_LVL; 693 } else if (trig == INTR_TRIGGER_EDGE) { 694 mask &= ~GICD_ICFGR_TRIG_MASK; 695 mask |= GICD_ICFGR_TRIG_EDGE; 696 } 697 698 /* Set mask */ 699 reg = reg & ~(0x3 << 2*(irq % 16)); 700 reg = reg | (mask << 2*(irq % 16)); 701 gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg); 702 703 mtx_unlock_spin(&sc->mutex); 704} 705 706static int 707gic_bind(struct arm_gic_softc *sc, u_int irq, cpuset_t *cpus) 708{ 709 uint32_t cpu, end, mask; 710 711 end = min(mp_ncpus, 8); 712 for (cpu = end; cpu < MAXCPU; cpu++) 713 if (CPU_ISSET(cpu, cpus)) 714 return (EINVAL); 715 716 for (mask = 0, cpu = 0; cpu < end; cpu++) 717 if (CPU_ISSET(cpu, cpus)) 718 mask |= 1 << cpu; 719 720 gic_d_write_1(sc, GICD_ITARGETSR(0) + irq, mask); 721 return (0); 722} 723 724#ifdef FDT 725static int 726gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, 727 enum intr_polarity *polp, enum intr_trigger *trigp) 728{ 729 730 if (ncells == 1) { 731 *irqp = cells[0]; 732 *polp = INTR_POLARITY_CONFORM; 733 *trigp = INTR_TRIGGER_CONFORM; 734 return (0); 735 } 736 if (ncells == 3) { 737 u_int irq, tripol; 738 739 /* 740 * The 1st cell is the interrupt type: 741 * 0 = SPI 742 * 1 = PPI 743 * The 2nd cell contains the interrupt number: 744 * [0 - 987] for SPI 745 * [0 - 15] for PPI 746 * The 3rd cell is the flags, encoded as follows: 747 * bits[3:0] trigger type and level flags 748 * 1 = low-to-high edge triggered 749 * 2 = high-to-low edge triggered 750 * 4 = active high level-sensitive 751 * 8 = active low level-sensitive 752 * bits[15:8] PPI interrupt cpu mask 753 * Each bit corresponds to each of the 8 possible cpus 754 * attached to the GIC. A bit set to '1' indicated 755 * the interrupt is wired to that CPU. 756 */ 757 switch (cells[0]) { 758 case 0: 759 irq = GIC_FIRST_SPI + cells[1]; 760 /* SPI irq is checked later. */ 761 break; 762 case 1: 763 irq = GIC_FIRST_PPI + cells[1]; 764 if (irq > GIC_LAST_PPI) { 765 device_printf(dev, "unsupported PPI interrupt " 766 "number %u\n", cells[1]); 767 return (EINVAL); 768 } 769 break; 770 default: 771 device_printf(dev, "unsupported interrupt type " 772 "configuration %u\n", cells[0]); 773 return (EINVAL); 774 } 775 776 tripol = cells[2] & 0xff; 777 if (tripol & 0xf0 || (tripol & 0x0a && cells[0] == 0)) 778 device_printf(dev, "unsupported trigger/polarity " 779 "configuration 0x%02x\n", tripol); 780 781 *irqp = irq; 782 *polp = INTR_POLARITY_CONFORM; 783 *trigp = tripol & 0x03 ? INTR_TRIGGER_EDGE : INTR_TRIGGER_LEVEL; 784 return (0); 785 } 786 return (EINVAL); 787} 788#endif 789 790static int 791gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, 792 enum intr_polarity *polp, enum intr_trigger *trigp) 793{ 794 u_int irq; 795 enum intr_polarity pol; 796 enum intr_trigger trig; 797 struct arm_gic_softc *sc; 798 799 sc = device_get_softc(dev); 800 switch (data->type) { 801#ifdef FDT 802 case INTR_MAP_DATA_FDT: 803 if (gic_map_fdt(dev, data->fdt.ncells, data->fdt.cells, &irq, 804 &pol, &trig) != 0) 805 return (EINVAL); 806 break; 807#endif 808 default: 809 return (EINVAL); 810 } 811 812 if (irq >= sc->nirqs) 813 return (EINVAL); 814 if (pol != INTR_POLARITY_CONFORM && pol != INTR_POLARITY_LOW && 815 pol != INTR_POLARITY_HIGH) 816 return (EINVAL); 817 if (trig != INTR_TRIGGER_CONFORM && trig != INTR_TRIGGER_EDGE && 818 trig != INTR_TRIGGER_LEVEL) 819 return (EINVAL); 820 821 *irqp = irq; 822 if (polp != NULL) 823 *polp = pol; 824 if (trigp != NULL) 825 *trigp = trig; 826 return (0); 827} 828 829static int 830arm_gic_map_intr(device_t dev, struct intr_map_data *data, 831 struct intr_irqsrc **isrcp) 832{ 833 int error; 834 u_int irq; 835 struct arm_gic_softc *sc; 836 837 error = gic_map_intr(dev, data, &irq, NULL, NULL); 838 if (error == 0) { 839 sc = device_get_softc(dev); 840 *isrcp = GIC_INTR_ISRC(sc, irq); 841 } 842 return (error); 843} 844 845static int 846arm_gic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 847 struct resource *res, struct intr_map_data *data) 848{ 849 struct arm_gic_softc *sc = device_get_softc(dev); 850 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 851 u_int irq; 852 enum intr_trigger trig; 853 enum intr_polarity pol; 854 855 if (data == NULL) 856 return (ENOTSUP); 857 858 /* Get config for resource. */ 859 if (gic_map_intr(dev, data, &irq, &pol, &trig)) 860 return (EINVAL); 861 862 if (gi->gi_irq != irq) 863 return (EINVAL); 864 865 /* Compare config if this is not first setup. */ 866 if (isrc->isrc_handlers != 0) { 867 if ((pol != INTR_POLARITY_CONFORM && pol != gi->gi_pol) || 868 (trig != INTR_TRIGGER_CONFORM && trig != gi->gi_trig)) 869 return (EINVAL); 870 else 871 return (0); 872 } 873 874 if (pol == INTR_POLARITY_CONFORM) 875 pol = INTR_POLARITY_LOW; /* just pick some */ 876 if (trig == INTR_TRIGGER_CONFORM) 877 trig = INTR_TRIGGER_EDGE; /* just pick some */ 878 879 gi->gi_pol = pol; 880 gi->gi_trig = trig; 881 882 /* 883 * XXX - In case that per CPU interrupt is going to be enabled in time 884 * when SMP is already started, we need some IPI call which 885 * enables it on others CPUs. Further, it's more complicated as 886 * pic_enable_source() and pic_disable_source() should act on 887 * per CPU basis only. Thus, it should be solved here somehow. 888 */ 889 if (isrc->isrc_flags & INTR_ISRCF_PPI) 890 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); 891 892 gic_config(sc, gi->gi_irq, trig, pol); 893 arm_gic_bind_intr(dev, isrc); 894 return (0); 895} 896 897static int 898arm_gic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 899 struct resource *res, struct intr_map_data *data) 900{ 901 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 902 903 if (isrc->isrc_handlers == 0) { 904 gi->gi_pol = INTR_POLARITY_CONFORM; 905 gi->gi_trig = INTR_TRIGGER_CONFORM; 906 } 907 return (0); 908} 909 910static void 911arm_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 912{ 913 struct arm_gic_softc *sc = device_get_softc(dev); 914 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 915 916 arm_irq_memory_barrier(gi->gi_irq); 917 gic_irq_unmask(sc, gi->gi_irq); 918} 919 920static void 921arm_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 922{ 923 struct arm_gic_softc *sc = device_get_softc(dev); 924 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 925 926 gic_irq_mask(sc, gi->gi_irq); 927} 928 929static void 930arm_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 931{ 932 struct arm_gic_softc *sc = device_get_softc(dev); 933 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 934 935 arm_gic_disable_intr(dev, isrc); 936 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq); 937} 938 939static void 940arm_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 941{ 942 943 arm_irq_memory_barrier(0); 944 arm_gic_enable_intr(dev, isrc); 945} 946 947static void 948arm_gic_post_filter(device_t dev, struct intr_irqsrc *isrc) 949{ 950 struct arm_gic_softc *sc = device_get_softc(dev); 951 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 952 953 /* EOI for edge-triggered done earlier. */ 954 if (gi->gi_trig == INTR_TRIGGER_EDGE) 955 return; 956 957 arm_irq_memory_barrier(0); 958 gic_c_write_4(sc, GICC_EOIR, gi->gi_irq); 959} 960 961static int 962arm_gic_bind_intr(device_t dev, struct intr_irqsrc *isrc) 963{ 964 struct arm_gic_softc *sc = device_get_softc(dev); 965 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 966 967 if (gi->gi_irq < GIC_FIRST_SPI) 968 return (EINVAL); 969 970 if (CPU_EMPTY(&isrc->isrc_cpu)) { 971 gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus); 972 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu); 973 } 974 return (gic_bind(sc, gi->gi_irq, &isrc->isrc_cpu)); 975} 976 977#ifdef SMP 978static void 979arm_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, 980 u_int ipi) 981{ 982 struct arm_gic_softc *sc = device_get_softc(dev); 983 struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc; 984 uint32_t val = 0, i; 985 986 for (i = 0; i < MAXCPU; i++) 987 if (CPU_ISSET(i, &cpus)) 988 val |= 1 << (16 + i); 989 990 gic_d_write_4(sc, GICD_SGIR(0), val | gi->gi_irq); 991} 992 993static int 994arm_gic_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp) 995{ 996 struct arm_gic_softc *sc = device_get_softc(dev); 997 998 if (sgi_first_unused > GIC_LAST_SGI) 999 return (ENOSPC); 1000 1001 *isrcp = GIC_INTR_ISRC(sc, sgi_first_unused); 1002 sgi_to_ipi[sgi_first_unused++] = ipi; 1003 return (0); 1004} 1005#endif 1006#else 1007static int 1008arm_gic_next_irq(struct arm_gic_softc *sc, int last_irq) 1009{ 1010 uint32_t active_irq; 1011 1012 active_irq = gic_c_read_4(sc, GICC_IAR); 1013 1014 /* 1015 * Immediatly EOIR the SGIs, because doing so requires the other 1016 * bits (ie CPU number), not just the IRQ number, and we do not 1017 * have this information later. 1018 */ 1019 if ((active_irq & 0x3ff) <= GIC_LAST_SGI) 1020 gic_c_write_4(sc, GICC_EOIR, active_irq); 1021 active_irq &= 0x3FF; 1022 1023 if (active_irq == 0x3FF) { 1024 if (last_irq == -1) 1025 device_printf(sc->gic_dev, 1026 "Spurious interrupt detected\n"); 1027 return -1; 1028 } 1029 1030 return active_irq; 1031} 1032 1033static int 1034arm_gic_config(device_t dev, int irq, enum intr_trigger trig, 1035 enum intr_polarity pol) 1036{ 1037 struct arm_gic_softc *sc = device_get_softc(dev); 1038 uint32_t reg; 1039 uint32_t mask; 1040 1041 /* Function is public-accessible, so validate input arguments */ 1042 if ((irq < 0) || (irq >= sc->nirqs)) 1043 goto invalid_args; 1044 if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) && 1045 (trig != INTR_TRIGGER_CONFORM)) 1046 goto invalid_args; 1047 if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) && 1048 (pol != INTR_POLARITY_CONFORM)) 1049 goto invalid_args; 1050 1051 mtx_lock_spin(&sc->mutex); 1052 1053 reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4)); 1054 mask = (reg >> 2*(irq % 16)) & 0x3; 1055 1056 if (pol == INTR_POLARITY_LOW) { 1057 mask &= ~GICD_ICFGR_POL_MASK; 1058 mask |= GICD_ICFGR_POL_LOW; 1059 } else if (pol == INTR_POLARITY_HIGH) { 1060 mask &= ~GICD_ICFGR_POL_MASK; 1061 mask |= GICD_ICFGR_POL_HIGH; 1062 } 1063 1064 if (trig == INTR_TRIGGER_LEVEL) { 1065 mask &= ~GICD_ICFGR_TRIG_MASK; 1066 mask |= GICD_ICFGR_TRIG_LVL; 1067 } else if (trig == INTR_TRIGGER_EDGE) { 1068 mask &= ~GICD_ICFGR_TRIG_MASK; 1069 mask |= GICD_ICFGR_TRIG_EDGE; 1070 } 1071 1072 /* Set mask */ 1073 reg = reg & ~(0x3 << 2*(irq % 16)); 1074 reg = reg | (mask << 2*(irq % 16)); 1075 gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg); 1076 1077 mtx_unlock_spin(&sc->mutex); 1078 1079 return (0); 1080 1081invalid_args: 1082 device_printf(dev, "gic_config_irg, invalid parameters\n"); 1083 return (EINVAL); 1084} 1085 1086 1087static void 1088arm_gic_mask(device_t dev, int irq) 1089{ 1090 struct arm_gic_softc *sc = device_get_softc(dev); 1091 1092 gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F))); 1093 gic_c_write_4(sc, GICC_EOIR, irq); /* XXX - not allowed */ 1094} 1095 1096static void 1097arm_gic_unmask(device_t dev, int irq) 1098{ 1099 struct arm_gic_softc *sc = device_get_softc(dev); 1100 1101 if (irq > GIC_LAST_SGI) 1102 arm_irq_memory_barrier(irq); 1103 1104 gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F))); 1105} 1106 1107#ifdef SMP 1108static void 1109arm_gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi) 1110{ 1111 struct arm_gic_softc *sc = device_get_softc(dev); 1112 uint32_t val = 0, i; 1113 1114 for (i = 0; i < MAXCPU; i++) 1115 if (CPU_ISSET(i, &cpus)) 1116 val |= 1 << (16 + i); 1117 1118 gic_d_write_4(sc, GICD_SGIR(0), val | ipi); 1119} 1120 1121static int 1122arm_gic_ipi_read(device_t dev, int i) 1123{ 1124 1125 if (i != -1) { 1126 /* 1127 * The intr code will automagically give the frame pointer 1128 * if the interrupt argument is 0. 1129 */ 1130 if ((unsigned int)i > 16) 1131 return (0); 1132 return (i); 1133 } 1134 1135 return (0x3ff); 1136} 1137 1138static void 1139arm_gic_ipi_clear(device_t dev, int ipi) 1140{ 1141 /* no-op */ 1142} 1143#endif 1144 1145static void 1146gic_post_filter(void *arg) 1147{ 1148 struct arm_gic_softc *sc = gic_sc; 1149 uintptr_t irq = (uintptr_t) arg; 1150 1151 if (irq > GIC_LAST_SGI) 1152 arm_irq_memory_barrier(irq); 1153 gic_c_write_4(sc, GICC_EOIR, irq); 1154} 1155 1156static int 1157gic_config_irq(int irq, enum intr_trigger trig, enum intr_polarity pol) 1158{ 1159 1160 return (arm_gic_config(gic_sc->gic_dev, irq, trig, pol)); 1161} 1162 1163void 1164arm_mask_irq(uintptr_t nb) 1165{ 1166 1167 arm_gic_mask(gic_sc->gic_dev, nb); 1168} 1169 1170void 1171arm_unmask_irq(uintptr_t nb) 1172{ 1173 1174 arm_gic_unmask(gic_sc->gic_dev, nb); 1175} 1176 1177int 1178arm_get_next_irq(int last_irq) 1179{ 1180 1181 return (arm_gic_next_irq(gic_sc, last_irq)); 1182} 1183 1184#ifdef SMP 1185void 1186intr_pic_init_secondary(void) 1187{ 1188 1189 arm_gic_init_secondary(gic_sc->gic_dev); 1190} 1191 1192void 1193pic_ipi_send(cpuset_t cpus, u_int ipi) 1194{ 1195 1196 arm_gic_ipi_send(gic_sc->gic_dev, cpus, ipi); 1197} 1198 1199int 1200pic_ipi_read(int i) 1201{ 1202 1203 return (arm_gic_ipi_read(gic_sc->gic_dev, i)); 1204} 1205 1206void 1207pic_ipi_clear(int ipi) 1208{ 1209 1210 arm_gic_ipi_clear(gic_sc->gic_dev, ipi); 1211} 1212#endif 1213#endif /* ARM_INTRNG */ 1214 1215static device_method_t arm_gic_methods[] = { 1216 /* Device interface */ 1217 DEVMETHOD(device_probe, arm_gic_probe), 1218 DEVMETHOD(device_attach, arm_gic_attach), 1219#ifdef ARM_INTRNG 1220 /* Interrupt controller interface */ 1221 DEVMETHOD(pic_disable_intr, arm_gic_disable_intr), 1222 DEVMETHOD(pic_enable_intr, arm_gic_enable_intr), 1223 DEVMETHOD(pic_map_intr, arm_gic_map_intr), 1224 DEVMETHOD(pic_setup_intr, arm_gic_setup_intr), 1225 DEVMETHOD(pic_teardown_intr, arm_gic_teardown_intr), 1226 DEVMETHOD(pic_post_filter, arm_gic_post_filter), 1227 DEVMETHOD(pic_post_ithread, arm_gic_post_ithread), 1228 DEVMETHOD(pic_pre_ithread, arm_gic_pre_ithread), 1229#ifdef SMP 1230 DEVMETHOD(pic_bind_intr, arm_gic_bind_intr), 1231 DEVMETHOD(pic_init_secondary, arm_gic_init_secondary), 1232 DEVMETHOD(pic_ipi_send, arm_gic_ipi_send), 1233 DEVMETHOD(pic_ipi_setup, arm_gic_ipi_setup), 1234#endif 1235#endif 1236 { 0, 0 } 1237}; 1238 1239static driver_t arm_gic_driver = { 1240 "gic", 1241 arm_gic_methods, 1242 sizeof(struct arm_gic_softc), 1243}; 1244 1245static devclass_t arm_gic_devclass; 1246 1247EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0, 1248 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1249EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0, 1250 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 1251