#
285830 |
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23-Jul-2015 |
gjb |
- Copy stable/10@285827 to releng/10.2 in preparation for 10.2-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.2. - Update default pkg(8) configuration to use the quarterly branch.[1]
Discussed with: re, portmgr [1] Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
284900 |
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28-Jun-2015 |
neel |
MFC r282209: Emulate the 'bit test' instruction.
MFC r282259: Re-implement RTC current time calculation to eliminate the possibility of losing time.
MFC r282281: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.
MFC r282284: When an instruction cannot be decoded just return to userspace so bhyve(8) can dump the instruction bytes.
MFC r282287: Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.
MFC r282296: Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are enabled.
MFC r282301: Relax limits when transitioning a vector from the IRR to the ISR and also when extinguishing it from the ISR in response to an EOI.
MFC r282335: Advertise an additional memory BAR in the "dummy" device emulation.
MFC r282336: Emulate machine check related MSRs to allow guest OSes like Windows to boot.
MFC r282351: Don't advertise the Intel SMX capability to the guest.
MFC r282407: Emulate the 'CMP r/m8, imm8' instruction.
MFC r282519: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE.
MFC r282520: Emulate guest writes to EFER_MSR properly.
MFC r282558: Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup().
MFC r282571: Check 'td_owepreempt' and yield the vcpu thread if it is set.
MFC r282595: Allow byte reads of AHCI registers.
MFC r282784: Handling indirect descriptors is a capability of the host and not one that needs to be negotiated. Use the host capabilities field and not the negotiated field when verifying that indirect descriptors are supported.
MFC r282788: Allow configuration of the sector size advertised to the guest.
MFC r282865: Set the subvendor field in config space to the vendor ID. This is required by the Windows virtio drivers to correctly match a device.
MFC r282922: Bump the size of the blockif scatter-gather list to 67.
MFC r283075: Fix off-by-one in array index bounds check. bhyveload would allow you to create 33 entries on an array that only has 32 slots
MFC r283168: Temporarily revert r282922 which bumped the max descriptors.
MFC r283255: Emulate the "CMP r/m, reg" instruction (opcode 39H).
MFC r283256: Add an option "--get-vmcs-exit-inst-length" to display the instruction length of the instruction that caused the VM-exit.
MFC r283264: Change the header type of the emulated host-bridge from type 1 to type 0.
MFC r283293: Don't rely on the 'VM-exit instruction length' field in the VMCS to always have an accurate length on an EPT violation.
MFC r283299: Remove bogus verification of instruction length after instruction decode.
MFC r283308: Exceptions don't deliver an error code in real mode.
MFC r283657: Fix non-deterministic delays when accessing a vcpu that was in "running" or "sleeping" state.
MFC r283973: Use tunable 'hw.vmm.svm.features' to disable specific SVM features even though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids' to limit the number of ASIDs used by the hypervisor.
MFC r284046: Fix regression in 'verify_gla()' with the RIP-relative addressing mode.
MFC r284174: Support guest writes to the TSC by enabling the "use TSC offsetting" execution control.
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#
276403 |
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30-Dec-2014 |
neel |
MFC r273375 Add support AMD processors with the SVM/AMD-V hardware extensions.
MFC r273749 Remove bhyve SVM feature printf's now that they are available in the general CPU feature detection code.
MFC r273766 Add missing 'break' pointed out by Coverity CID 1249760.
MFC r276098 Allow ktr(4) tracing of all guest exceptions via the tunable "hw.vmm.trace_guest_exceptions"
MFC r276392 Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT' on an AMD/SVM host.
MFC r276402 Remove "svn:mergeinfo" property that was dragged along when these files were svn copied in r273375.
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#
273375 |
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21-Oct-2014 |
neel |
Merge projects/bhyve_svm into HEAD.
After this change bhyve supports AMD processors with the SVM/AMD-V hardware extensions.
More details available here: https://lists.freebsd.org/pipermail/freebsd-virtualization/2014-October/002905.html
Submitted by: Anish Gupta (akgupt3@gmail.com) Tested by: Benjamin Perrault (ben.perrault@gmail.com) Tested by: Willem Jan Withagen (wjw@digiware.nl)
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#
272916 |
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10-Oct-2014 |
neel |
Fix bhyvectl so it works correctly on AMD/SVM hosts. Also, add command line options to display some key VMCB fields.
The set of valid options that can be passed to bhyvectl now depends on the processor type. AMD-specific options are identified by a "--vmcb" or "--avic" in the option name. Intel-specific options are identified by a "--vmcs" in the option name.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
271939 |
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21-Sep-2014 |
neel |
Allow more VMCB fields to be cached: - CR2 - CR0, CR3, CR4 and EFER - GDT/IDT base/limit fields - CS/DS/ES/SS selector/base/limit/attrib fields
The caching can be further restricted via the tunable 'hw.vmm.svm.vmcb_clean'.
Restructure the code such that the fields above are only modified in a single place. This makes it easy to invalidate the VMCB cache when any of these fields is modified.
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#
271346 |
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10-Sep-2014 |
neel |
Move the VMCB initialization into svm.c in preparation for changes to the interrupt injection logic.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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#
271345 |
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10-Sep-2014 |
neel |
Move the event injection function into svm.c and add KTR logging for every event injection.
This in in preparation for changes to SVM guest interrupt injection.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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#
271203 |
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06-Sep-2014 |
neel |
Do proper ASID management for guest vcpus.
Prior to this change an ASID was hard allocated to a guest and shared by all its vcpus. The meant that the number of VMs that could be created was limited to the number of ASIDs supported by the CPU. It was also inefficient because it forced a TLB flush on every VMRUN.
With this change the number of guests that can be created is independent of the number of available ASIDs. Also, the TLB is flushed only when a new ASID is allocated.
Discussed with: grehan Reviewed by: Anish Gupta (akgupt3@gmail.com)
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#
271152 |
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05-Sep-2014 |
neel |
Merge svm_set_vmcb() and svm_init_vmcb() into a single function that is called just once when a vcpu is initialized.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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#
270511 |
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25-Aug-2014 |
neel |
An exception is allowed to be injected even if the vcpu is in an interrupt shadow, so move the check for pending exception before bailing out due to an interrupt shadow.
Change return type of 'vmcb_eventinject()' to a void and convert all error returns into KASSERTs.
Fix VMCB_EXITINTINFO_EC(x) and VMCB_EXITINTINFO_TYPE(x) to do the shift before masking the result.
Reviewed by: Anish Gupta (akgupt3@gmail.com)
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#
267217 |
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07-Jun-2014 |
grehan |
Set the guest PAT MSR in the VMCB to power-on defaults.
Linux guests accept the values in this register, while *BSD guests reprogram it. Default values of zero correspond to PAT_UNCACHEABLE, resulting in glacial performance.
Thanks to Willem Jan Withagen for first reporting this and helping out with the investigation.
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#
267096 |
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05-Jun-2014 |
grehan |
Allow the guest's CR2 value to be read/written. This is required for page-fault injection.
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#
267003 |
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03-Jun-2014 |
grehan |
Bring (almost) up-to-date with HEAD.
- use the new virtual APIC page - update to current bhyve APIs
Tested by Anish with multiple FreeBSD SMP VMs on a Phenom, and verified by myself with light FreeBSD VM testing on a Sempron 3850 APU.
The issues reported with Linux guests are very likely to still be here, but this sync eliminates the skew between the project branch and CURRENT, and should help to determine the causes.
Some follow-on commits will fix minor cosmetic issues.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
259579 |
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18-Dec-2013 |
grehan |
Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
249967 |
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27-Apr-2013 |
neel |
- SVM nested paging support - Define data structures to contain the SVM vcpu context - Define data structures to contain guest and host software context - Change license in vmcb.h and vmcb.c to remove references to NetApp that inadvertently sneaked in when the license text was copied from amdv.c.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
249493 |
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15-Apr-2013 |
neel |
Add a Cliff Notes version of the purpose and contents of the VMCB.
Requested by: julian
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#
249353 |
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11-Apr-2013 |
neel |
Provide functions to manipulate the guest state in the VMCB.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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