vmcb.c revision 267096
1/*- 2 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: projects/bhyve_svm/sys/amd64/vmm/amd/vmcb.c 267096 2014-06-05 06:29:18Z grehan $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/cpuset.h> 33 34#include <machine/segments.h> 35#include <machine/specialreg.h> 36#include <machine/vmm.h> 37 38#include "vmcb.h" 39#include "svm.h" 40 41/* 42 * The VMCB aka Virtual Machine Control Block is a 4KB aligned page 43 * in memory that describes the virtual machine. 44 * 45 * The VMCB contains: 46 * - instructions or events in the guest to intercept 47 * - control bits that modify execution environment of the guest 48 * - guest processor state (e.g. general purpose registers) 49 */ 50 51/* 52 * Initialize SVM h/w context i.e. the VMCB control and saved state areas. 53 */ 54int 55svm_init_vmcb(struct vmcb *vmcb, uint64_t iopm_base_pa, 56 uint64_t msrpm_base_pa, uint64_t np_pml4) 57{ 58 struct vmcb_ctrl *ctrl; 59 struct vmcb_state *state; 60 61 ctrl = &vmcb->ctrl; 62 state = &vmcb->state; 63 64 ctrl->iopm_base_pa = iopm_base_pa; 65 ctrl->msrpm_base_pa = msrpm_base_pa; 66 67 /* Enable nested paging */ 68 ctrl->np_enable = 1; 69 ctrl->n_cr3 = np_pml4; 70 71 /* EFER_SVM must always be set when the guest is executing */ 72 state->efer = EFER_SVM; 73 74 return (0); 75} 76 77/* 78 * Set non-persistent fields of VMCB that are cleared by VMEXIT and must 79 * be set before restarting the guest (e.g. ASID, intercepts etc). 80 * 81 * APM2, Section 15.6, VMEXIT 82 */ 83int 84svm_set_vmcb(struct vmcb *vmcb, uint8_t asid) 85{ 86 struct vmcb_ctrl *ctrl; 87 struct vmcb_state *state; 88 uint16_t cr_shadow; 89 90 ctrl = &vmcb->ctrl; 91 state = &vmcb->state; 92 93 /* 94 * Intercept accesses to the control registers that are not shadowed 95 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8. 96 */ 97 cr_shadow = BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(8); 98 ctrl->cr_write = ctrl->cr_read = ~cr_shadow; 99 100 /* Intercept Machine Check exceptions. */ 101 ctrl->exception = BIT(IDT_MC); 102 103 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */ 104 ctrl->ctrl1 = VMCB_INTCPT_IO | 105 VMCB_INTCPT_MSR | 106 VMCB_INTCPT_HLT | 107 VMCB_INTCPT_CPUID | 108 VMCB_INTCPT_INTR | 109 VMCB_INTCPT_VINTR | 110 VMCB_INTCPT_INIT | 111 VMCB_INTCPT_NMI | 112 VMCB_INTCPT_SMI | 113 VMCB_INTCPT_FERR_FREEZE | 114 VMCB_INTCPT_SHUTDOWN; 115 116 /* VMRUN intercept is required, see APM2 */ 117 ctrl->ctrl2 = VMCB_INTCPT_VMRUN; 118 119 /* ASID is cleared after every #VMEXIT. */ 120 ctrl->asid = asid; 121 122 /* 123 * Section 15.21.1, Interrupt Masking in EFLAGS 124 * Section 15.21.2, Virtualizing APIC.TPR 125 * 126 * This must be set for %rflag and %cr8 isolation of guest and host. 127 */ 128 ctrl->v_intr_masking = 1; 129 130 /* Enable Last Branch Record aka LBR for debugging */ 131 ctrl->lbr_virt_en = 1; 132 state->dbgctl = BIT(0); 133 134 return (0); 135} 136 137/* 138 * Read from segment selector, control and general purpose register of VMCB. 139 */ 140int 141vmcb_read(struct vmcb *vmcb, int ident, uint64_t *retval) 142{ 143 struct vmcb_state *state; 144 struct vmcb_segment *seg; 145 int err; 146 147 state = &vmcb->state; 148 err = 0; 149 150 switch (ident) { 151 case VM_REG_GUEST_CR0: 152 *retval = state->cr0; 153 break; 154 155 case VM_REG_GUEST_CR2: 156 *retval = state->cr2; 157 break; 158 159 case VM_REG_GUEST_CR3: 160 *retval = state->cr3; 161 break; 162 163 case VM_REG_GUEST_CR4: 164 *retval = state->cr4; 165 break; 166 167 case VM_REG_GUEST_DR7: 168 *retval = state->dr7; 169 break; 170 171 case VM_REG_GUEST_EFER: 172 *retval = state->efer; 173 break; 174 175 case VM_REG_GUEST_RAX: 176 *retval = state->rax; 177 break; 178 179 case VM_REG_GUEST_RFLAGS: 180 *retval = state->rflags; 181 break; 182 183 case VM_REG_GUEST_RIP: 184 *retval = state->rip; 185 break; 186 187 case VM_REG_GUEST_RSP: 188 *retval = state->rsp; 189 break; 190 191 case VM_REG_GUEST_CS: 192 case VM_REG_GUEST_DS: 193 case VM_REG_GUEST_ES: 194 case VM_REG_GUEST_FS: 195 case VM_REG_GUEST_GS: 196 case VM_REG_GUEST_SS: 197 case VM_REG_GUEST_GDTR: 198 case VM_REG_GUEST_IDTR: 199 case VM_REG_GUEST_LDTR: 200 case VM_REG_GUEST_TR: 201 seg = vmcb_seg(vmcb, ident); 202 if (seg == NULL) { 203 ERR("Invalid seg type %d\n", ident); 204 err = EINVAL; 205 break; 206 } 207 208 *retval = seg->selector; 209 break; 210 211 default: 212 err = EINVAL; 213 break; 214 } 215 216 return (err); 217} 218 219/* 220 * Write to segment selector, control and general purpose register of VMCB. 221 */ 222int 223vmcb_write(struct vmcb *vmcb, int ident, uint64_t val) 224{ 225 struct vmcb_state *state; 226 struct vmcb_segment *seg; 227 int err; 228 229 state = &vmcb->state; 230 err = 0; 231 232 switch (ident) { 233 case VM_REG_GUEST_CR0: 234 state->cr0 = val; 235 break; 236 237 case VM_REG_GUEST_CR2: 238 state->cr2 = val; 239 break; 240 241 case VM_REG_GUEST_CR3: 242 state->cr3 = val; 243 break; 244 245 case VM_REG_GUEST_CR4: 246 state->cr4 = val; 247 break; 248 249 case VM_REG_GUEST_DR7: 250 state->dr7 = val; 251 break; 252 253 case VM_REG_GUEST_EFER: 254 /* EFER_SVM must always be set when the guest is executing */ 255 state->efer = val | EFER_SVM; 256 break; 257 258 case VM_REG_GUEST_RAX: 259 state->rax = val; 260 break; 261 262 case VM_REG_GUEST_RFLAGS: 263 state->rflags = val; 264 break; 265 266 case VM_REG_GUEST_RIP: 267 state->rip = val; 268 break; 269 270 case VM_REG_GUEST_RSP: 271 state->rsp = val; 272 break; 273 274 case VM_REG_GUEST_CS: 275 case VM_REG_GUEST_DS: 276 case VM_REG_GUEST_ES: 277 case VM_REG_GUEST_FS: 278 case VM_REG_GUEST_GS: 279 case VM_REG_GUEST_SS: 280 case VM_REG_GUEST_GDTR: 281 case VM_REG_GUEST_IDTR: 282 case VM_REG_GUEST_LDTR: 283 case VM_REG_GUEST_TR: 284 seg = vmcb_seg(vmcb, ident); 285 if (seg == NULL) { 286 ERR("Invalid segment type %d\n", ident); 287 err = EINVAL; 288 break; 289 } 290 291 seg->selector = val; 292 break; 293 294 default: 295 err = EINVAL; 296 } 297 298 return (err); 299} 300 301/* 302 * Return VMCB segment area. 303 */ 304struct vmcb_segment * 305vmcb_seg(struct vmcb *vmcb, int type) 306{ 307 struct vmcb_state *state; 308 struct vmcb_segment *seg; 309 310 state = &vmcb->state; 311 312 switch (type) { 313 case VM_REG_GUEST_CS: 314 seg = &state->cs; 315 break; 316 317 case VM_REG_GUEST_DS: 318 seg = &state->ds; 319 break; 320 321 case VM_REG_GUEST_ES: 322 seg = &state->es; 323 break; 324 325 case VM_REG_GUEST_FS: 326 seg = &state->fs; 327 break; 328 329 case VM_REG_GUEST_GS: 330 seg = &state->gs; 331 break; 332 333 case VM_REG_GUEST_SS: 334 seg = &state->ss; 335 break; 336 337 case VM_REG_GUEST_GDTR: 338 seg = &state->gdt; 339 break; 340 341 case VM_REG_GUEST_IDTR: 342 seg = &state->idt; 343 break; 344 345 case VM_REG_GUEST_LDTR: 346 seg = &state->ldt; 347 break; 348 349 case VM_REG_GUEST_TR: 350 seg = &state->tr; 351 break; 352 353 default: 354 seg = NULL; 355 break; 356 } 357 358 return (seg); 359} 360 361/* 362 * Inject an event to vcpu as described in section 15.20, "Event injection". 363 */ 364int 365vmcb_eventinject(struct vmcb_ctrl *ctrl, int intr_type, int vector, 366 uint32_t error, bool ec_valid) 367{ 368 if (intr_type < VMCB_EVENTINJ_TYPE_INTR || 369 intr_type > VMCB_EVENTINJ_TYPE_INTn) { 370 ERR("Event:%d is not supported by SVM.\n", intr_type); 371 return (EINVAL); 372 } 373 374 if (intr_type == VMCB_EVENTINJ_TYPE_EXCEPTION && vector == IDT_NMI) { 375 ERR("NMI with Exception type is not possible.\n"); 376 return (EINVAL); 377 } 378 379 ctrl->eventinj = (vector & VMCB_EVENTINJ_VECTOR_MASK) | 380 (intr_type << VMCB_EVENTINJ_INTR_TYPE_SHIFT) | 381 (ec_valid ? VMCB_EVENTINJ_EC_VALID : 0) | 382 VMCB_EVENTINJ_VALID; 383 384 ctrl->eventinj |= (uint64_t)error << VMCB_EVENTINJ_ERRCODE_SHIFT; 385 386 return (0); 387} 388