MFC r276247, r276333, r276334, r276335, r276336, r276340, r276350:

Include acle-compat.h directly rather than getting it via sysreg.h.

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7.

Add new TLB and cache maintainence functions for armv6 and armv7.

Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h

Add cache maintenance functions which will be used by startup code to
initially set up the MMU.

Fix a "decl is not a prototype" error noticed by gcc (but not clang).

Update comments (r4 is not used anywhere), use non-profiling entry macros.

Add arm option ARM_NEW_PMAP, to allow us to begin adding the new pmap
code alongside the existing implementation

Add armv6 implementations of cache operations to avoid duplication

MFC 265861, 265870:

Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

MFC 265111: Make a declaration into a proper function prototype.

MFC 264990, 264994, 265020, 265025:

Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.

Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.

Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)

MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,
263030, 263033, 263034, 263056, 263057,

Remove all the redundant external declarations of exception vectors and
runtime setting of the pointers that's scattered around various places.

Remove all traces of support for ARM chips prior to the arm9 series.

Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).

Eliminate irq_dispatch.S. Move the data items it contained into
arm/intr.c and the functionality it provided into arm/exception.S.

Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S.

Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros.

Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Except that didn't work
and the whole change was reverted.

Remove some unnecessary indirection and jump right to the handler functions.

Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32).

Remove the unreferenced DATA() macro.

Remove #include <machine/asmacros.h> from files that don't need it.

MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,
r262585, r262587, r262696, r262712

Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.

aicasm: Don't complain about missing prototypes to ease bootstrap issues.

Vybrid: Add driver for Inter-Integrated Circuit (I2C).

imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.

All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.

mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.

imx6: Add some rudimentary voltage control.

Add an armv7 implementation of cpu_sleep().

Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.

MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,
r262482, r262483, r262531,

Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.

If the L2 cache type is PIPT, pass a physical address for a flush.

Actually set the proper bit to indicate TTB shared memory.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.

Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

Add the bits needed to run SMP on imx6.

Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

Minor tweaks to the imx GPT timer

Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock

MFC r258359, r258742, r258845, r259936, r259640

Apply access flags for managed and unmanaged pages properly on ARMv6/v7

Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.

Enable missing Access Flag for secondary cores on ARMv6/v7

Add identification and necessary type checks for Krait CPU cores.

MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,
r257282, r257332

Wait for DesignWare UART transfers completion before accessing line control

Enable UART busy detection handling for Armada XP - based board

Enable SATA interface on Armada XP
Run mvs SATA driver on Armada XP instead of old mv_sata

Retire arm_remap_nocache() and the data and constants associated with it.

Remove hard-coded mappings related to Armada XP support

Fix-up DTB for Armada XP registers' base according to the actual settings

Change Armada XP kernel load address to the u-boot's end address

Remove not working and deprecated PJ4Bv6 support

Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

Add missing ARMv6 CPU functions to ARM Makefile

MFC r276247, r276333, r276334, r276335, r276336, r276340, r276350:

Include acle-compat.h directly rather than getting it via sysreg.h.

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7.

Add new TLB and cache maintainence functions for armv6 and armv7.

Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h

Add cache maintenance functions which will be used by startup code to
initially set up the MMU.

Fix a "decl is not a prototype" error noticed by gcc (but not clang).

Update comments (r4 is not used anywhere), use non-profiling entry macros.

Add arm option ARM_NEW_PMAP, to allow us to begin adding the new pmap
code alongside the existing implementation

Add armv6 implementations of cache operations to avoid duplication

MFC 265861, 265870:

Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

MFC 265111: Make a declaration into a proper function prototype.

MFC 264990, 264994, 265020, 265025:

Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.

Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.

Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)

MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,
263030, 263033, 263034, 263056, 263057,

Remove all the redundant external declarations of exception vectors and
runtime setting of the pointers that's scattered around various places.

Remove all traces of support for ARM chips prior to the arm9 series.

Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).

Eliminate irq_dispatch.S. Move the data items it contained into
arm/intr.c and the functionality it provided into arm/exception.S.

Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S.

Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.

Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros.

Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Except that didn't work
and the whole change was reverted.

Remove some unnecessary indirection and jump right to the handler functions.

Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32).

Remove the unreferenced DATA() macro.

Remove #include <machine/asmacros.h> from files that don't need it.

MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,
r262585, r262587, r262696, r262712

Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.

aicasm: Don't complain about missing prototypes to ease bootstrap issues.

Vybrid: Add driver for Inter-Integrated Circuit (I2C).

imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.

All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.

mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.

imx6: Add some rudimentary voltage control.

Add an armv7 implementation of cpu_sleep().

Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.

MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,
r262482, r262483, r262531,

Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.

If the L2 cache type is PIPT, pass a physical address for a flush.

Actually set the proper bit to indicate TTB shared memory.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.

Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

Add the bits needed to run SMP on imx6.

Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

Minor tweaks to the imx GPT timer

Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock

MFC r258359, r258742, r258845, r259936, r259640

Apply access flags for managed and unmanaged pages properly on ARMv6/v7

Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.

Enable missing Access Flag for secondary cores on ARMv6/v7

Add identification and necessary type checks for Krait CPU cores.

MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,
r257282, r257332

Wait for DesignWare UART transfers completion before accessing line control

Enable UART busy detection handling for Armada XP - based board

Enable SATA interface on Armada XP
Run mvs SATA driver on Armada XP instead of old mv_sata

Retire arm_remap_nocache() and the data and constants associated with it.

Remove hard-coded mappings related to Armada XP support

Fix-up DTB for Armada XP registers' base according to the actual settings

Change Armada XP kernel load address to the u-boot's end address

Remove not working and deprecated PJ4Bv6 support

Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

Add missing ARMv6 CPU functions to ARM Makefile