cpufunc.h revision 266378
1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 266378 2014-05-17 23:21:53Z ian $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/cpuconf.h> 51#include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53static __inline void 54breakpoint(void) 55{ 56 __asm(".word 0xe7ffffff"); 57} 58 59struct cpu_functions { 60 61 /* CPU functions */ 62 63 u_int (*cf_id) (void); 64 void (*cf_cpwait) (void); 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_domains) (u_int domains); 70 void (*cf_setttb) (u_int ttb); 71 u_int (*cf_faultstatus) (void); 72 u_int (*cf_faultaddress) (void); 73 74 /* TLB functions */ 75 76 void (*cf_tlb_flushID) (void); 77 void (*cf_tlb_flushID_SE) (u_int va); 78 void (*cf_tlb_flushI) (void); 79 void (*cf_tlb_flushI_SE) (u_int va); 80 void (*cf_tlb_flushD) (void); 81 void (*cf_tlb_flushD_SE) (u_int va); 82 83 /* 84 * Cache operations: 85 * 86 * We define the following primitives: 87 * 88 * icache_sync_all Synchronize I-cache 89 * icache_sync_range Synchronize I-cache range 90 * 91 * dcache_wbinv_all Write-back and Invalidate D-cache 92 * dcache_wbinv_range Write-back and Invalidate D-cache range 93 * dcache_inv_range Invalidate D-cache range 94 * dcache_wb_range Write-back D-cache range 95 * 96 * idcache_wbinv_all Write-back and Invalidate D-cache, 97 * Invalidate I-cache 98 * idcache_wbinv_range Write-back and Invalidate D-cache, 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * 107 * ID-cache Invalidate All: 108 * Unlike other functions, this one must never write back. 109 * It is used to intialize the MMU when it is in an unknown 110 * state (such as when it may have lines tagged as valid 111 * that belong to a previous set of mappings). 112 * 113 * I-cache Synch (all or range): 114 * The goal is to synchronize the instruction stream, 115 * so you may beed to write-back dirty D-cache blocks 116 * first. If a range is requested, and you can't 117 * synchronize just a range, you have to hit the whole 118 * thing. 119 * 120 * D-cache Write-Back and Invalidate range: 121 * If you can't WB-Inv a range, you must WB-Inv the 122 * entire D-cache. 123 * 124 * D-cache Invalidate: 125 * If you can't Inv the D-cache, you must Write-Back 126 * and Invalidate. Code that uses this operation 127 * MUST NOT assume that the D-cache will not be written 128 * back to memory. 129 * 130 * D-cache Write-Back: 131 * If you can't Write-back without doing an Inv, 132 * that's fine. Then treat this as a WB-Inv. 133 * Skipping the invalidate is merely an optimization. 134 * 135 * All operations: 136 * Valid virtual addresses must be passed to each 137 * cache operation. 138 */ 139 void (*cf_icache_sync_all) (void); 140 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 141 142 void (*cf_dcache_wbinv_all) (void); 143 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 146 147 void (*cf_idcache_inv_all) (void); 148 void (*cf_idcache_wbinv_all) (void); 149 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 150 void (*cf_l2cache_wbinv_all) (void); 151 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 152 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 153 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 154 155 /* Other functions */ 156 157 void (*cf_flush_prefetchbuf) (void); 158 void (*cf_drain_writebuf) (void); 159 void (*cf_flush_brnchtgt_C) (void); 160 void (*cf_flush_brnchtgt_E) (u_int va); 161 162 void (*cf_sleep) (int mode); 163 164 /* Soft functions */ 165 166 int (*cf_dataabt_fixup) (void *arg); 167 int (*cf_prefetchabt_fixup) (void *arg); 168 169 void (*cf_context_switch) (void); 170 171 void (*cf_setup) (char *string); 172}; 173 174extern struct cpu_functions cpufuncs; 175extern u_int cputype; 176 177#define cpu_id() cpufuncs.cf_id() 178#define cpu_cpwait() cpufuncs.cf_cpwait() 179 180#define cpu_control(c, e) cpufuncs.cf_control(c, e) 181#define cpu_domains(d) cpufuncs.cf_domains(d) 182#define cpu_setttb(t) cpufuncs.cf_setttb(t) 183#define cpu_faultstatus() cpufuncs.cf_faultstatus() 184#define cpu_faultaddress() cpufuncs.cf_faultaddress() 185 186#ifndef SMP 187 188#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 189#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 190#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 191#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 192#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 193#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 194 195#else 196void tlb_broadcast(int); 197 198#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 199#define TLB_BROADCAST /* No need to explicitely send an IPI */ 200#else 201#define TLB_BROADCAST tlb_broadcast(7) 202#endif 203 204#define cpu_tlb_flushID() do { \ 205 cpufuncs.cf_tlb_flushID(); \ 206 TLB_BROADCAST; \ 207} while(0) 208 209#define cpu_tlb_flushID_SE(e) do { \ 210 cpufuncs.cf_tlb_flushID_SE(e); \ 211 TLB_BROADCAST; \ 212} while(0) 213 214 215#define cpu_tlb_flushI() do { \ 216 cpufuncs.cf_tlb_flushI(); \ 217 TLB_BROADCAST; \ 218} while(0) 219 220 221#define cpu_tlb_flushI_SE(e) do { \ 222 cpufuncs.cf_tlb_flushI_SE(e); \ 223 TLB_BROADCAST; \ 224} while(0) 225 226 227#define cpu_tlb_flushD() do { \ 228 cpufuncs.cf_tlb_flushD(); \ 229 TLB_BROADCAST; \ 230} while(0) 231 232 233#define cpu_tlb_flushD_SE(e) do { \ 234 cpufuncs.cf_tlb_flushD_SE(e); \ 235 TLB_BROADCAST; \ 236} while(0) 237 238#endif 239 240#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 241#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 242 243#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 244#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 245#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 246#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 247 248#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 249#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 250#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 251#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 252#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 253#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 254#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 255 256#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 257#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 258#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 259#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 260 261#define cpu_sleep(m) cpufuncs.cf_sleep(m) 262 263#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 264#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 265#define ABORT_FIXUP_OK 0 /* fixup succeeded */ 266#define ABORT_FIXUP_FAILED 1 /* fixup failed */ 267#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 268 269#define cpu_setup(a) cpufuncs.cf_setup(a) 270 271int set_cpufuncs (void); 272#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 273#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 274 275void cpufunc_nullop (void); 276int cpufunc_null_fixup (void *); 277int early_abort_fixup (void *); 278int late_abort_fixup (void *); 279u_int cpufunc_id (void); 280u_int cpufunc_cpuid (void); 281u_int cpufunc_control (u_int clear, u_int bic); 282void cpufunc_domains (u_int domains); 283u_int cpufunc_faultstatus (void); 284u_int cpufunc_faultaddress (void); 285u_int cpu_pfr (int); 286 287#if defined(CPU_FA526) || defined(CPU_FA626TE) 288void fa526_setup (char *arg); 289void fa526_setttb (u_int ttb); 290void fa526_context_switch (void); 291void fa526_cpu_sleep (int); 292void fa526_tlb_flushI_SE (u_int); 293void fa526_tlb_flushID_SE (u_int); 294void fa526_flush_prefetchbuf (void); 295void fa526_flush_brnchtgt_E (u_int); 296 297void fa526_icache_sync_all (void); 298void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 299void fa526_dcache_wbinv_all (void); 300void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 301void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 302void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 303void fa526_idcache_wbinv_all(void); 304void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 305#endif 306 307 308#ifdef CPU_ARM9 309void arm9_setttb (u_int); 310 311void arm9_tlb_flushID_SE (u_int va); 312 313void arm9_icache_sync_all (void); 314void arm9_icache_sync_range (vm_offset_t, vm_size_t); 315 316void arm9_dcache_wbinv_all (void); 317void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 318void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 319void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 320 321void arm9_idcache_wbinv_all (void); 322void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 323 324void arm9_context_switch (void); 325 326void arm9_setup (char *string); 327 328extern unsigned arm9_dcache_sets_max; 329extern unsigned arm9_dcache_sets_inc; 330extern unsigned arm9_dcache_index_max; 331extern unsigned arm9_dcache_index_inc; 332#endif 333 334#if defined(CPU_ARM9E) || defined(CPU_ARM10) 335void arm10_setttb (u_int); 336 337void arm10_tlb_flushID_SE (u_int); 338void arm10_tlb_flushI_SE (u_int); 339 340void arm10_icache_sync_all (void); 341void arm10_icache_sync_range (vm_offset_t, vm_size_t); 342 343void arm10_dcache_wbinv_all (void); 344void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 345void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 346void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 347 348void arm10_idcache_wbinv_all (void); 349void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 350 351void arm10_context_switch (void); 352 353void arm10_setup (char *string); 354 355extern unsigned arm10_dcache_sets_max; 356extern unsigned arm10_dcache_sets_inc; 357extern unsigned arm10_dcache_index_max; 358extern unsigned arm10_dcache_index_inc; 359 360u_int sheeva_control_ext (u_int, u_int); 361void sheeva_cpu_sleep (int); 362void sheeva_setttb (u_int); 363void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 364void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 365void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 366void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 367 368void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 369void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 370void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 371void sheeva_l2cache_wbinv_all (void); 372#endif 373 374#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ 375 defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 376void arm11_setttb (u_int); 377void arm11_sleep (int); 378 379void arm11_tlb_flushID_SE (u_int); 380void arm11_tlb_flushI_SE (u_int); 381 382void arm11_context_switch (void); 383 384void arm11_setup (char *string); 385void arm11_tlb_flushID (void); 386void arm11_tlb_flushI (void); 387void arm11_tlb_flushD (void); 388void arm11_tlb_flushD_SE (u_int va); 389 390void arm11_drain_writebuf (void); 391 392void pj4b_setttb (u_int); 393 394void pj4b_drain_readbuf (void); 395void pj4b_flush_brnchtgt_all (void); 396void pj4b_flush_brnchtgt_va (u_int); 397void pj4b_sleep (int); 398 399void armv6_icache_sync_all (void); 400void armv6_icache_sync_range (vm_offset_t, vm_size_t); 401 402void armv6_dcache_wbinv_all (void); 403void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 404void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 405void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 406 407void armv6_idcache_inv_all (void); 408void armv6_idcache_wbinv_all (void); 409void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 410 411void armv7_setttb (u_int); 412void armv7_tlb_flushID (void); 413void armv7_tlb_flushID_SE (u_int); 414void armv7_icache_sync_all (void); 415void armv7_icache_sync_range (vm_offset_t, vm_size_t); 416void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 417void armv7_idcache_inv_all (void); 418void armv7_dcache_wbinv_all (void); 419void armv7_idcache_wbinv_all (void); 420void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 421void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 422void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 423void armv7_cpu_sleep (int); 424void armv7_setup (char *string); 425void armv7_context_switch (void); 426void armv7_drain_writebuf (void); 427void armv7_sev (void); 428void armv7_sleep (int unused); 429u_int armv7_auxctrl (u_int, u_int); 430void pj4bv7_setup (char *string); 431void pj4b_config (void); 432 433int get_core_id (void); 434 435void armadaxp_idcache_wbinv_all (void); 436 437void cortexa_setup (char *); 438#endif 439 440#if defined(CPU_ARM1136) || defined(CPU_ARM1176) 441void arm11x6_setttb (u_int); 442void arm11x6_idcache_wbinv_all (void); 443void arm11x6_dcache_wbinv_all (void); 444void arm11x6_icache_sync_all (void); 445void arm11x6_flush_prefetchbuf (void); 446void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 447void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 448void arm11x6_setup (char *string); 449void arm11x6_sleep (int); /* no ref. for errata */ 450#endif 451#if defined(CPU_ARM1136) 452void arm1136_sleep_rev0 (int); /* for errata 336501 */ 453#endif 454 455#if defined(CPU_ARM9E) || defined (CPU_ARM10) 456void armv5_ec_setttb(u_int); 457 458void armv5_ec_icache_sync_all(void); 459void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 460 461void armv5_ec_dcache_wbinv_all(void); 462void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 463void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 464void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 465 466void armv5_ec_idcache_wbinv_all(void); 467void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 468#endif 469 470#if defined (CPU_ARM10) 471void armv5_setttb(u_int); 472 473void armv5_icache_sync_all(void); 474void armv5_icache_sync_range(vm_offset_t, vm_size_t); 475 476void armv5_dcache_wbinv_all(void); 477void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 478void armv5_dcache_inv_range(vm_offset_t, vm_size_t); 479void armv5_dcache_wb_range(vm_offset_t, vm_size_t); 480 481void armv5_idcache_wbinv_all(void); 482void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 483 484extern unsigned armv5_dcache_sets_max; 485extern unsigned armv5_dcache_sets_inc; 486extern unsigned armv5_dcache_index_max; 487extern unsigned armv5_dcache_index_inc; 488#endif 489 490#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 491 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 492 defined(CPU_FA526) || defined(CPU_FA626TE) || \ 493 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 494 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 495 496void armv4_tlb_flushID (void); 497void armv4_tlb_flushI (void); 498void armv4_tlb_flushD (void); 499void armv4_tlb_flushD_SE (u_int va); 500 501void armv4_drain_writebuf (void); 502void armv4_idcache_inv_all (void); 503#endif 504 505#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 506 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 507 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 508void xscale_cpwait (void); 509 510void xscale_cpu_sleep (int mode); 511 512u_int xscale_control (u_int clear, u_int bic); 513 514void xscale_setttb (u_int ttb); 515 516void xscale_tlb_flushID_SE (u_int va); 517 518void xscale_cache_flushID (void); 519void xscale_cache_flushI (void); 520void xscale_cache_flushD (void); 521void xscale_cache_flushD_SE (u_int entry); 522 523void xscale_cache_cleanID (void); 524void xscale_cache_cleanD (void); 525void xscale_cache_cleanD_E (u_int entry); 526 527void xscale_cache_clean_minidata (void); 528 529void xscale_cache_purgeID (void); 530void xscale_cache_purgeID_E (u_int entry); 531void xscale_cache_purgeD (void); 532void xscale_cache_purgeD_E (u_int entry); 533 534void xscale_cache_syncI (void); 535void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 536void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 537void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 538void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 539void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 540void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 541 542void xscale_context_switch (void); 543 544void xscale_setup (char *string); 545#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 546 CPU_XSCALE_80219 */ 547 548#ifdef CPU_XSCALE_81342 549 550void xscalec3_l2cache_purge (void); 551void xscalec3_cache_purgeID (void); 552void xscalec3_cache_purgeD (void); 553void xscalec3_cache_cleanID (void); 554void xscalec3_cache_cleanD (void); 555void xscalec3_cache_syncI (void); 556 557void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 558void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 559void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 560void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 561void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 562 563void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 564void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 565void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 566 567 568void xscalec3_setttb (u_int ttb); 569void xscalec3_context_switch (void); 570 571#endif /* CPU_XSCALE_81342 */ 572 573#define tlb_flush cpu_tlb_flushID 574#define setttb cpu_setttb 575#define drain_writebuf cpu_drain_writebuf 576 577/* 578 * Macros for manipulating CPU interrupts 579 */ 580static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 581 582static __inline u_int32_t 583__set_cpsr_c(u_int bic, u_int eor) 584{ 585 u_int32_t tmp, ret; 586 587 __asm __volatile( 588 "mrs %0, cpsr\n" /* Get the CPSR */ 589 "bic %1, %0, %2\n" /* Clear bits */ 590 "eor %1, %1, %3\n" /* XOR bits */ 591 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 592 : "=&r" (ret), "=&r" (tmp) 593 : "r" (bic), "r" (eor) : "memory"); 594 595 return ret; 596} 597 598#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ 599#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ 600 601#define disable_interrupts(mask) \ 602 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ 603 (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 604 605#define enable_interrupts(mask) \ 606 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) 607 608#define restore_interrupts(old_cpsr) \ 609 (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ 610 (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 611 612static __inline register_t 613intr_disable(void) 614{ 615 register_t s; 616 617 s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); 618 return (s); 619} 620 621static __inline void 622intr_restore(register_t s) 623{ 624 625 restore_interrupts(s); 626} 627 628/* Functions to manipulate the CPSR. */ 629u_int SetCPSR(u_int bic, u_int eor); 630u_int GetCPSR(void); 631 632/* 633 * Functions to manipulate cpu r13 634 * (in arm/arm32/setstack.S) 635 */ 636 637void set_stackptr (u_int mode, u_int address); 638u_int get_stackptr (u_int mode); 639 640/* 641 * Miscellany 642 */ 643 644int get_pc_str_offset (void); 645 646/* 647 * CPU functions from locore.S 648 */ 649 650void cpu_reset (void) __attribute__((__noreturn__)); 651 652/* 653 * Cache info variables. 654 */ 655 656/* PRIMARY CACHE VARIABLES */ 657extern int arm_picache_size; 658extern int arm_picache_line_size; 659extern int arm_picache_ways; 660 661extern int arm_pdcache_size; /* and unified */ 662extern int arm_pdcache_line_size; 663extern int arm_pdcache_ways; 664 665extern int arm_pcache_type; 666extern int arm_pcache_unified; 667 668extern int arm_dcache_align; 669extern int arm_dcache_align_mask; 670 671extern u_int arm_cache_level; 672extern u_int arm_cache_loc; 673extern u_int arm_cache_type[14]; 674 675#endif /* _KERNEL */ 676#endif /* _MACHINE_CPUFUNC_H_ */ 677 678/* End of cpufunc.h */ 679