History log of /barrelfish-master/devices/cortex_a9_gt.dev
Revision Date Author Comments
# 9bd8d1d5 03-Apr-2019 Reto Achermann <reto.achermann@inf.ethz.ch>

replacing umlaute and fixing address in headers Haldeneggsteig -> Universitaetsstrasse

Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>


# 96d27a40 30-May-2016 Timothy Roscoe <troscoe@inf.ethz.ch>

Refactored ARMv7-A code.
Cleaner startup process.
Cleaner cross-platform portability (platform.h).
Removed ARMv5.
Removed ARMv7-m
Removed XScale
Changed kernel device paging interface and fixed bugs.

Signed-off-by: Timothy Roscoe <troscoe@inf.ethz.ch>


# c8d0fa0b 04-Feb-2014 Sebastian Wicki <swicki@student.ethz.ch>

Added basic support for the Cortex A9 Global Timer

The Cortex A9 global timer is a 64-bit incrementing counter, which
is memory mapped in the private memory region. Thus, the code for
the timer is currently all in the CPU driver.

To read out the timer in userspace, two system calls are needed,
one for the lower and and one for the upper half of the counter.
The following helper function is provided to correctly read out
the timer value in two 32 bit reads as suggested in the ARM TRM:

errval_t sys_debug_hardware_global_timer_read(uint64_t *ret)