1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/usr.sbin/bhyve/pci_emul.c 248477 2013-03-18 22:38:30Z neel $
|
| 26 * $FreeBSD: head/usr.sbin/bhyve/pci_emul.c 249321 2013-04-10 02:12:39Z neel $ |
27 */
28
29#include <sys/cdefs.h>
|
30__FBSDID("$FreeBSD: head/usr.sbin/bhyve/pci_emul.c 248477 2013-03-18 22:38:30Z neel $");
|
| 30__FBSDID("$FreeBSD: head/usr.sbin/bhyve/pci_emul.c 249321 2013-04-10 02:12:39Z neel $"); |
31
32#include <sys/param.h>
33#include <sys/linker_set.h>
|
| 34#include <sys/errno.h> |
35
36#include <ctype.h>
37#include <stdio.h>
38#include <stdlib.h>
39#include <string.h>
40#include <strings.h>
41#include <assert.h>
|
| 42#include <stdbool.h> |
43
44#include <machine/vmm.h>
45#include <vmmapi.h>
46
47#include "bhyverun.h"
48#include "inout.h"
49#include "mem.h"
50#include "mptbl.h"
51#include "pci_emul.h"
52#include "ioapic.h"
53
54#define CONF1_ADDR_PORT 0x0cf8
55#define CONF1_DATA_PORT 0x0cfc
56
57#define CFGWRITE(pi,off,val,b) \
58do { \
59 if ((b) == 1) { \
60 pci_set_cfgdata8((pi),(off),(val)); \
61 } else if ((b) == 2) { \
62 pci_set_cfgdata16((pi),(off),(val)); \
63 } else { \
64 pci_set_cfgdata32((pi),(off),(val)); \
65 } \
66} while (0)
67
68#define MAXSLOTS (PCI_SLOTMAX + 1)
69#define MAXFUNCS (PCI_FUNCMAX + 1)
70
71static struct slotinfo {
72 char *si_name;
73 char *si_param;
74 struct pci_devinst *si_devi;
75 int si_legacy;
76} pci_slotinfo[MAXSLOTS][MAXFUNCS];
77
78/*
79 * Used to keep track of legacy interrupt owners/requestors
80 */
81#define NLIRQ 16
82
83static struct lirqinfo {
84 int li_generic;
85 int li_acount;
86 struct pci_devinst *li_owner; /* XXX should be a list */
87} lirq[NLIRQ];
88
89SET_DECLARE(pci_devemu_set, struct pci_devemu);
90
91static uint32_t pci_hole_startaddr;
92
93static uint64_t pci_emul_iobase;
94static uint64_t pci_emul_membase32;
95static uint64_t pci_emul_membase64;
96
97#define PCI_EMUL_IOBASE 0x2000
98#define PCI_EMUL_IOLIMIT 0x10000
99
100#define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */
101
102#define PCI_EMUL_MEMBASE64 0xD000000000UL
103#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
104
105static int pci_emul_devices;
106
107/*
108 * I/O access
109 */
110
111/*
112 * Slot options are in the form:
113 *
114 * <slot>[:<func>],<emul>[,<config>]
115 *
116 * slot is 0..31
117 * func is 0..7
118 * emul is a string describing the type of PCI device e.g. virtio-net
119 * config is an optional string, depending on the device, that can be
120 * used for configuration.
121 * Examples are:
122 * 1,virtio-net,tap0
123 * 3:0,dummy
124 */
125static void
126pci_parse_slot_usage(char *aopt)
127{
128 printf("Invalid PCI slot info field \"%s\"\n", aopt);
129 free(aopt);
130}
131
132void
133pci_parse_slot(char *opt, int legacy)
134{
135 char *slot, *func, *emul, *config;
136 char *str, *cpy;
137 int snum, fnum;
138
139 str = cpy = strdup(opt);
140
141 config = NULL;
142
143 if (strchr(str, ':') != NULL) {
144 slot = strsep(&str, ":");
145 func = strsep(&str, ",");
146 } else {
147 slot = strsep(&str, ",");
148 func = NULL;
149 }
150
151 emul = strsep(&str, ",");
152 if (str != NULL) {
153 config = strsep(&str, ",");
154 }
155
156 if (emul == NULL) {
157 pci_parse_slot_usage(cpy);
158 return;
159 }
160
161 snum = atoi(slot);
162 fnum = func ? atoi(func) : 0;
163 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) {
164 pci_parse_slot_usage(cpy);
165 } else {
166 pci_slotinfo[snum][fnum].si_name = emul;
167 pci_slotinfo[snum][fnum].si_param = config;
168 pci_slotinfo[snum][fnum].si_legacy = legacy;
169 }
170}
171
172static int
173pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
174{
175
176 if (offset < pi->pi_msix.pba_offset)
177 return (0);
178
179 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
180 return (0);
181 }
182
183 return (1);
184}
185
186int
187pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
188 uint64_t value)
189{
190 int msix_entry_offset;
191 int tab_index;
192 char *dest;
193
194 /* support only 4 or 8 byte writes */
195 if (size != 4 && size != 8)
196 return (-1);
197
198 /*
199 * Return if table index is beyond what device supports
200 */
201 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
202 if (tab_index >= pi->pi_msix.table_count)
203 return (-1);
204
205 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
206
207 /* support only aligned writes */
208 if ((msix_entry_offset % size) != 0)
209 return (-1);
210
211 dest = (char *)(pi->pi_msix.table + tab_index);
212 dest += msix_entry_offset;
213
214 if (size == 4)
215 *((uint32_t *)dest) = value;
216 else
217 *((uint64_t *)dest) = value;
218
219 return (0);
220}
221
222uint64_t
223pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
224{
225 char *dest;
226 int msix_entry_offset;
227 int tab_index;
228 uint64_t retval = ~0;
229
230 /* support only 4 or 8 byte reads */
231 if (size != 4 && size != 8)
232 return (retval);
233
234 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
235
236 /* support only aligned reads */
237 if ((msix_entry_offset % size) != 0) {
238 return (retval);
239 }
240
241 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
242
243 if (tab_index < pi->pi_msix.table_count) {
244 /* valid MSI-X Table access */
245 dest = (char *)(pi->pi_msix.table + tab_index);
246 dest += msix_entry_offset;
247
248 if (size == 4)
249 retval = *((uint32_t *)dest);
250 else
251 retval = *((uint64_t *)dest);
252 } else if (pci_valid_pba_offset(pi, offset)) {
253 /* return 0 for PBA access */
254 retval = 0;
255 }
256
257 return (retval);
258}
259
260int
261pci_msix_table_bar(struct pci_devinst *pi)
262{
263
264 if (pi->pi_msix.table != NULL)
265 return (pi->pi_msix.table_bar);
266 else
267 return (-1);
268}
269
270int
271pci_msix_pba_bar(struct pci_devinst *pi)
272{
273
274 if (pi->pi_msix.table != NULL)
275 return (pi->pi_msix.pba_bar);
276 else
277 return (-1);
278}
279
280static int
281pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
282 uint32_t *eax, void *arg)
283{
284 struct pci_devinst *pdi = arg;
285 struct pci_devemu *pe = pdi->pi_d;
286 uint64_t offset;
287 int i;
288
289 for (i = 0; i <= PCI_BARMAX; i++) {
290 if (pdi->pi_bar[i].type == PCIBAR_IO &&
291 port >= pdi->pi_bar[i].addr &&
292 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
293 offset = port - pdi->pi_bar[i].addr;
294 if (in)
295 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
296 offset, bytes);
297 else
298 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
299 bytes, *eax);
300 return (0);
301 }
302 }
303 return (-1);
304}
305
306static int
307pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
308 int size, uint64_t *val, void *arg1, long arg2)
309{
310 struct pci_devinst *pdi = arg1;
311 struct pci_devemu *pe = pdi->pi_d;
312 uint64_t offset;
313 int bidx = (int) arg2;
314
315 assert(bidx <= PCI_BARMAX);
316 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
317 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
318 assert(addr >= pdi->pi_bar[bidx].addr &&
319 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
320
321 offset = addr - pdi->pi_bar[bidx].addr;
322
323 if (dir == MEM_F_WRITE)
324 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val);
325 else
326 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size);
327
328 return (0);
329}
330
331
332static int
333pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
334 uint64_t *addr)
335{
336 uint64_t base;
337
338 assert((size & (size - 1)) == 0); /* must be a power of 2 */
339
340 base = roundup2(*baseptr, size);
341
342 if (base + size <= limit) {
343 *addr = base;
344 *baseptr = base + size;
345 return (0);
346 } else
347 return (-1);
348}
349
350int
351pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
352 uint64_t size)
353{
354
355 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
356}
357
|
358/*
359 * Register (or unregister) the MMIO or I/O region associated with the BAR
360 * register 'idx' of an emulated pci device.
361 */
362static void
363modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
364{
365 int error;
366 struct inout_port iop;
367 struct mem_range mr;
368
369 switch (pi->pi_bar[idx].type) {
370 case PCIBAR_IO:
371 bzero(&iop, sizeof(struct inout_port));
372 iop.name = pi->pi_name;
373 iop.port = pi->pi_bar[idx].addr;
374 iop.size = pi->pi_bar[idx].size;
375 if (registration) {
376 iop.flags = IOPORT_F_INOUT;
377 iop.handler = pci_emul_io_handler;
378 iop.arg = pi;
379 error = register_inout(&iop);
380 } else
381 error = unregister_inout(&iop);
382 break;
383 case PCIBAR_MEM32:
384 case PCIBAR_MEM64:
385 bzero(&mr, sizeof(struct mem_range));
386 mr.name = pi->pi_name;
387 mr.base = pi->pi_bar[idx].addr;
388 mr.size = pi->pi_bar[idx].size;
389 if (registration) {
390 mr.flags = MEM_F_RW;
391 mr.handler = pci_emul_mem_handler;
392 mr.arg1 = pi;
393 mr.arg2 = idx;
394 error = register_mem(&mr);
395 } else
396 error = unregister_mem(&mr);
397 break;
398 default:
399 error = EINVAL;
400 break;
401 }
402 assert(error == 0);
403}
404
405static void
406unregister_bar(struct pci_devinst *pi, int idx)
407{
408
409 modify_bar_registration(pi, idx, 0);
410}
411
412static void
413register_bar(struct pci_devinst *pi, int idx)
414{
415
416 modify_bar_registration(pi, idx, 1);
417}
418
419/* Are we decoding i/o port accesses for the emulated pci device? */
420static int
421porten(struct pci_devinst *pi)
422{
423 uint16_t cmd;
424
425 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
426
427 return (cmd & PCIM_CMD_PORTEN);
428}
429
430/* Are we decoding memory accesses for the emulated pci device? */
431static int
432memen(struct pci_devinst *pi)
433{
434 uint16_t cmd;
435
436 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
437
438 return (cmd & PCIM_CMD_MEMEN);
439}
440
441/*
442 * Update the MMIO or I/O address that is decoded by the BAR register.
443 *
444 * If the pci device has enabled the address space decoding then intercept
445 * the address range decoded by the BAR register.
446 */
447static void
448update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
449{
450 int decode;
451
452 if (pi->pi_bar[idx].type == PCIBAR_IO)
453 decode = porten(pi);
454 else
455 decode = memen(pi);
456
457 if (decode)
458 unregister_bar(pi, idx);
459
460 switch (type) {
461 case PCIBAR_IO:
462 case PCIBAR_MEM32:
463 pi->pi_bar[idx].addr = addr;
464 break;
465 case PCIBAR_MEM64:
466 pi->pi_bar[idx].addr &= ~0xffffffffUL;
467 pi->pi_bar[idx].addr |= addr;
468 break;
469 case PCIBAR_MEMHI64:
470 pi->pi_bar[idx].addr &= 0xffffffff;
471 pi->pi_bar[idx].addr |= addr;
472 break;
473 default:
474 assert(0);
475 }
476
477 if (decode)
478 register_bar(pi, idx);
479}
480 |
481int
482pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
483 enum pcibar_type type, uint64_t size)
484{
|
360 int i, error;
|
| 485 int error; |
486 uint64_t *baseptr, limit, addr, mask, lobits, bar;
|
362 struct inout_port iop;
363 struct mem_range memp;
|
487
488 assert(idx >= 0 && idx <= PCI_BARMAX);
489
490 if ((size & (size - 1)) != 0)
491 size = 1UL << flsl(size); /* round up to a power of 2 */
492
|
493 /* Enforce minimum BAR sizes required by the PCI standard */
494 if (type == PCIBAR_IO) {
495 if (size < 4)
496 size = 4;
497 } else {
498 if (size < 16)
499 size = 16;
500 }
501 |
502 switch (type) {
503 case PCIBAR_NONE:
504 baseptr = NULL;
505 addr = mask = lobits = 0;
506 break;
507 case PCIBAR_IO:
508 if (hostbase &&
509 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) {
510 assert(hostbase < PCI_EMUL_IOBASE);
511 baseptr = &hostbase;
512 } else {
513 baseptr = &pci_emul_iobase;
514 }
515 limit = PCI_EMUL_IOLIMIT;
516 mask = PCIM_BAR_IO_BASE;
517 lobits = PCIM_BAR_IO_SPACE;
518 break;
519 case PCIBAR_MEM64:
520 /*
521 * XXX
522 * Some drivers do not work well if the 64-bit BAR is allocated
523 * above 4GB. Allow for this by allocating small requests under
524 * 4GB unless then allocation size is larger than some arbitrary
525 * number (32MB currently).
526 */
527 if (size > 32 * 1024 * 1024) {
528 /*
529 * XXX special case for device requiring peer-peer DMA
530 */
531 if (size == 0x100000000UL)
532 baseptr = &hostbase;
533 else
534 baseptr = &pci_emul_membase64;
535 limit = PCI_EMUL_MEMLIMIT64;
536 mask = PCIM_BAR_MEM_BASE;
537 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
538 PCIM_BAR_MEM_PREFETCH;
539 break;
540 } else {
541 baseptr = &pci_emul_membase32;
542 limit = PCI_EMUL_MEMLIMIT32;
543 mask = PCIM_BAR_MEM_BASE;
544 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
545 }
546 break;
547 case PCIBAR_MEM32:
548 baseptr = &pci_emul_membase32;
549 limit = PCI_EMUL_MEMLIMIT32;
550 mask = PCIM_BAR_MEM_BASE;
551 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
552 break;
553 default:
554 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
555 assert(0);
556 }
557
558 if (baseptr != NULL) {
559 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
560 if (error != 0)
561 return (error);
562 }
563
564 pdi->pi_bar[idx].type = type;
565 pdi->pi_bar[idx].addr = addr;
566 pdi->pi_bar[idx].size = size;
567
568 /* Initialize the BAR register in config space */
569 bar = (addr & mask) | lobits;
570 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
571
572 if (type == PCIBAR_MEM64) {
573 assert(idx + 1 <= PCI_BARMAX);
574 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
575 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
576 }
577
|
446 /* add a handler to intercept accesses to the I/O bar */
447 if (type == PCIBAR_IO) {
448 iop.name = pdi->pi_name;
449 iop.flags = IOPORT_F_INOUT;
450 iop.handler = pci_emul_io_handler;
451 iop.arg = pdi;
|
| 578 register_bar(pdi, idx); |
579
|
453 for (i = 0; i < size; i++) {
454 iop.port = addr + i;
455 register_inout(&iop);
456 }
457 } else if (type == PCIBAR_MEM32 || type == PCIBAR_MEM64) {
458 /* add memory bar intercept handler */
459 memp.name = pdi->pi_name;
460 memp.flags = MEM_F_RW;
461 memp.base = addr;
462 memp.size = size;
463 memp.handler = pci_emul_mem_handler;
464 memp.arg1 = pdi;
465 memp.arg2 = idx;
466
467 error = register_mem(&memp);
468 assert(error == 0);
469 }
470
|
580 return (0);
581}
582
583#define CAP_START_OFFSET 0x40
584static int
585pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
586{
587 int i, capoff, capid, reallen;
588 uint16_t sts;
589
590 static u_char endofcap[4] = {
591 PCIY_RESERVED, 0, 0, 0
592 };
593
594 assert(caplen > 0 && capdata[0] != PCIY_RESERVED);
595
596 reallen = roundup2(caplen, 4); /* dword aligned */
597
598 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
599 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
600 capoff = CAP_START_OFFSET;
601 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
602 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
603 } else {
604 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
605 while (1) {
606 assert((capoff & 0x3) == 0);
607 capid = pci_get_cfgdata8(pi, capoff);
608 if (capid == PCIY_RESERVED)
609 break;
610 capoff = pci_get_cfgdata8(pi, capoff + 1);
611 }
612 }
613
614 /* Check if we have enough space */
615 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1)
616 return (-1);
617
618 /* Copy the capability */
619 for (i = 0; i < caplen; i++)
620 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
621
622 /* Set the next capability pointer */
623 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen);
624
625 /* Copy of the reserved capability which serves as the end marker */
626 for (i = 0; i < sizeof(endofcap); i++)
627 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]);
628
629 return (0);
630}
631
632static struct pci_devemu *
633pci_emul_finddev(char *name)
634{
635 struct pci_devemu **pdpp, *pdp;
636
637 SET_FOREACH(pdpp, pci_devemu_set) {
638 pdp = *pdpp;
639 if (!strcmp(pdp->pe_emu, name)) {
640 return (pdp);
641 }
642 }
643
644 return (NULL);
645}
646
647static void
648pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func,
649 char *params)
650{
651 struct pci_devinst *pdi;
652 pdi = malloc(sizeof(struct pci_devinst));
653 bzero(pdi, sizeof(*pdi));
654
655 pdi->pi_vmctx = ctx;
656 pdi->pi_bus = 0;
657 pdi->pi_slot = slot;
658 pdi->pi_func = func;
659 pdi->pi_d = pde;
660 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
661
662 /* Disable legacy interrupts */
663 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
664 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
665
666 pci_set_cfgdata8(pdi, PCIR_COMMAND,
667 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
668
669 if ((*pde->pe_init)(ctx, pdi, params) != 0) {
670 free(pdi);
671 } else {
672 pci_emul_devices++;
673 pci_slotinfo[slot][func].si_devi = pdi;
674 }
675}
676
677void
678pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
679{
680 int mmc;
681
682 CTASSERT(sizeof(struct msicap) == 14);
683
684 /* Number of msi messages must be a power of 2 between 1 and 32 */
685 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
686 mmc = ffs(msgnum) - 1;
687
688 bzero(msicap, sizeof(struct msicap));
689 msicap->capid = PCIY_MSI;
690 msicap->nextptr = nextptr;
691 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
692}
693
694int
695pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
696{
697 struct msicap msicap;
698
699 pci_populate_msicap(&msicap, msgnum, 0);
700
701 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
702}
703
704static void
705pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
706 uint32_t msix_tab_size, int nextptr)
707{
708 CTASSERT(sizeof(struct msixcap) == 12);
709
710 assert(msix_tab_size % 4096 == 0);
711
712 bzero(msixcap, sizeof(struct msixcap));
713 msixcap->capid = PCIY_MSIX;
714 msixcap->nextptr = nextptr;
715
716 /*
717 * Message Control Register, all fields set to
718 * zero except for the Table Size.
719 * Note: Table size N is encoded as N-1
720 */
721 msixcap->msgctrl = msgnum - 1;
722
723 /*
724 * MSI-X BAR setup:
725 * - MSI-X table start at offset 0
726 * - PBA table starts at a 4K aligned offset after the MSI-X table
727 */
728 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
729 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
730}
731
732static void
733pci_msix_table_init(struct pci_devinst *pi, int table_entries)
734{
735 int i, table_size;
736
737 assert(table_entries > 0);
738 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
739
740 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
741 pi->pi_msix.table = malloc(table_size);
742 bzero(pi->pi_msix.table, table_size);
743
744 /* set mask bit of vector control register */
745 for (i = 0; i < table_entries; i++)
746 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
747}
748
749int
750pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
751{
752 uint16_t pba_index;
753 uint32_t tab_size;
754 struct msixcap msixcap;
755
756 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
757 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
758
759 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
760
761 /* Align table size to nearest 4K */
762 tab_size = roundup2(tab_size, 4096);
763
764 pi->pi_msix.table_bar = barnum;
765 pi->pi_msix.pba_bar = barnum;
766 pi->pi_msix.table_offset = 0;
767 pi->pi_msix.table_count = msgnum;
768 pi->pi_msix.pba_offset = tab_size;
769
770 /* calculate the MMIO size required for MSI-X PBA */
771 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8);
772 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE;
773
774 pci_msix_table_init(pi, msgnum);
775
776 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0);
777
778 /* allocate memory for MSI-X Table and PBA */
779 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
780 tab_size + pi->pi_msix.pba_size);
781
782 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
783 sizeof(msixcap)));
784}
785
786void
787msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
788 int bytes, uint32_t val)
789{
790 uint16_t msgctrl, rwmask;
791 int off, table_bar;
792
793 off = offset - capoff;
794 table_bar = pi->pi_msix.table_bar;
795 /* Message Control Register */
796 if (off == 2 && bytes == 2) {
797 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
798 msgctrl = pci_get_cfgdata16(pi, offset);
799 msgctrl &= ~rwmask;
800 msgctrl |= val & rwmask;
801 val = msgctrl;
802
803 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
804 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
805 }
806
807 CFGWRITE(pi, offset, val, bytes);
808}
809
810void
811msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
812 int bytes, uint32_t val)
813{
814 uint16_t msgctrl, rwmask, msgdata, mme;
815 uint32_t addrlo;
816
817 /*
818 * If guest is writing to the message control register make sure
819 * we do not overwrite read-only fields.
820 */
821 if ((offset - capoff) == 2 && bytes == 2) {
822 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
823 msgctrl = pci_get_cfgdata16(pi, offset);
824 msgctrl &= ~rwmask;
825 msgctrl |= val & rwmask;
826 val = msgctrl;
827
828 addrlo = pci_get_cfgdata32(pi, capoff + 4);
829 if (msgctrl & PCIM_MSICTRL_64BIT)
830 msgdata = pci_get_cfgdata16(pi, capoff + 12);
831 else
832 msgdata = pci_get_cfgdata16(pi, capoff + 8);
833
834 /*
835 * XXX check delivery mode, destination mode etc
836 */
837 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
838 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
839 if (pi->pi_msi.enabled) {
840 pi->pi_msi.cpu = (addrlo >> 12) & 0xff;
841 pi->pi_msi.vector = msgdata & 0xff;
842 pi->pi_msi.msgnum = 1 << (mme >> 4);
843 } else {
844 pi->pi_msi.cpu = 0;
845 pi->pi_msi.vector = 0;
846 pi->pi_msi.msgnum = 0;
847 }
848 }
849
850 CFGWRITE(pi, offset, val, bytes);
851}
852
853void
854pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
855 int bytes, uint32_t val)
856{
857
858 /* XXX don't write to the readonly parts */
859 CFGWRITE(pi, offset, val, bytes);
860}
861
862#define PCIECAP_VERSION 0x2
863int
864pci_emul_add_pciecap(struct pci_devinst *pi, int type)
865{
866 int err;
867 struct pciecap pciecap;
868
869 CTASSERT(sizeof(struct pciecap) == 60);
870
871 if (type != PCIEM_TYPE_ROOT_PORT)
872 return (-1);
873
874 bzero(&pciecap, sizeof(pciecap));
875
876 pciecap.capid = PCIY_EXPRESS;
877 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
878 pciecap.link_capabilities = 0x411; /* gen1, x1 */
879 pciecap.link_status = 0x11; /* gen1, x1 */
880
881 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
882 return (err);
883}
884
885/*
886 * This function assumes that 'coff' is in the capabilities region of the
887 * config space.
888 */
889static void
890pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
891{
892 int capid;
893 uint8_t capoff, nextoff;
894
895 /* Do not allow un-aligned writes */
896 if ((offset & (bytes - 1)) != 0)
897 return;
898
899 /* Find the capability that we want to update */
900 capoff = CAP_START_OFFSET;
901 while (1) {
902 capid = pci_get_cfgdata8(pi, capoff);
903 if (capid == PCIY_RESERVED)
904 break;
905
906 nextoff = pci_get_cfgdata8(pi, capoff + 1);
907 if (offset >= capoff && offset < nextoff)
908 break;
909
910 capoff = nextoff;
911 }
912 assert(offset >= capoff);
913
914 /*
915 * Capability ID and Next Capability Pointer are readonly
916 */
917 if (offset == capoff || offset == capoff + 1)
918 return;
919
920 switch (capid) {
921 case PCIY_MSI:
922 msicap_cfgwrite(pi, capoff, offset, bytes, val);
923 break;
924 case PCIY_MSIX:
925 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
926 break;
927 case PCIY_EXPRESS:
928 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
929 break;
930 default:
931 break;
932 }
933}
934
935static int
936pci_emul_iscap(struct pci_devinst *pi, int offset)
937{
938 int found;
939 uint16_t sts;
940 uint8_t capid, lastoff;
941
942 found = 0;
943 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
944 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
945 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR);
946 while (1) {
947 assert((lastoff & 0x3) == 0);
948 capid = pci_get_cfgdata8(pi, lastoff);
949 if (capid == PCIY_RESERVED)
950 break;
951 lastoff = pci_get_cfgdata8(pi, lastoff + 1);
952 }
953 if (offset >= CAP_START_OFFSET && offset <= lastoff)
954 found = 1;
955 }
956 return (found);
957}
958
959static int
960pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
961 int size, uint64_t *val, void *arg1, long arg2)
962{
963 /*
964 * Ignore writes; return 0xff's for reads. The mem read code
965 * will take care of truncating to the correct size.
966 */
967 if (dir == MEM_F_READ) {
968 *val = 0xffffffffffffffff;
969 }
970
971 return (0);
972}
973
974void
975init_pci(struct vmctx *ctx)
976{
977 struct mem_range memp;
978 struct pci_devemu *pde;
979 struct slotinfo *si;
980 int slot, func;
981 int error;
982
983 pci_hole_startaddr = vm_get_lowmem_limit(ctx);
984
985 pci_emul_iobase = PCI_EMUL_IOBASE;
986 pci_emul_membase32 = pci_hole_startaddr;
987 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
988
989 for (slot = 0; slot < MAXSLOTS; slot++) {
990 for (func = 0; func < MAXFUNCS; func++) {
991 si = &pci_slotinfo[slot][func];
992 if (si->si_name != NULL) {
993 pde = pci_emul_finddev(si->si_name);
994 if (pde != NULL) {
995 pci_emul_init(ctx, pde, slot, func,
996 si->si_param);
997 }
998 }
999 }
1000 }
1001
1002 /*
1003 * Allow ISA IRQs 5,10,11,12, and 15 to be available for
1004 * generic use
1005 */
1006 lirq[5].li_generic = 1;
1007 lirq[10].li_generic = 1;
1008 lirq[11].li_generic = 1;
1009 lirq[12].li_generic = 1;
1010 lirq[15].li_generic = 1;
1011
1012 /*
1013 * Setup the PCI hole to return 0xff's when accessed in a region
1014 * with no devices
1015 */
1016 memset(&memp, 0, sizeof(struct mem_range));
1017 memp.name = "PCI hole";
1018 memp.flags = MEM_F_RW;
1019 memp.base = pci_hole_startaddr;
1020 memp.size = (4ULL * 1024 * 1024 * 1024) - pci_hole_startaddr;
1021 memp.handler = pci_emul_fallback_handler;
1022
1023 error = register_mem_fallback(&memp);
1024 assert(error == 0);
1025}
1026
1027int
1028pci_msi_enabled(struct pci_devinst *pi)
1029{
1030 return (pi->pi_msi.enabled);
1031}
1032
1033int
1034pci_msi_msgnum(struct pci_devinst *pi)
1035{
1036 if (pi->pi_msi.enabled)
1037 return (pi->pi_msi.msgnum);
1038 else
1039 return (0);
1040}
1041
1042int
1043pci_msix_enabled(struct pci_devinst *pi)
1044{
1045
1046 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1047}
1048
1049void
1050pci_generate_msix(struct pci_devinst *pi, int index)
1051{
1052 struct msix_table_entry *mte;
1053
1054 if (!pci_msix_enabled(pi))
1055 return;
1056
1057 if (pi->pi_msix.function_mask)
1058 return;
1059
1060 if (index >= pi->pi_msix.table_count)
1061 return;
1062
1063 mte = &pi->pi_msix.table[index];
1064 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1065 /* XXX Set PBA bit if interrupt is disabled */
1066 vm_lapic_irq(pi->pi_vmctx,
1067 (mte->addr >> 12) & 0xff, mte->msg_data & 0xff);
1068 }
1069}
1070
1071void
1072pci_generate_msi(struct pci_devinst *pi, int msg)
1073{
1074
1075 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) {
1076 vm_lapic_irq(pi->pi_vmctx,
1077 pi->pi_msi.cpu,
1078 pi->pi_msi.vector + msg);
1079 }
1080}
1081
1082int
1083pci_is_legacy(struct pci_devinst *pi)
1084{
1085
1086 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy);
1087}
1088
1089static int
1090pci_lintr_alloc(struct pci_devinst *pi, int vec)
1091{
1092 int i;
1093
1094 assert(vec < NLIRQ);
1095
1096 if (vec == -1) {
1097 for (i = 0; i < NLIRQ; i++) {
1098 if (lirq[i].li_generic &&
1099 lirq[i].li_owner == NULL) {
1100 vec = i;
1101 break;
1102 }
1103 }
1104 } else {
1105 if (lirq[vec].li_owner != NULL) {
1106 vec = -1;
1107 }
1108 }
1109 assert(vec != -1);
1110
1111 lirq[vec].li_owner = pi;
1112 pi->pi_lintr_pin = vec;
1113
1114 return (vec);
1115}
1116
1117int
1118pci_lintr_request(struct pci_devinst *pi, int vec)
1119{
1120
1121 vec = pci_lintr_alloc(pi, vec);
1122 pci_set_cfgdata8(pi, PCIR_INTLINE, vec);
1123 pci_set_cfgdata8(pi, PCIR_INTPIN, 1);
1124 return (0);
1125}
1126
1127void
1128pci_lintr_assert(struct pci_devinst *pi)
1129{
1130
1131 assert(pi->pi_lintr_pin);
1132 ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin);
1133}
1134
1135void
1136pci_lintr_deassert(struct pci_devinst *pi)
1137{
1138
1139 assert(pi->pi_lintr_pin);
1140 ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin);
1141}
1142
1143/*
1144 * Return 1 if the emulated device in 'slot' is a multi-function device.
1145 * Return 0 otherwise.
1146 */
1147static int
1148pci_emul_is_mfdev(int slot)
1149{
1150 int f, numfuncs;
1151
1152 numfuncs = 0;
1153 for (f = 0; f < MAXFUNCS; f++) {
1154 if (pci_slotinfo[slot][f].si_devi != NULL) {
1155 numfuncs++;
1156 }
1157 }
1158 return (numfuncs > 1);
1159}
1160
1161/*
1162 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1163 * whether or not is a multi-function being emulated in the pci 'slot'.
1164 */
1165static void
1166pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv)
1167{
1168 int mfdev;
1169
1170 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1171 mfdev = pci_emul_is_mfdev(slot);
1172 switch (bytes) {
1173 case 1:
1174 case 2:
1175 *rv &= ~PCIM_MFDEV;
1176 if (mfdev) {
1177 *rv |= PCIM_MFDEV;
1178 }
1179 break;
1180 case 4:
1181 *rv &= ~(PCIM_MFDEV << 16);
1182 if (mfdev) {
1183 *rv |= (PCIM_MFDEV << 16);
1184 }
1185 break;
1186 }
1187 }
1188}
1189
1190static int cfgbus, cfgslot, cfgfunc, cfgoff;
1191
1192static int
1193pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1194 uint32_t *eax, void *arg)
1195{
1196 uint32_t x;
1197
1198 assert(!in);
1199
1200 if (bytes != 4)
1201 return (-1);
1202
1203 x = *eax;
1204 cfgoff = x & PCI_REGMAX;
1205 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1206 cfgslot = (x >> 11) & PCI_SLOTMAX;
1207 cfgbus = (x >> 16) & PCI_BUSMAX;
1208
1209 return (0);
1210}
1211INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_OUT, pci_emul_cfgaddr);
1212
|
1213static uint32_t
1214bits_changed(uint32_t old, uint32_t new, uint32_t mask)
1215{
1216
1217 return ((old ^ new) & mask);
1218}
1219
1220static void
1221pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes)
1222{
1223 int i;
1224 uint16_t old;
1225
1226 /*
1227 * The command register is at an offset of 4 bytes and thus the
1228 * guest could write 1, 2 or 4 bytes starting at this offset.
1229 */
1230
1231 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1232 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */
1233 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1234
1235 /*
1236 * If the MMIO or I/O address space decoding has changed then
1237 * register/unregister all BARs that decode that address space.
1238 */
1239 for (i = 0; i < PCI_BARMAX; i++) {
1240 switch (pi->pi_bar[i].type) {
1241 case PCIBAR_NONE:
1242 case PCIBAR_MEMHI64:
1243 break;
1244 case PCIBAR_IO:
1245 /* I/O address space decoding changed? */
1246 if (bits_changed(old, new, PCIM_CMD_PORTEN)) {
1247 if (porten(pi))
1248 register_bar(pi, i);
1249 else
1250 unregister_bar(pi, i);
1251 }
1252 break;
1253 case PCIBAR_MEM32:
1254 case PCIBAR_MEM64:
1255 /* MMIO address space decoding changed? */
1256 if (bits_changed(old, new, PCIM_CMD_MEMEN)) {
1257 if (memen(pi))
1258 register_bar(pi, i);
1259 else
1260 unregister_bar(pi, i);
1261 }
1262 break;
1263 default:
1264 assert(0);
1265 }
1266 }
1267}
1268 |
1269static int
1270pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1271 uint32_t *eax, void *arg)
1272{
1273 struct pci_devinst *pi;
1274 struct pci_devemu *pe;
1275 int coff, idx, needcfg;
|
1111 uint64_t mask, bar;
|
| 1276 uint64_t addr, bar, mask; |
1277
1278 assert(bytes == 1 || bytes == 2 || bytes == 4);
1279
1280 if (cfgbus == 0)
1281 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi;
1282 else
1283 pi = NULL;
1284
1285 coff = cfgoff + (port - CONF1_DATA_PORT);
1286
1287#if 0
1288 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r",
1289 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc);
1290#endif
1291
1292 /*
1293 * Just return if there is no device at this cfgslot:cfgfunc or
1294 * if the guest is doing an un-aligned access
1295 */
1296 if (pi == NULL || (coff & (bytes - 1)) != 0) {
1297 if (in)
1298 *eax = 0xffffffff;
1299 return (0);
1300 }
1301
1302 pe = pi->pi_d;
1303
1304 /*
1305 * Config read
1306 */
1307 if (in) {
1308 /* Let the device emulation override the default handler */
1309 if (pe->pe_cfgread != NULL) {
1310 needcfg = pe->pe_cfgread(ctx, vcpu, pi,
1311 coff, bytes, eax);
1312 } else {
1313 needcfg = 1;
1314 }
1315
1316 if (needcfg) {
1317 if (bytes == 1)
1318 *eax = pci_get_cfgdata8(pi, coff);
1319 else if (bytes == 2)
1320 *eax = pci_get_cfgdata16(pi, coff);
1321 else
1322 *eax = pci_get_cfgdata32(pi, coff);
1323 }
1324
1325 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax);
1326 } else {
1327 /* Let the device emulation override the default handler */
1328 if (pe->pe_cfgwrite != NULL &&
1329 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1330 return (0);
1331
1332 /*
1333 * Special handling for write to BAR registers
1334 */
1335 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1336 /*
1337 * Ignore writes to BAR registers that are not
1338 * 4-byte aligned.
1339 */
1340 if (bytes != 4 || (coff & 0x3) != 0)
1341 return (0);
1342 idx = (coff - PCIR_BAR(0)) / 4;
|
| 1343 mask = ~(pi->pi_bar[idx].size - 1); |
1344 switch (pi->pi_bar[idx].type) {
1345 case PCIBAR_NONE:
|
1180 bar = 0;
|
| 1346 pi->pi_bar[idx].addr = bar = 0; |
1347 break;
1348 case PCIBAR_IO:
|
1183 mask = ~(pi->pi_bar[idx].size - 1);
1184 mask &= PCIM_BAR_IO_BASE;
1185 bar = (*eax & mask) | PCIM_BAR_IO_SPACE;
|
1349 addr = *eax & mask;
1350 addr &= 0xffff;
1351 bar = addr | PCIM_BAR_IO_SPACE;
1352 /*
1353 * Register the new BAR value for interception
1354 */
1355 if (addr != pi->pi_bar[idx].addr) {
1356 update_bar_address(pi, addr, idx,
1357 PCIBAR_IO);
1358 } |
1359 break;
1360 case PCIBAR_MEM32:
|
1188 mask = ~(pi->pi_bar[idx].size - 1);
1189 mask &= PCIM_BAR_MEM_BASE;
1190 bar = *eax & mask;
|
| 1361 addr = bar = *eax & mask; |
1362 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
|
1363 if (addr != pi->pi_bar[idx].addr) {
1364 update_bar_address(pi, addr, idx,
1365 PCIBAR_MEM32);
1366 } |
1367 break;
1368 case PCIBAR_MEM64:
|
1194 mask = ~(pi->pi_bar[idx].size - 1);
1195 mask &= PCIM_BAR_MEM_BASE;
1196 bar = *eax & mask;
|
| 1369 addr = bar = *eax & mask; |
1370 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1371 PCIM_BAR_MEM_PREFETCH;
|
1372 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1373 update_bar_address(pi, addr, idx,
1374 PCIBAR_MEM64);
1375 } |
1376 break;
1377 case PCIBAR_MEMHI64:
1378 mask = ~(pi->pi_bar[idx - 1].size - 1);
|
1202 mask &= PCIM_BAR_MEM_BASE;
1203 bar = ((uint64_t)*eax << 32) & mask;
1204 bar = bar >> 32;
|
1379 addr = ((uint64_t)*eax << 32) & mask;
1380 bar = addr >> 32;
1381 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1382 update_bar_address(pi, addr, idx - 1,
1383 PCIBAR_MEMHI64);
1384 } |
1385 break;
1386 default:
1387 assert(0);
1388 }
1389 pci_set_cfgdata32(pi, coff, bar);
1390
1391 } else if (pci_emul_iscap(pi, coff)) {
1392 pci_emul_capwrite(pi, coff, bytes, *eax);
|
1393 } else if (coff == PCIR_COMMAND) {
1394 pci_emul_cmdwrite(pi, *eax, bytes); |
1395 } else {
1396 CFGWRITE(pi, coff, *eax, bytes);
1397 }
1398 }
1399
1400 return (0);
1401}
1402
1403INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1404INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1405INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1406INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1407
1408/*
1409 * I/O ports to configure PCI IRQ routing. We ignore all writes to it.
1410 */
1411static int
1412pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1413 uint32_t *eax, void *arg)
1414{
1415 assert(in == 0);
1416 return (0);
1417}
1418INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler);
1419INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler);
1420
1421#define PCI_EMUL_TEST
1422#ifdef PCI_EMUL_TEST
1423/*
1424 * Define a dummy test device
1425 */
1426#define DIOSZ 20
1427#define DMEMSZ 4096
1428struct pci_emul_dsoftc {
1429 uint8_t ioregs[DIOSZ];
1430 uint8_t memregs[DMEMSZ];
1431};
1432
1433#define PCI_EMUL_MSI_MSGS 4
1434#define PCI_EMUL_MSIX_MSGS 16
1435
1436static int
1437pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1438{
1439 int error;
1440 struct pci_emul_dsoftc *sc;
1441
1442 sc = malloc(sizeof(struct pci_emul_dsoftc));
1443 memset(sc, 0, sizeof(struct pci_emul_dsoftc));
1444
1445 pi->pi_arg = sc;
1446
1447 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1448 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1449 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1450
1451 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1452 assert(error == 0);
1453
1454 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1455 assert(error == 0);
1456
1457 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1458 assert(error == 0);
1459
1460 return (0);
1461}
1462
1463static void
1464pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1465 uint64_t offset, int size, uint64_t value)
1466{
1467 int i;
1468 struct pci_emul_dsoftc *sc = pi->pi_arg;
1469
1470 if (baridx == 0) {
1471 if (offset + size > DIOSZ) {
1472 printf("diow: iow too large, offset %ld size %d\n",
1473 offset, size);
1474 return;
1475 }
1476
1477 if (size == 1) {
1478 sc->ioregs[offset] = value & 0xff;
1479 } else if (size == 2) {
1480 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
1481 } else if (size == 4) {
1482 *(uint32_t *)&sc->ioregs[offset] = value;
1483 } else {
1484 printf("diow: iow unknown size %d\n", size);
1485 }
1486
1487 /*
1488 * Special magic value to generate an interrupt
1489 */
1490 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
1491 pci_generate_msi(pi, value % pci_msi_msgnum(pi));
1492
1493 if (value == 0xabcdef) {
1494 for (i = 0; i < pci_msi_msgnum(pi); i++)
1495 pci_generate_msi(pi, i);
1496 }
1497 }
1498
1499 if (baridx == 1) {
1500 if (offset + size > DMEMSZ) {
1501 printf("diow: memw too large, offset %ld size %d\n",
1502 offset, size);
1503 return;
1504 }
1505
1506 if (size == 1) {
1507 sc->memregs[offset] = value;
1508 } else if (size == 2) {
1509 *(uint16_t *)&sc->memregs[offset] = value;
1510 } else if (size == 4) {
1511 *(uint32_t *)&sc->memregs[offset] = value;
1512 } else if (size == 8) {
1513 *(uint64_t *)&sc->memregs[offset] = value;
1514 } else {
1515 printf("diow: memw unknown size %d\n", size);
1516 }
1517
1518 /*
1519 * magic interrupt ??
1520 */
1521 }
1522
1523 if (baridx > 1) {
1524 printf("diow: unknown bar idx %d\n", baridx);
1525 }
1526}
1527
1528static uint64_t
1529pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1530 uint64_t offset, int size)
1531{
1532 struct pci_emul_dsoftc *sc = pi->pi_arg;
1533 uint32_t value;
1534
1535 if (baridx == 0) {
1536 if (offset + size > DIOSZ) {
1537 printf("dior: ior too large, offset %ld size %d\n",
1538 offset, size);
1539 return (0);
1540 }
1541
1542 if (size == 1) {
1543 value = sc->ioregs[offset];
1544 } else if (size == 2) {
1545 value = *(uint16_t *) &sc->ioregs[offset];
1546 } else if (size == 4) {
1547 value = *(uint32_t *) &sc->ioregs[offset];
1548 } else {
1549 printf("dior: ior unknown size %d\n", size);
1550 }
1551 }
1552
1553 if (baridx == 1) {
1554 if (offset + size > DMEMSZ) {
1555 printf("dior: memr too large, offset %ld size %d\n",
1556 offset, size);
1557 return (0);
1558 }
1559
1560 if (size == 1) {
1561 value = sc->memregs[offset];
1562 } else if (size == 2) {
1563 value = *(uint16_t *) &sc->memregs[offset];
1564 } else if (size == 4) {
1565 value = *(uint32_t *) &sc->memregs[offset];
1566 } else if (size == 8) {
1567 value = *(uint64_t *) &sc->memregs[offset];
1568 } else {
1569 printf("dior: ior unknown size %d\n", size);
1570 }
1571 }
1572
1573
1574 if (baridx > 1) {
1575 printf("dior: unknown bar idx %d\n", baridx);
1576 return (0);
1577 }
1578
1579 return (value);
1580}
1581
1582struct pci_devemu pci_dummy = {
1583 .pe_emu = "dummy",
1584 .pe_init = pci_emul_dinit,
1585 .pe_barwrite = pci_emul_diow,
1586 .pe_barread = pci_emul_dior
1587};
1588PCI_EMUL_SET(pci_dummy);
1589
1590#endif /* PCI_EMUL_TEST */
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