135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140
141static struct ti_type ti_devs[] = {
142 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
143 "Alteon AceNIC Gigabit Ethernet" },
144 { TC_VENDORID, TC_DEVICEID_3C985,
145 "3Com 3c985-SX Gigabit Ethernet" },
146 { NG_VENDORID, NG_DEVICEID_GA620,
147 "Netgear GA620 Gigabit Ethernet" },
148 { SGI_VENDORID, SGI_DEVICEID_TIGON,
149 "Silicon Graphics Gigabit Ethernet" },
150 { 0, 0, NULL }
151};
152
153static int ti_probe __P((device_t));
154static int ti_attach __P((device_t));
155static int ti_detach __P((device_t));
156static void ti_txeof __P((struct ti_softc *));
157static void ti_rxeof __P((struct ti_softc *));
158
159static void ti_stats_update __P((struct ti_softc *));
160static int ti_encap __P((struct ti_softc *, struct mbuf *,
161 u_int32_t *));
162
163static void ti_intr __P((void *));
164static void ti_start __P((struct ifnet *));
165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
166static void ti_init __P((void *));
167static void ti_init2 __P((struct ti_softc *));
168static void ti_stop __P((struct ti_softc *));
169static void ti_watchdog __P((struct ifnet *));
170static void ti_shutdown __P((device_t));
171static int ti_ifmedia_upd __P((struct ifnet *));
172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
173
174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
176 int, u_int8_t *));
177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
178
179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
181static void ti_setmulti __P((struct ti_softc *));
182
183static void ti_mem __P((struct ti_softc *, u_int32_t,
184 u_int32_t, caddr_t));
185static void ti_loadfw __P((struct ti_softc *));
186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
188 caddr_t, int));
189static void ti_handle_events __P((struct ti_softc *));
190static int ti_alloc_jumbo_mem __P((struct ti_softc *));
191static void *ti_jalloc __P((struct ti_softc *));
192static void ti_jfree __P((caddr_t, u_int));
193static void ti_jref __P((caddr_t, u_int));
194static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
195static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
196static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
197static int ti_init_rx_ring_std __P((struct ti_softc *));
198static void ti_free_rx_ring_std __P((struct ti_softc *));
199static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
200static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
201static int ti_init_rx_ring_mini __P((struct ti_softc *));
202static void ti_free_rx_ring_mini __P((struct ti_softc *));
203static void ti_free_tx_ring __P((struct ti_softc *));
204static int ti_init_tx_ring __P((struct ti_softc *));
205
206static int ti_64bitslot_war __P((struct ti_softc *));
207static int ti_chipinit __P((struct ti_softc *));
208static int ti_gibinit __P((struct ti_softc *));
209
210static device_method_t ti_methods[] = {
211 /* Device interface */
212 DEVMETHOD(device_probe, ti_probe),
213 DEVMETHOD(device_attach, ti_attach),
214 DEVMETHOD(device_detach, ti_detach),
215 DEVMETHOD(device_shutdown, ti_shutdown),
216 { 0, 0 }
217};
218
219static driver_t ti_driver = {
220 "ti",
221 ti_methods,
222 sizeof(struct ti_softc)
223};
224
225static devclass_t ti_devclass;
226
227DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
228
229/*
230 * Send an instruction or address to the EEPROM, check for ACK.
231 */
232static u_int32_t ti_eeprom_putbyte(sc, byte)
233 struct ti_softc *sc;
234 int byte;
235{
236 register int i, ack = 0;
237
238 /*
239 * Make sure we're in TX mode.
240 */
241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
242
243 /*
244 * Feed in each bit and stobe the clock.
245 */
246 for (i = 0x80; i; i >>= 1) {
247 if (byte & i) {
248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
249 } else {
250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
251 }
252 DELAY(1);
253 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
254 DELAY(1);
255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
256 }
257
258 /*
259 * Turn off TX mode.
260 */
261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
262
263 /*
264 * Check for ack.
265 */
266 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
267 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
269
270 return(ack);
271}
272
273/*
274 * Read a byte of data stored in the EEPROM at address 'addr.'
275 * We have to send two address bytes since the EEPROM can hold
276 * more than 256 bytes of data.
277 */
278static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
279 struct ti_softc *sc;
280 int addr;
281 u_int8_t *dest;
282{
283 register int i;
284 u_int8_t byte = 0;
285
286 EEPROM_START;
287
288 /*
289 * Send write control code to EEPROM.
290 */
291 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
292 printf("ti%d: failed to send write command, status: %x\n",
293 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
294 return(1);
295 }
296
297 /*
298 * Send first byte of address of byte we want to read.
299 */
300 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
301 printf("ti%d: failed to send address, status: %x\n",
302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
303 return(1);
304 }
305 /*
306 * Send second byte address of byte we want to read.
307 */
308 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
309 printf("ti%d: failed to send address, status: %x\n",
310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
311 return(1);
312 }
313
314 EEPROM_STOP;
315 EEPROM_START;
316 /*
317 * Send read control code to EEPROM.
318 */
319 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
320 printf("ti%d: failed to send read command, status: %x\n",
321 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
322 return(1);
323 }
324
325 /*
326 * Start reading bits from EEPROM.
327 */
328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
329 for (i = 0x80; i; i >>= 1) {
330 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
331 DELAY(1);
332 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
333 byte |= i;
334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
335 DELAY(1);
336 }
337
338 EEPROM_STOP;
339
340 /*
341 * No ACK generated for read, so just return byte.
342 */
343
344 *dest = byte;
345
346 return(0);
347}
348
349/*
350 * Read a sequence of bytes from the EEPROM.
351 */
352static int ti_read_eeprom(sc, dest, off, cnt)
353 struct ti_softc *sc;
354 caddr_t dest;
355 int off;
356 int cnt;
357{
358 int err = 0, i;
359 u_int8_t byte = 0;
360
361 for (i = 0; i < cnt; i++) {
362 err = ti_eeprom_getbyte(sc, off + i, &byte);
363 if (err)
364 break;
365 *(dest + i) = byte;
366 }
367
368 return(err ? 1 : 0);
369}
370
371/*
372 * NIC memory access function. Can be used to either clear a section
373 * of NIC local memory or (if buf is non-NULL) copy data into it.
374 */
375static void ti_mem(sc, addr, len, buf)
376 struct ti_softc *sc;
377 u_int32_t addr, len;
378 caddr_t buf;
379{
380 int segptr, segsize, cnt;
381 caddr_t ti_winbase, ptr;
382
383 segptr = addr;
384 cnt = len;
385 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
386 ptr = buf;
387
388 while(cnt) {
389 if (cnt < TI_WINLEN)
390 segsize = cnt;
391 else
392 segsize = TI_WINLEN - (segptr % TI_WINLEN);
393 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
394 if (buf == NULL)
395 bzero((char *)ti_winbase + (segptr &
396 (TI_WINLEN - 1)), segsize);
397 else {
398 bcopy((char *)ptr, (char *)ti_winbase +
399 (segptr & (TI_WINLEN - 1)), segsize);
400 ptr += segsize;
401 }
402 segptr += segsize;
403 cnt -= segsize;
404 }
405
406 return;
407}
408
409/*
410 * Load firmware image into the NIC. Check that the firmware revision
411 * is acceptable and see if we want the firmware for the Tigon 1 or
412 * Tigon 2.
413 */
414static void ti_loadfw(sc)
415 struct ti_softc *sc;
416{
417 switch(sc->ti_hwrev) {
418 case TI_HWREV_TIGON:
419 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
420 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
421 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
422 printf("ti%d: firmware revision mismatch; want "
423 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
424 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
425 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
426 tigonFwReleaseMinor, tigonFwReleaseFix);
427 return;
428 }
429 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
430 (caddr_t)tigonFwText);
431 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
432 (caddr_t)tigonFwData);
433 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
434 (caddr_t)tigonFwRodata);
435 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
436 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
437 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
438 break;
439 case TI_HWREV_TIGON_II:
440 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
441 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
442 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
443 printf("ti%d: firmware revision mismatch; want "
444 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
445 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
446 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
447 tigon2FwReleaseMinor, tigon2FwReleaseFix);
448 return;
449 }
450 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
451 (caddr_t)tigon2FwText);
452 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
453 (caddr_t)tigon2FwData);
454 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
455 (caddr_t)tigon2FwRodata);
456 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
457 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
458 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
459 break;
460 default:
461 printf("ti%d: can't load firmware: unknown hardware rev\n",
462 sc->ti_unit);
463 break;
464 }
465
466 return;
467}
468
469/*
470 * Send the NIC a command via the command ring.
471 */
472static void ti_cmd(sc, cmd)
473 struct ti_softc *sc;
474 struct ti_cmd_desc *cmd;
475{
476 u_int32_t index;
477
478 if (sc->ti_rdata->ti_cmd_ring == NULL)
479 return;
480
481 index = sc->ti_cmd_saved_prodidx;
482 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
483 TI_INC(index, TI_CMD_RING_CNT);
484 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
485 sc->ti_cmd_saved_prodidx = index;
486
487 return;
488}
489
490/*
491 * Send the NIC an extended command. The 'len' parameter specifies the
492 * number of command slots to include after the initial command.
493 */
494static void ti_cmd_ext(sc, cmd, arg, len)
495 struct ti_softc *sc;
496 struct ti_cmd_desc *cmd;
497 caddr_t arg;
498 int len;
499{
500 u_int32_t index;
501 register int i;
502
503 if (sc->ti_rdata->ti_cmd_ring == NULL)
504 return;
505
506 index = sc->ti_cmd_saved_prodidx;
507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
508 TI_INC(index, TI_CMD_RING_CNT);
509 for (i = 0; i < len; i++) {
510 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
511 *(u_int32_t *)(&arg[i * 4]));
512 TI_INC(index, TI_CMD_RING_CNT);
513 }
514 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
515 sc->ti_cmd_saved_prodidx = index;
516
517 return;
518}
519
520/*
521 * Handle events that have triggered interrupts.
522 */
523static void ti_handle_events(sc)
524 struct ti_softc *sc;
525{
526 struct ti_event_desc *e;
527
528 if (sc->ti_rdata->ti_event_ring == NULL)
529 return;
530
531 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
532 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
533 switch(e->ti_event) {
534 case TI_EV_LINKSTAT_CHANGED:
535 sc->ti_linkstat = e->ti_code;
536 if (e->ti_code == TI_EV_CODE_LINK_UP)
537 printf("ti%d: 10/100 link up\n", sc->ti_unit);
538 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
539 printf("ti%d: gigabit link up\n", sc->ti_unit);
540 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
541 printf("ti%d: link down\n", sc->ti_unit);
542 break;
543 case TI_EV_ERROR:
544 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
545 printf("ti%d: invalid command\n", sc->ti_unit);
546 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
547 printf("ti%d: unknown command\n", sc->ti_unit);
548 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
549 printf("ti%d: bad config data\n", sc->ti_unit);
550 break;
551 case TI_EV_FIRMWARE_UP:
552 ti_init2(sc);
553 break;
554 case TI_EV_STATS_UPDATED:
555 ti_stats_update(sc);
556 break;
557 case TI_EV_RESET_JUMBO_RING:
558 case TI_EV_MCAST_UPDATED:
559 /* Who cares. */
560 break;
561 default:
562 printf("ti%d: unknown event: %d\n",
563 sc->ti_unit, e->ti_event);
564 break;
565 }
566 /* Advance the consumer index. */
567 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
568 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
569 }
570
571 return;
572}
573
574/*
575 * Memory management for the jumbo receive ring is a pain in the
576 * butt. We need to allocate at least 9018 bytes of space per frame,
577 * _and_ it has to be contiguous (unless you use the extended
578 * jumbo descriptor format). Using malloc() all the time won't
579 * work: malloc() allocates memory in powers of two, which means we
580 * would end up wasting a considerable amount of space by allocating
581 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
582 * to do our own memory management.
583 *
584 * The driver needs to allocate a contiguous chunk of memory at boot
585 * time. We then chop this up ourselves into 9K pieces and use them
586 * as external mbuf storage.
587 *
588 * One issue here is how much memory to allocate. The jumbo ring has
589 * 256 slots in it, but at 9K per slot than can consume over 2MB of
590 * RAM. This is a bit much, especially considering we also need
591 * RAM for the standard ring and mini ring (on the Tigon 2). To
592 * save space, we only actually allocate enough memory for 64 slots
593 * by default, which works out to between 500 and 600K. This can
594 * be tuned by changing a #define in if_tireg.h.
595 */
596
597static int ti_alloc_jumbo_mem(sc)
598 struct ti_softc *sc;
599{
600 caddr_t ptr;
601 register int i;
602 struct ti_jpool_entry *entry;
603
604 /* Grab a big chunk o' storage. */
605 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
607
608 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
609 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
610 return(ENOBUFS);
611 }
612
613 SLIST_INIT(&sc->ti_jfree_listhead);
614 SLIST_INIT(&sc->ti_jinuse_listhead);
615
616 /*
617 * Now divide it up into 9K pieces and save the addresses
618 * in an array. Note that we play an evil trick here by using
619 * the first few bytes in the buffer to hold the the address
620 * of the softc structure for this interface. This is because
621 * ti_jfree() needs it, but it is called by the mbuf management
622 * code which will not pass it to us explicitly.
623 */
624 ptr = sc->ti_cdata.ti_jumbo_buf;
625 for (i = 0; i < TI_JSLOTS; i++) {
626 u_int64_t **aptr;
627 aptr = (u_int64_t **)ptr;
628 aptr[0] = (u_int64_t *)sc;
629 ptr += sizeof(u_int64_t);
630 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
631 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
632 ptr += (TI_JLEN - sizeof(u_int64_t));
633 entry = malloc(sizeof(struct ti_jpool_entry),
634 M_DEVBUF, M_NOWAIT);
635 if (entry == NULL) {
636 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
637 sc->ti_cdata.ti_jumbo_buf = NULL;
638 printf("ti%d: no memory for jumbo "
639 "buffer queue!\n", sc->ti_unit);
640 return(ENOBUFS);
641 }
642 entry->slot = i;
643 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
644 }
645
646 return(0);
647}
648
649/*
650 * Allocate a jumbo buffer.
651 */
652static void *ti_jalloc(sc)
653 struct ti_softc *sc;
654{
655 struct ti_jpool_entry *entry;
656
657 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
658
659 if (entry == NULL) {
660 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
661 return(NULL);
662 }
663
664 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
665 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
666 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
667 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
668}
669
670/*
671 * Adjust usage count on a jumbo buffer. In general this doesn't
672 * get used much because our jumbo buffers don't get passed around
673 * too much, but it's implemented for correctness.
674 */
675static void ti_jref(buf, size)
676 caddr_t buf;
677 u_int size;
678{
679 struct ti_softc *sc;
680 u_int64_t **aptr;
681 register int i;
682
683 /* Extract the softc struct pointer. */
684 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
685 sc = (struct ti_softc *)(aptr[0]);
686
687 if (sc == NULL)
688 panic("ti_jref: can't find softc pointer!");
689
690 if (size != TI_JUMBO_FRAMELEN)
691 panic("ti_jref: adjusting refcount of buf of wrong size!");
692
693 /* calculate the slot this buffer belongs to */
694
695 i = ((vm_offset_t)aptr
696 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
697
698 if ((i < 0) || (i >= TI_JSLOTS))
699 panic("ti_jref: asked to reference buffer "
700 "that we don't manage!");
701 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
702 panic("ti_jref: buffer already free!");
703 else
704 sc->ti_cdata.ti_jslots[i].ti_inuse++;
705
706 return;
707}
708
709/*
710 * Release a jumbo buffer.
711 */
712static void ti_jfree(buf, size)
713 caddr_t buf;
714 u_int size;
715{
716 struct ti_softc *sc;
717 u_int64_t **aptr;
718 int i;
719 struct ti_jpool_entry *entry;
720
721 /* Extract the softc struct pointer. */
722 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
723 sc = (struct ti_softc *)(aptr[0]);
724
725 if (sc == NULL)
726 panic("ti_jfree: can't find softc pointer!");
727
728 if (size != TI_JUMBO_FRAMELEN)
729 panic("ti_jfree: freeing buffer of wrong size!");
730
731 /* calculate the slot this buffer belongs to */
732
733 i = ((vm_offset_t)aptr
734 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
735
736 if ((i < 0) || (i >= TI_JSLOTS))
737 panic("ti_jfree: asked to free buffer that we don't manage!");
738 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
739 panic("ti_jfree: buffer already free!");
740 else {
741 sc->ti_cdata.ti_jslots[i].ti_inuse--;
742 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
743 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
744 if (entry == NULL)
745 panic("ti_jfree: buffer not in use!");
746 entry->slot = i;
747 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
748 jpool_entries);
749 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
750 entry, jpool_entries);
751 }
752 }
753
754 return;
755}
756
757
758/*
759 * Intialize a standard receive ring descriptor.
760 */
761static int ti_newbuf_std(sc, i, m)
762 struct ti_softc *sc;
763 int i;
764 struct mbuf *m;
765{
766 struct mbuf *m_new = NULL;
767 struct ti_rx_desc *r;
768
769 if (m == NULL) {
770 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
771 if (m_new == NULL) {
772 printf("ti%d: mbuf allocation failed "
773 "-- packet dropped!\n", sc->ti_unit);
774 return(ENOBUFS);
775 }
776
777 MCLGET(m_new, M_DONTWAIT);
778 if (!(m_new->m_flags & M_EXT)) {
779 printf("ti%d: cluster allocation failed "
780 "-- packet dropped!\n", sc->ti_unit);
781 m_freem(m_new);
782 return(ENOBUFS);
783 }
784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
785 } else {
786 m_new = m;
787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
788 m_new->m_data = m_new->m_ext.ext_buf;
789 }
790
791 m_adj(m_new, ETHER_ALIGN);
792 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
793 r = &sc->ti_rdata->ti_rx_std_ring[i];
794 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
795 r->ti_type = TI_BDTYPE_RECV_BD;
796#ifdef TI_CSUM_OFFLOAD
797 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
798#else
799 r->ti_flags = 0;
800#endif
801 r->ti_len = m_new->m_len;
802 r->ti_idx = i;
803
804 return(0);
805}
806
807/*
808 * Intialize a mini receive ring descriptor. This only applies to
809 * the Tigon 2.
810 */
811static int ti_newbuf_mini(sc, i, m)
812 struct ti_softc *sc;
813 int i;
814 struct mbuf *m;
815{
816 struct mbuf *m_new = NULL;
817 struct ti_rx_desc *r;
818
819 if (m == NULL) {
820 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
821 if (m_new == NULL) {
822 printf("ti%d: mbuf allocation failed "
823 "-- packet dropped!\n", sc->ti_unit);
824 return(ENOBUFS);
825 }
826 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
827 } else {
828 m_new = m;
829 m_new->m_data = m_new->m_pktdat;
830 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
831 }
832
833 m_adj(m_new, ETHER_ALIGN);
834 r = &sc->ti_rdata->ti_rx_mini_ring[i];
835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
837 r->ti_type = TI_BDTYPE_RECV_BD;
838 r->ti_flags = TI_BDFLAG_MINI_RING;
839#ifdef TI_CSUM_OFFLOAD
840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
841#endif
842 r->ti_len = m_new->m_len;
843 r->ti_idx = i;
844
845 return(0);
846}
847
848/*
849 * Initialize a jumbo receive ring descriptor. This allocates
850 * a jumbo buffer from the pool managed internally by the driver.
851 */
852static int ti_newbuf_jumbo(sc, i, m)
853 struct ti_softc *sc;
854 int i;
855 struct mbuf *m;
856{
857 struct mbuf *m_new = NULL;
858 struct ti_rx_desc *r;
859
860 if (m == NULL) {
861 caddr_t *buf = NULL;
862
863 /* Allocate the mbuf. */
864 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
865 if (m_new == NULL) {
866 printf("ti%d: mbuf allocation failed "
867 "-- packet dropped!\n", sc->ti_unit);
868 return(ENOBUFS);
869 }
870
871 /* Allocate the jumbo buffer */
872 buf = ti_jalloc(sc);
873 if (buf == NULL) {
874 m_freem(m_new);
875 printf("ti%d: jumbo allocation failed "
876 "-- packet dropped!\n", sc->ti_unit);
877 return(ENOBUFS);
878 }
879
880 /* Attach the buffer to the mbuf. */
881 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
882 m_new->m_flags |= M_EXT;
883 m_new->m_len = m_new->m_pkthdr.len =
884 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
885 m_new->m_ext.ext_free = ti_jfree;
886 m_new->m_ext.ext_ref = ti_jref;
887 } else {
888 m_new = m;
889 m_new->m_data = m_new->m_ext.ext_buf;
890 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
891 }
892
893 m_adj(m_new, ETHER_ALIGN);
894 /* Set up the descriptor. */
895 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
896 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
897 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
898 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
899 r->ti_flags = TI_BDFLAG_JUMBO_RING;
900#ifdef TI_CSUM_OFFLOAD
901 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
902#endif
903 r->ti_len = m_new->m_len;
904 r->ti_idx = i;
905
906 return(0);
907}
908
909/*
910 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
911 * that's 1MB or memory, which is a lot. For now, we fill only the first
912 * 256 ring entries and hope that our CPU is fast enough to keep up with
913 * the NIC.
914 */
915static int ti_init_rx_ring_std(sc)
916 struct ti_softc *sc;
917{
918 register int i;
919 struct ti_cmd_desc cmd;
920
921 for (i = 0; i < TI_SSLOTS; i++) {
922 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
923 return(ENOBUFS);
924 };
925
926 TI_UPDATE_STDPROD(sc, i - 1);
927 sc->ti_std = i - 1;
928
929 return(0);
930}
931
932static void ti_free_rx_ring_std(sc)
933 struct ti_softc *sc;
934{
935 register int i;
936
937 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
938 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
939 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
940 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
941 }
942 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
943 sizeof(struct ti_rx_desc));
944 }
945
946 return;
947}
948
949static int ti_init_rx_ring_jumbo(sc)
950 struct ti_softc *sc;
951{
952 register int i;
953 struct ti_cmd_desc cmd;
954
955 for (i = 0; i < (TI_JSLOTS - 20); i++) {
956 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
957 return(ENOBUFS);
958 };
959
960 TI_UPDATE_JUMBOPROD(sc, i - 1);
961 sc->ti_jumbo = i - 1;
962
963 return(0);
964}
965
966static void ti_free_rx_ring_jumbo(sc)
967 struct ti_softc *sc;
968{
969 register int i;
970
971 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
972 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
973 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
974 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
975 }
976 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
977 sizeof(struct ti_rx_desc));
978 }
979
980 return;
981}
982
983static int ti_init_rx_ring_mini(sc)
984 struct ti_softc *sc;
985{
986 register int i;
987
988 for (i = 0; i < TI_MSLOTS; i++) {
989 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
990 return(ENOBUFS);
991 };
992
993 TI_UPDATE_MINIPROD(sc, i - 1);
994 sc->ti_mini = i - 1;
995
996 return(0);
997}
998
999static void ti_free_rx_ring_mini(sc)
1000 struct ti_softc *sc;
1001{
1002 register int i;
1003
1004 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1005 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1006 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1007 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1008 }
1009 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1010 sizeof(struct ti_rx_desc));
1011 }
1012
1013 return;
1014}
1015
1016static void ti_free_tx_ring(sc)
1017 struct ti_softc *sc;
1018{
1019 register int i;
1020
1021 if (sc->ti_rdata->ti_tx_ring == NULL)
1022 return;
1023
1024 for (i = 0; i < TI_TX_RING_CNT; i++) {
1025 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1026 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1027 sc->ti_cdata.ti_tx_chain[i] = NULL;
1028 }
1029 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1030 sizeof(struct ti_tx_desc));
1031 }
1032
1033 return;
1034}
1035
1036static int ti_init_tx_ring(sc)
1037 struct ti_softc *sc;
1038{
1039 sc->ti_txcnt = 0;
1040 sc->ti_tx_saved_considx = 0;
1041 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1042 return(0);
1043}
1044
1045/*
1046 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1047 * but we have to support the old way too so that Tigon 1 cards will
1048 * work.
1049 */
1050void ti_add_mcast(sc, addr)
1051 struct ti_softc *sc;
1052 struct ether_addr *addr;
1053{
1054 struct ti_cmd_desc cmd;
1055 u_int16_t *m;
1056 u_int32_t ext[2] = {0, 0};
1057
1058 m = (u_int16_t *)&addr->octet[0];
1059
1060 switch(sc->ti_hwrev) {
1061 case TI_HWREV_TIGON:
1062 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1063 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1064 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1065 break;
1066 case TI_HWREV_TIGON_II:
1067 ext[0] = htons(m[0]);
1068 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1069 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1070 break;
1071 default:
1072 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1073 break;
1074 }
1075
1076 return;
1077}
1078
1079void ti_del_mcast(sc, addr)
1080 struct ti_softc *sc;
1081 struct ether_addr *addr;
1082{
1083 struct ti_cmd_desc cmd;
1084 u_int16_t *m;
1085 u_int32_t ext[2] = {0, 0};
1086
1087 m = (u_int16_t *)&addr->octet[0];
1088
1089 switch(sc->ti_hwrev) {
1090 case TI_HWREV_TIGON:
1091 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1092 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1093 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1094 break;
1095 case TI_HWREV_TIGON_II:
1096 ext[0] = htons(m[0]);
1097 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1098 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1099 break;
1100 default:
1101 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1102 break;
1103 }
1104
1105 return;
1106}
1107
1108/*
1109 * Configure the Tigon's multicast address filter.
1110 *
1111 * The actual multicast table management is a bit of a pain, thanks to
1112 * slight brain damage on the part of both Alteon and us. With our
1113 * multicast code, we are only alerted when the multicast address table
1114 * changes and at that point we only have the current list of addresses:
1115 * we only know the current state, not the previous state, so we don't
1116 * actually know what addresses were removed or added. The firmware has
1117 * state, but we can't get our grubby mits on it, and there is no 'delete
1118 * all multicast addresses' command. Hence, we have to maintain our own
1119 * state so we know what addresses have been programmed into the NIC at
1120 * any given time.
1121 */
1122static void ti_setmulti(sc)
1123 struct ti_softc *sc;
1124{
1125 struct ifnet *ifp;
1126 struct ifmultiaddr *ifma;
1127 struct ti_cmd_desc cmd;
1128 struct ti_mc_entry *mc;
1129 u_int32_t intrs;
1130
1131 ifp = &sc->arpcom.ac_if;
1132
1133 if (ifp->if_flags & IFF_ALLMULTI) {
1134 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1135 return;
1136 } else {
1137 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1138 }
1139
1140 /* Disable interrupts. */
1141 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1142 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1143
1144 /* First, zot all the existing filters. */
1145 while (sc->ti_mc_listhead.slh_first != NULL) {
1146 mc = sc->ti_mc_listhead.slh_first;
1147 ti_del_mcast(sc, &mc->mc_addr);
1148 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1149 free(mc, M_DEVBUF);
1150 }
1151
1152 /* Now program new ones. */
1153 for (ifma = ifp->if_multiaddrs.lh_first;
1154 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1155 if (ifma->ifma_addr->sa_family != AF_LINK)
1156 continue;
1157 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1158 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1159 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1160 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1161 ti_add_mcast(sc, &mc->mc_addr);
1162 }
1163
1164 /* Re-enable interrupts. */
1165 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1166
1167 return;
1168}
1169
1170/*
1171 * Check to see if the BIOS has configured us for a 64 bit slot when
1172 * we aren't actually in one. If we detect this condition, we can work
1173 * around it on the Tigon 2 by setting a bit in the PCI state register,
1174 * but for the Tigon 1 we must give up and abort the interface attach.
1175 */
1176static int ti_64bitslot_war(sc)
1177 struct ti_softc *sc;
1178{
1179 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1180 CSR_WRITE_4(sc, 0x600, 0);
1181 CSR_WRITE_4(sc, 0x604, 0);
1182 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1183 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1184 if (sc->ti_hwrev == TI_HWREV_TIGON)
1185 return(EINVAL);
1186 else {
1187 TI_SETBIT(sc, TI_PCI_STATE,
1188 TI_PCISTATE_32BIT_BUS);
1189 return(0);
1190 }
1191 }
1192 }
1193
1194 return(0);
1195}
1196
1197/*
1198 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1199 * self-test results.
1200 */
1201static int ti_chipinit(sc)
1202 struct ti_softc *sc;
1203{
1204 u_int32_t cacheline;
1205 u_int32_t pci_writemax = 0;
1206
1207 /* Initialize link to down state. */
1208 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1209
1210 /* Set endianness before we access any non-PCI registers. */
1211#if BYTE_ORDER == BIG_ENDIAN
1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1214#else
1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1217#endif
1218
1219 /* Check the ROM failed bit to see if self-tests passed. */
1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1222 return(ENODEV);
1223 }
1224
1225 /* Halt the CPU. */
1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1227
1228 /* Figure out the hardware revision. */
1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1230 case TI_REV_TIGON_I:
1231 sc->ti_hwrev = TI_HWREV_TIGON;
1232 break;
1233 case TI_REV_TIGON_II:
1234 sc->ti_hwrev = TI_HWREV_TIGON_II;
1235 break;
1236 default:
1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1238 return(ENODEV);
1239 }
1240
1241 /* Do special setup for Tigon 2. */
1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1246 }
1247
1248 /* Set up the PCI state register. */
1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1252 }
1253
1254 /* Clear the read/write max DMA parameters. */
1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1256 TI_PCISTATE_READ_MAXDMA));
1257
1258 /* Get cache line size. */
1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1260
1261 /*
1262 * If the system has set enabled the PCI memory write
1263 * and invalidate command in the command register, set
1264 * the write max parameter accordingly. This is necessary
1265 * to use MWI with the Tigon 2.
1266 */
1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1268 switch(cacheline) {
1269 case 1:
1270 case 4:
1271 case 8:
1272 case 16:
1273 case 32:
1274 case 64:
1275 break;
1276 default:
1277 /* Disable PCI memory write and invalidate. */
1278 if (bootverbose)
1279 printf("ti%d: cache line size %d not "
1280 "supported; disabling PCI MWI\n",
1281 sc->ti_unit, cacheline);
1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1284 break;
1285 }
1286 }
1287
1288#ifdef __brokenalpha__
1289 /*
1290 * From the Alteon sample driver:
1291 * Must insure that we do not cross an 8K (bytes) boundary
1292 * for DMA reads. Our highest limit is 1K bytes. This is a
1293 * restriction on some ALPHA platforms with early revision
1294 * 21174 PCI chipsets, such as the AlphaPC 164lx
1295 */
1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1297#else
1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1299#endif
1300
1301 /* This sets the min dma param all the way up (0xff). */
1302 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1303
1304 /* Configure DMA variables. */
1305#if BYTE_ORDER == BIG_ENDIAN
1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1307 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1308 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1309 TI_OPMODE_DONT_FRAG_JUMBO);
1310#else
1311 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1312 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1313 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1314#endif
1315
1316 /*
1317 * Only allow 1 DMA channel to be active at a time.
1318 * I don't think this is a good idea, but without it
1319 * the firmware racks up lots of nicDmaReadRingFull
1320 * errors.
1321 */
1322#ifndef TI_CSUM_OFFLOAD
1323 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1324#endif
1325
1326 /* Recommended settings from Tigon manual. */
1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1329
1330 if (ti_64bitslot_war(sc)) {
1331 printf("ti%d: bios thinks we're in a 64 bit slot, "
1332 "but we aren't", sc->ti_unit);
1333 return(EINVAL);
1334 }
1335
1336 return(0);
1337}
1338
1339/*
1340 * Initialize the general information block and firmware, and
1341 * start the CPU(s) running.
1342 */
1343static int ti_gibinit(sc)
1344 struct ti_softc *sc;
1345{
1346 struct ti_rcb *rcb;
1347 int i;
1348 struct ifnet *ifp;
1349
1350 ifp = &sc->arpcom.ac_if;
1351
1352 /* Disable interrupts for now. */
1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1354
1355 /* Tell the chip where to find the general information block. */
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1358
1359 /* Load the firmware into SRAM. */
1360 ti_loadfw(sc);
1361
1362 /* Set up the contents of the general info and ring control blocks. */
1363
1364 /* Set up the event ring and producer pointer. */
1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1366
1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1368 rcb->ti_flags = 0;
1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1370 vtophys(&sc->ti_ev_prodidx);
1371 sc->ti_ev_prodidx.ti_idx = 0;
1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1373 sc->ti_ev_saved_considx = 0;
1374
1375 /* Set up the command ring and producer mailbox. */
1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1377
1378 sc->ti_rdata->ti_cmd_ring =
1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1381 rcb->ti_flags = 0;
1382 rcb->ti_max_len = 0;
1383 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1385 }
1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1388 sc->ti_cmd_saved_prodidx = 0;
1389
1390 /*
1391 * Assign the address of the stats refresh buffer.
1392 * We re-use the current stats buffer for this to
1393 * conserve memory.
1394 */
1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1396 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1397
1398 /* Set up the standard receive ring. */
1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1401 rcb->ti_max_len = TI_FRAMELEN;
1402 rcb->ti_flags = 0;
1403#ifdef TI_CSUM_OFFLOAD
1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1405#endif
1406#if NVLAN > 0
1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1408#endif
1409
1410 /* Set up the jumbo receive ring. */
1411 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1412 TI_HOSTADDR(rcb->ti_hostaddr) =
1413 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1414 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1415 rcb->ti_flags = 0;
1416#ifdef TI_CSUM_OFFLOAD
1417 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1418#endif
1419#if NVLAN > 0
1420 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1421#endif
1422
1423 /*
1424 * Set up the mini ring. Only activated on the
1425 * Tigon 2 but the slot in the config block is
1426 * still there on the Tigon 1.
1427 */
1428 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1429 TI_HOSTADDR(rcb->ti_hostaddr) =
1430 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
| 135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140
141static struct ti_type ti_devs[] = {
142 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
143 "Alteon AceNIC Gigabit Ethernet" },
144 { TC_VENDORID, TC_DEVICEID_3C985,
145 "3Com 3c985-SX Gigabit Ethernet" },
146 { NG_VENDORID, NG_DEVICEID_GA620,
147 "Netgear GA620 Gigabit Ethernet" },
148 { SGI_VENDORID, SGI_DEVICEID_TIGON,
149 "Silicon Graphics Gigabit Ethernet" },
150 { 0, 0, NULL }
151};
152
153static int ti_probe __P((device_t));
154static int ti_attach __P((device_t));
155static int ti_detach __P((device_t));
156static void ti_txeof __P((struct ti_softc *));
157static void ti_rxeof __P((struct ti_softc *));
158
159static void ti_stats_update __P((struct ti_softc *));
160static int ti_encap __P((struct ti_softc *, struct mbuf *,
161 u_int32_t *));
162
163static void ti_intr __P((void *));
164static void ti_start __P((struct ifnet *));
165static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
166static void ti_init __P((void *));
167static void ti_init2 __P((struct ti_softc *));
168static void ti_stop __P((struct ti_softc *));
169static void ti_watchdog __P((struct ifnet *));
170static void ti_shutdown __P((device_t));
171static int ti_ifmedia_upd __P((struct ifnet *));
172static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
173
174static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
175static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
176 int, u_int8_t *));
177static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
178
179static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
180static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
181static void ti_setmulti __P((struct ti_softc *));
182
183static void ti_mem __P((struct ti_softc *, u_int32_t,
184 u_int32_t, caddr_t));
185static void ti_loadfw __P((struct ti_softc *));
186static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
187static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
188 caddr_t, int));
189static void ti_handle_events __P((struct ti_softc *));
190static int ti_alloc_jumbo_mem __P((struct ti_softc *));
191static void *ti_jalloc __P((struct ti_softc *));
192static void ti_jfree __P((caddr_t, u_int));
193static void ti_jref __P((caddr_t, u_int));
194static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
195static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
196static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
197static int ti_init_rx_ring_std __P((struct ti_softc *));
198static void ti_free_rx_ring_std __P((struct ti_softc *));
199static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
200static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
201static int ti_init_rx_ring_mini __P((struct ti_softc *));
202static void ti_free_rx_ring_mini __P((struct ti_softc *));
203static void ti_free_tx_ring __P((struct ti_softc *));
204static int ti_init_tx_ring __P((struct ti_softc *));
205
206static int ti_64bitslot_war __P((struct ti_softc *));
207static int ti_chipinit __P((struct ti_softc *));
208static int ti_gibinit __P((struct ti_softc *));
209
210static device_method_t ti_methods[] = {
211 /* Device interface */
212 DEVMETHOD(device_probe, ti_probe),
213 DEVMETHOD(device_attach, ti_attach),
214 DEVMETHOD(device_detach, ti_detach),
215 DEVMETHOD(device_shutdown, ti_shutdown),
216 { 0, 0 }
217};
218
219static driver_t ti_driver = {
220 "ti",
221 ti_methods,
222 sizeof(struct ti_softc)
223};
224
225static devclass_t ti_devclass;
226
227DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
228
229/*
230 * Send an instruction or address to the EEPROM, check for ACK.
231 */
232static u_int32_t ti_eeprom_putbyte(sc, byte)
233 struct ti_softc *sc;
234 int byte;
235{
236 register int i, ack = 0;
237
238 /*
239 * Make sure we're in TX mode.
240 */
241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
242
243 /*
244 * Feed in each bit and stobe the clock.
245 */
246 for (i = 0x80; i; i >>= 1) {
247 if (byte & i) {
248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
249 } else {
250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
251 }
252 DELAY(1);
253 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
254 DELAY(1);
255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
256 }
257
258 /*
259 * Turn off TX mode.
260 */
261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
262
263 /*
264 * Check for ack.
265 */
266 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
267 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
268 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
269
270 return(ack);
271}
272
273/*
274 * Read a byte of data stored in the EEPROM at address 'addr.'
275 * We have to send two address bytes since the EEPROM can hold
276 * more than 256 bytes of data.
277 */
278static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
279 struct ti_softc *sc;
280 int addr;
281 u_int8_t *dest;
282{
283 register int i;
284 u_int8_t byte = 0;
285
286 EEPROM_START;
287
288 /*
289 * Send write control code to EEPROM.
290 */
291 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
292 printf("ti%d: failed to send write command, status: %x\n",
293 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
294 return(1);
295 }
296
297 /*
298 * Send first byte of address of byte we want to read.
299 */
300 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
301 printf("ti%d: failed to send address, status: %x\n",
302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
303 return(1);
304 }
305 /*
306 * Send second byte address of byte we want to read.
307 */
308 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
309 printf("ti%d: failed to send address, status: %x\n",
310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
311 return(1);
312 }
313
314 EEPROM_STOP;
315 EEPROM_START;
316 /*
317 * Send read control code to EEPROM.
318 */
319 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
320 printf("ti%d: failed to send read command, status: %x\n",
321 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
322 return(1);
323 }
324
325 /*
326 * Start reading bits from EEPROM.
327 */
328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
329 for (i = 0x80; i; i >>= 1) {
330 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
331 DELAY(1);
332 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
333 byte |= i;
334 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
335 DELAY(1);
336 }
337
338 EEPROM_STOP;
339
340 /*
341 * No ACK generated for read, so just return byte.
342 */
343
344 *dest = byte;
345
346 return(0);
347}
348
349/*
350 * Read a sequence of bytes from the EEPROM.
351 */
352static int ti_read_eeprom(sc, dest, off, cnt)
353 struct ti_softc *sc;
354 caddr_t dest;
355 int off;
356 int cnt;
357{
358 int err = 0, i;
359 u_int8_t byte = 0;
360
361 for (i = 0; i < cnt; i++) {
362 err = ti_eeprom_getbyte(sc, off + i, &byte);
363 if (err)
364 break;
365 *(dest + i) = byte;
366 }
367
368 return(err ? 1 : 0);
369}
370
371/*
372 * NIC memory access function. Can be used to either clear a section
373 * of NIC local memory or (if buf is non-NULL) copy data into it.
374 */
375static void ti_mem(sc, addr, len, buf)
376 struct ti_softc *sc;
377 u_int32_t addr, len;
378 caddr_t buf;
379{
380 int segptr, segsize, cnt;
381 caddr_t ti_winbase, ptr;
382
383 segptr = addr;
384 cnt = len;
385 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
386 ptr = buf;
387
388 while(cnt) {
389 if (cnt < TI_WINLEN)
390 segsize = cnt;
391 else
392 segsize = TI_WINLEN - (segptr % TI_WINLEN);
393 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
394 if (buf == NULL)
395 bzero((char *)ti_winbase + (segptr &
396 (TI_WINLEN - 1)), segsize);
397 else {
398 bcopy((char *)ptr, (char *)ti_winbase +
399 (segptr & (TI_WINLEN - 1)), segsize);
400 ptr += segsize;
401 }
402 segptr += segsize;
403 cnt -= segsize;
404 }
405
406 return;
407}
408
409/*
410 * Load firmware image into the NIC. Check that the firmware revision
411 * is acceptable and see if we want the firmware for the Tigon 1 or
412 * Tigon 2.
413 */
414static void ti_loadfw(sc)
415 struct ti_softc *sc;
416{
417 switch(sc->ti_hwrev) {
418 case TI_HWREV_TIGON:
419 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
420 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
421 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
422 printf("ti%d: firmware revision mismatch; want "
423 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
424 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
425 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
426 tigonFwReleaseMinor, tigonFwReleaseFix);
427 return;
428 }
429 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
430 (caddr_t)tigonFwText);
431 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
432 (caddr_t)tigonFwData);
433 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
434 (caddr_t)tigonFwRodata);
435 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
436 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
437 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
438 break;
439 case TI_HWREV_TIGON_II:
440 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
441 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
442 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
443 printf("ti%d: firmware revision mismatch; want "
444 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
445 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
446 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
447 tigon2FwReleaseMinor, tigon2FwReleaseFix);
448 return;
449 }
450 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
451 (caddr_t)tigon2FwText);
452 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
453 (caddr_t)tigon2FwData);
454 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
455 (caddr_t)tigon2FwRodata);
456 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
457 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
458 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
459 break;
460 default:
461 printf("ti%d: can't load firmware: unknown hardware rev\n",
462 sc->ti_unit);
463 break;
464 }
465
466 return;
467}
468
469/*
470 * Send the NIC a command via the command ring.
471 */
472static void ti_cmd(sc, cmd)
473 struct ti_softc *sc;
474 struct ti_cmd_desc *cmd;
475{
476 u_int32_t index;
477
478 if (sc->ti_rdata->ti_cmd_ring == NULL)
479 return;
480
481 index = sc->ti_cmd_saved_prodidx;
482 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
483 TI_INC(index, TI_CMD_RING_CNT);
484 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
485 sc->ti_cmd_saved_prodidx = index;
486
487 return;
488}
489
490/*
491 * Send the NIC an extended command. The 'len' parameter specifies the
492 * number of command slots to include after the initial command.
493 */
494static void ti_cmd_ext(sc, cmd, arg, len)
495 struct ti_softc *sc;
496 struct ti_cmd_desc *cmd;
497 caddr_t arg;
498 int len;
499{
500 u_int32_t index;
501 register int i;
502
503 if (sc->ti_rdata->ti_cmd_ring == NULL)
504 return;
505
506 index = sc->ti_cmd_saved_prodidx;
507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
508 TI_INC(index, TI_CMD_RING_CNT);
509 for (i = 0; i < len; i++) {
510 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
511 *(u_int32_t *)(&arg[i * 4]));
512 TI_INC(index, TI_CMD_RING_CNT);
513 }
514 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
515 sc->ti_cmd_saved_prodidx = index;
516
517 return;
518}
519
520/*
521 * Handle events that have triggered interrupts.
522 */
523static void ti_handle_events(sc)
524 struct ti_softc *sc;
525{
526 struct ti_event_desc *e;
527
528 if (sc->ti_rdata->ti_event_ring == NULL)
529 return;
530
531 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
532 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
533 switch(e->ti_event) {
534 case TI_EV_LINKSTAT_CHANGED:
535 sc->ti_linkstat = e->ti_code;
536 if (e->ti_code == TI_EV_CODE_LINK_UP)
537 printf("ti%d: 10/100 link up\n", sc->ti_unit);
538 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
539 printf("ti%d: gigabit link up\n", sc->ti_unit);
540 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
541 printf("ti%d: link down\n", sc->ti_unit);
542 break;
543 case TI_EV_ERROR:
544 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
545 printf("ti%d: invalid command\n", sc->ti_unit);
546 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
547 printf("ti%d: unknown command\n", sc->ti_unit);
548 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
549 printf("ti%d: bad config data\n", sc->ti_unit);
550 break;
551 case TI_EV_FIRMWARE_UP:
552 ti_init2(sc);
553 break;
554 case TI_EV_STATS_UPDATED:
555 ti_stats_update(sc);
556 break;
557 case TI_EV_RESET_JUMBO_RING:
558 case TI_EV_MCAST_UPDATED:
559 /* Who cares. */
560 break;
561 default:
562 printf("ti%d: unknown event: %d\n",
563 sc->ti_unit, e->ti_event);
564 break;
565 }
566 /* Advance the consumer index. */
567 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
568 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
569 }
570
571 return;
572}
573
574/*
575 * Memory management for the jumbo receive ring is a pain in the
576 * butt. We need to allocate at least 9018 bytes of space per frame,
577 * _and_ it has to be contiguous (unless you use the extended
578 * jumbo descriptor format). Using malloc() all the time won't
579 * work: malloc() allocates memory in powers of two, which means we
580 * would end up wasting a considerable amount of space by allocating
581 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
582 * to do our own memory management.
583 *
584 * The driver needs to allocate a contiguous chunk of memory at boot
585 * time. We then chop this up ourselves into 9K pieces and use them
586 * as external mbuf storage.
587 *
588 * One issue here is how much memory to allocate. The jumbo ring has
589 * 256 slots in it, but at 9K per slot than can consume over 2MB of
590 * RAM. This is a bit much, especially considering we also need
591 * RAM for the standard ring and mini ring (on the Tigon 2). To
592 * save space, we only actually allocate enough memory for 64 slots
593 * by default, which works out to between 500 and 600K. This can
594 * be tuned by changing a #define in if_tireg.h.
595 */
596
597static int ti_alloc_jumbo_mem(sc)
598 struct ti_softc *sc;
599{
600 caddr_t ptr;
601 register int i;
602 struct ti_jpool_entry *entry;
603
604 /* Grab a big chunk o' storage. */
605 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
607
608 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
609 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
610 return(ENOBUFS);
611 }
612
613 SLIST_INIT(&sc->ti_jfree_listhead);
614 SLIST_INIT(&sc->ti_jinuse_listhead);
615
616 /*
617 * Now divide it up into 9K pieces and save the addresses
618 * in an array. Note that we play an evil trick here by using
619 * the first few bytes in the buffer to hold the the address
620 * of the softc structure for this interface. This is because
621 * ti_jfree() needs it, but it is called by the mbuf management
622 * code which will not pass it to us explicitly.
623 */
624 ptr = sc->ti_cdata.ti_jumbo_buf;
625 for (i = 0; i < TI_JSLOTS; i++) {
626 u_int64_t **aptr;
627 aptr = (u_int64_t **)ptr;
628 aptr[0] = (u_int64_t *)sc;
629 ptr += sizeof(u_int64_t);
630 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
631 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
632 ptr += (TI_JLEN - sizeof(u_int64_t));
633 entry = malloc(sizeof(struct ti_jpool_entry),
634 M_DEVBUF, M_NOWAIT);
635 if (entry == NULL) {
636 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
637 sc->ti_cdata.ti_jumbo_buf = NULL;
638 printf("ti%d: no memory for jumbo "
639 "buffer queue!\n", sc->ti_unit);
640 return(ENOBUFS);
641 }
642 entry->slot = i;
643 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
644 }
645
646 return(0);
647}
648
649/*
650 * Allocate a jumbo buffer.
651 */
652static void *ti_jalloc(sc)
653 struct ti_softc *sc;
654{
655 struct ti_jpool_entry *entry;
656
657 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
658
659 if (entry == NULL) {
660 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
661 return(NULL);
662 }
663
664 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
665 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
666 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
667 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
668}
669
670/*
671 * Adjust usage count on a jumbo buffer. In general this doesn't
672 * get used much because our jumbo buffers don't get passed around
673 * too much, but it's implemented for correctness.
674 */
675static void ti_jref(buf, size)
676 caddr_t buf;
677 u_int size;
678{
679 struct ti_softc *sc;
680 u_int64_t **aptr;
681 register int i;
682
683 /* Extract the softc struct pointer. */
684 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
685 sc = (struct ti_softc *)(aptr[0]);
686
687 if (sc == NULL)
688 panic("ti_jref: can't find softc pointer!");
689
690 if (size != TI_JUMBO_FRAMELEN)
691 panic("ti_jref: adjusting refcount of buf of wrong size!");
692
693 /* calculate the slot this buffer belongs to */
694
695 i = ((vm_offset_t)aptr
696 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
697
698 if ((i < 0) || (i >= TI_JSLOTS))
699 panic("ti_jref: asked to reference buffer "
700 "that we don't manage!");
701 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
702 panic("ti_jref: buffer already free!");
703 else
704 sc->ti_cdata.ti_jslots[i].ti_inuse++;
705
706 return;
707}
708
709/*
710 * Release a jumbo buffer.
711 */
712static void ti_jfree(buf, size)
713 caddr_t buf;
714 u_int size;
715{
716 struct ti_softc *sc;
717 u_int64_t **aptr;
718 int i;
719 struct ti_jpool_entry *entry;
720
721 /* Extract the softc struct pointer. */
722 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
723 sc = (struct ti_softc *)(aptr[0]);
724
725 if (sc == NULL)
726 panic("ti_jfree: can't find softc pointer!");
727
728 if (size != TI_JUMBO_FRAMELEN)
729 panic("ti_jfree: freeing buffer of wrong size!");
730
731 /* calculate the slot this buffer belongs to */
732
733 i = ((vm_offset_t)aptr
734 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
735
736 if ((i < 0) || (i >= TI_JSLOTS))
737 panic("ti_jfree: asked to free buffer that we don't manage!");
738 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
739 panic("ti_jfree: buffer already free!");
740 else {
741 sc->ti_cdata.ti_jslots[i].ti_inuse--;
742 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
743 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
744 if (entry == NULL)
745 panic("ti_jfree: buffer not in use!");
746 entry->slot = i;
747 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
748 jpool_entries);
749 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
750 entry, jpool_entries);
751 }
752 }
753
754 return;
755}
756
757
758/*
759 * Intialize a standard receive ring descriptor.
760 */
761static int ti_newbuf_std(sc, i, m)
762 struct ti_softc *sc;
763 int i;
764 struct mbuf *m;
765{
766 struct mbuf *m_new = NULL;
767 struct ti_rx_desc *r;
768
769 if (m == NULL) {
770 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
771 if (m_new == NULL) {
772 printf("ti%d: mbuf allocation failed "
773 "-- packet dropped!\n", sc->ti_unit);
774 return(ENOBUFS);
775 }
776
777 MCLGET(m_new, M_DONTWAIT);
778 if (!(m_new->m_flags & M_EXT)) {
779 printf("ti%d: cluster allocation failed "
780 "-- packet dropped!\n", sc->ti_unit);
781 m_freem(m_new);
782 return(ENOBUFS);
783 }
784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
785 } else {
786 m_new = m;
787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
788 m_new->m_data = m_new->m_ext.ext_buf;
789 }
790
791 m_adj(m_new, ETHER_ALIGN);
792 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
793 r = &sc->ti_rdata->ti_rx_std_ring[i];
794 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
795 r->ti_type = TI_BDTYPE_RECV_BD;
796#ifdef TI_CSUM_OFFLOAD
797 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
798#else
799 r->ti_flags = 0;
800#endif
801 r->ti_len = m_new->m_len;
802 r->ti_idx = i;
803
804 return(0);
805}
806
807/*
808 * Intialize a mini receive ring descriptor. This only applies to
809 * the Tigon 2.
810 */
811static int ti_newbuf_mini(sc, i, m)
812 struct ti_softc *sc;
813 int i;
814 struct mbuf *m;
815{
816 struct mbuf *m_new = NULL;
817 struct ti_rx_desc *r;
818
819 if (m == NULL) {
820 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
821 if (m_new == NULL) {
822 printf("ti%d: mbuf allocation failed "
823 "-- packet dropped!\n", sc->ti_unit);
824 return(ENOBUFS);
825 }
826 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
827 } else {
828 m_new = m;
829 m_new->m_data = m_new->m_pktdat;
830 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
831 }
832
833 m_adj(m_new, ETHER_ALIGN);
834 r = &sc->ti_rdata->ti_rx_mini_ring[i];
835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
837 r->ti_type = TI_BDTYPE_RECV_BD;
838 r->ti_flags = TI_BDFLAG_MINI_RING;
839#ifdef TI_CSUM_OFFLOAD
840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
841#endif
842 r->ti_len = m_new->m_len;
843 r->ti_idx = i;
844
845 return(0);
846}
847
848/*
849 * Initialize a jumbo receive ring descriptor. This allocates
850 * a jumbo buffer from the pool managed internally by the driver.
851 */
852static int ti_newbuf_jumbo(sc, i, m)
853 struct ti_softc *sc;
854 int i;
855 struct mbuf *m;
856{
857 struct mbuf *m_new = NULL;
858 struct ti_rx_desc *r;
859
860 if (m == NULL) {
861 caddr_t *buf = NULL;
862
863 /* Allocate the mbuf. */
864 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
865 if (m_new == NULL) {
866 printf("ti%d: mbuf allocation failed "
867 "-- packet dropped!\n", sc->ti_unit);
868 return(ENOBUFS);
869 }
870
871 /* Allocate the jumbo buffer */
872 buf = ti_jalloc(sc);
873 if (buf == NULL) {
874 m_freem(m_new);
875 printf("ti%d: jumbo allocation failed "
876 "-- packet dropped!\n", sc->ti_unit);
877 return(ENOBUFS);
878 }
879
880 /* Attach the buffer to the mbuf. */
881 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
882 m_new->m_flags |= M_EXT;
883 m_new->m_len = m_new->m_pkthdr.len =
884 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
885 m_new->m_ext.ext_free = ti_jfree;
886 m_new->m_ext.ext_ref = ti_jref;
887 } else {
888 m_new = m;
889 m_new->m_data = m_new->m_ext.ext_buf;
890 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
891 }
892
893 m_adj(m_new, ETHER_ALIGN);
894 /* Set up the descriptor. */
895 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
896 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
897 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
898 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
899 r->ti_flags = TI_BDFLAG_JUMBO_RING;
900#ifdef TI_CSUM_OFFLOAD
901 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
902#endif
903 r->ti_len = m_new->m_len;
904 r->ti_idx = i;
905
906 return(0);
907}
908
909/*
910 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
911 * that's 1MB or memory, which is a lot. For now, we fill only the first
912 * 256 ring entries and hope that our CPU is fast enough to keep up with
913 * the NIC.
914 */
915static int ti_init_rx_ring_std(sc)
916 struct ti_softc *sc;
917{
918 register int i;
919 struct ti_cmd_desc cmd;
920
921 for (i = 0; i < TI_SSLOTS; i++) {
922 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
923 return(ENOBUFS);
924 };
925
926 TI_UPDATE_STDPROD(sc, i - 1);
927 sc->ti_std = i - 1;
928
929 return(0);
930}
931
932static void ti_free_rx_ring_std(sc)
933 struct ti_softc *sc;
934{
935 register int i;
936
937 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
938 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
939 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
940 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
941 }
942 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
943 sizeof(struct ti_rx_desc));
944 }
945
946 return;
947}
948
949static int ti_init_rx_ring_jumbo(sc)
950 struct ti_softc *sc;
951{
952 register int i;
953 struct ti_cmd_desc cmd;
954
955 for (i = 0; i < (TI_JSLOTS - 20); i++) {
956 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
957 return(ENOBUFS);
958 };
959
960 TI_UPDATE_JUMBOPROD(sc, i - 1);
961 sc->ti_jumbo = i - 1;
962
963 return(0);
964}
965
966static void ti_free_rx_ring_jumbo(sc)
967 struct ti_softc *sc;
968{
969 register int i;
970
971 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
972 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
973 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
974 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
975 }
976 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
977 sizeof(struct ti_rx_desc));
978 }
979
980 return;
981}
982
983static int ti_init_rx_ring_mini(sc)
984 struct ti_softc *sc;
985{
986 register int i;
987
988 for (i = 0; i < TI_MSLOTS; i++) {
989 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
990 return(ENOBUFS);
991 };
992
993 TI_UPDATE_MINIPROD(sc, i - 1);
994 sc->ti_mini = i - 1;
995
996 return(0);
997}
998
999static void ti_free_rx_ring_mini(sc)
1000 struct ti_softc *sc;
1001{
1002 register int i;
1003
1004 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1005 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1006 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1007 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1008 }
1009 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1010 sizeof(struct ti_rx_desc));
1011 }
1012
1013 return;
1014}
1015
1016static void ti_free_tx_ring(sc)
1017 struct ti_softc *sc;
1018{
1019 register int i;
1020
1021 if (sc->ti_rdata->ti_tx_ring == NULL)
1022 return;
1023
1024 for (i = 0; i < TI_TX_RING_CNT; i++) {
1025 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1026 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1027 sc->ti_cdata.ti_tx_chain[i] = NULL;
1028 }
1029 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1030 sizeof(struct ti_tx_desc));
1031 }
1032
1033 return;
1034}
1035
1036static int ti_init_tx_ring(sc)
1037 struct ti_softc *sc;
1038{
1039 sc->ti_txcnt = 0;
1040 sc->ti_tx_saved_considx = 0;
1041 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1042 return(0);
1043}
1044
1045/*
1046 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1047 * but we have to support the old way too so that Tigon 1 cards will
1048 * work.
1049 */
1050void ti_add_mcast(sc, addr)
1051 struct ti_softc *sc;
1052 struct ether_addr *addr;
1053{
1054 struct ti_cmd_desc cmd;
1055 u_int16_t *m;
1056 u_int32_t ext[2] = {0, 0};
1057
1058 m = (u_int16_t *)&addr->octet[0];
1059
1060 switch(sc->ti_hwrev) {
1061 case TI_HWREV_TIGON:
1062 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1063 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1064 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1065 break;
1066 case TI_HWREV_TIGON_II:
1067 ext[0] = htons(m[0]);
1068 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1069 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1070 break;
1071 default:
1072 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1073 break;
1074 }
1075
1076 return;
1077}
1078
1079void ti_del_mcast(sc, addr)
1080 struct ti_softc *sc;
1081 struct ether_addr *addr;
1082{
1083 struct ti_cmd_desc cmd;
1084 u_int16_t *m;
1085 u_int32_t ext[2] = {0, 0};
1086
1087 m = (u_int16_t *)&addr->octet[0];
1088
1089 switch(sc->ti_hwrev) {
1090 case TI_HWREV_TIGON:
1091 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1092 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1093 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1094 break;
1095 case TI_HWREV_TIGON_II:
1096 ext[0] = htons(m[0]);
1097 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1098 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1099 break;
1100 default:
1101 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1102 break;
1103 }
1104
1105 return;
1106}
1107
1108/*
1109 * Configure the Tigon's multicast address filter.
1110 *
1111 * The actual multicast table management is a bit of a pain, thanks to
1112 * slight brain damage on the part of both Alteon and us. With our
1113 * multicast code, we are only alerted when the multicast address table
1114 * changes and at that point we only have the current list of addresses:
1115 * we only know the current state, not the previous state, so we don't
1116 * actually know what addresses were removed or added. The firmware has
1117 * state, but we can't get our grubby mits on it, and there is no 'delete
1118 * all multicast addresses' command. Hence, we have to maintain our own
1119 * state so we know what addresses have been programmed into the NIC at
1120 * any given time.
1121 */
1122static void ti_setmulti(sc)
1123 struct ti_softc *sc;
1124{
1125 struct ifnet *ifp;
1126 struct ifmultiaddr *ifma;
1127 struct ti_cmd_desc cmd;
1128 struct ti_mc_entry *mc;
1129 u_int32_t intrs;
1130
1131 ifp = &sc->arpcom.ac_if;
1132
1133 if (ifp->if_flags & IFF_ALLMULTI) {
1134 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1135 return;
1136 } else {
1137 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1138 }
1139
1140 /* Disable interrupts. */
1141 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1142 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1143
1144 /* First, zot all the existing filters. */
1145 while (sc->ti_mc_listhead.slh_first != NULL) {
1146 mc = sc->ti_mc_listhead.slh_first;
1147 ti_del_mcast(sc, &mc->mc_addr);
1148 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1149 free(mc, M_DEVBUF);
1150 }
1151
1152 /* Now program new ones. */
1153 for (ifma = ifp->if_multiaddrs.lh_first;
1154 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1155 if (ifma->ifma_addr->sa_family != AF_LINK)
1156 continue;
1157 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1158 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1159 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1160 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1161 ti_add_mcast(sc, &mc->mc_addr);
1162 }
1163
1164 /* Re-enable interrupts. */
1165 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1166
1167 return;
1168}
1169
1170/*
1171 * Check to see if the BIOS has configured us for a 64 bit slot when
1172 * we aren't actually in one. If we detect this condition, we can work
1173 * around it on the Tigon 2 by setting a bit in the PCI state register,
1174 * but for the Tigon 1 we must give up and abort the interface attach.
1175 */
1176static int ti_64bitslot_war(sc)
1177 struct ti_softc *sc;
1178{
1179 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1180 CSR_WRITE_4(sc, 0x600, 0);
1181 CSR_WRITE_4(sc, 0x604, 0);
1182 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1183 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1184 if (sc->ti_hwrev == TI_HWREV_TIGON)
1185 return(EINVAL);
1186 else {
1187 TI_SETBIT(sc, TI_PCI_STATE,
1188 TI_PCISTATE_32BIT_BUS);
1189 return(0);
1190 }
1191 }
1192 }
1193
1194 return(0);
1195}
1196
1197/*
1198 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1199 * self-test results.
1200 */
1201static int ti_chipinit(sc)
1202 struct ti_softc *sc;
1203{
1204 u_int32_t cacheline;
1205 u_int32_t pci_writemax = 0;
1206
1207 /* Initialize link to down state. */
1208 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1209
1210 /* Set endianness before we access any non-PCI registers. */
1211#if BYTE_ORDER == BIG_ENDIAN
1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1214#else
1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1217#endif
1218
1219 /* Check the ROM failed bit to see if self-tests passed. */
1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1222 return(ENODEV);
1223 }
1224
1225 /* Halt the CPU. */
1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1227
1228 /* Figure out the hardware revision. */
1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1230 case TI_REV_TIGON_I:
1231 sc->ti_hwrev = TI_HWREV_TIGON;
1232 break;
1233 case TI_REV_TIGON_II:
1234 sc->ti_hwrev = TI_HWREV_TIGON_II;
1235 break;
1236 default:
1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1238 return(ENODEV);
1239 }
1240
1241 /* Do special setup for Tigon 2. */
1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1246 }
1247
1248 /* Set up the PCI state register. */
1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1252 }
1253
1254 /* Clear the read/write max DMA parameters. */
1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1256 TI_PCISTATE_READ_MAXDMA));
1257
1258 /* Get cache line size. */
1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1260
1261 /*
1262 * If the system has set enabled the PCI memory write
1263 * and invalidate command in the command register, set
1264 * the write max parameter accordingly. This is necessary
1265 * to use MWI with the Tigon 2.
1266 */
1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1268 switch(cacheline) {
1269 case 1:
1270 case 4:
1271 case 8:
1272 case 16:
1273 case 32:
1274 case 64:
1275 break;
1276 default:
1277 /* Disable PCI memory write and invalidate. */
1278 if (bootverbose)
1279 printf("ti%d: cache line size %d not "
1280 "supported; disabling PCI MWI\n",
1281 sc->ti_unit, cacheline);
1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1284 break;
1285 }
1286 }
1287
1288#ifdef __brokenalpha__
1289 /*
1290 * From the Alteon sample driver:
1291 * Must insure that we do not cross an 8K (bytes) boundary
1292 * for DMA reads. Our highest limit is 1K bytes. This is a
1293 * restriction on some ALPHA platforms with early revision
1294 * 21174 PCI chipsets, such as the AlphaPC 164lx
1295 */
1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1297#else
1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1299#endif
1300
1301 /* This sets the min dma param all the way up (0xff). */
1302 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1303
1304 /* Configure DMA variables. */
1305#if BYTE_ORDER == BIG_ENDIAN
1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1307 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1308 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1309 TI_OPMODE_DONT_FRAG_JUMBO);
1310#else
1311 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1312 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1313 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1314#endif
1315
1316 /*
1317 * Only allow 1 DMA channel to be active at a time.
1318 * I don't think this is a good idea, but without it
1319 * the firmware racks up lots of nicDmaReadRingFull
1320 * errors.
1321 */
1322#ifndef TI_CSUM_OFFLOAD
1323 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1324#endif
1325
1326 /* Recommended settings from Tigon manual. */
1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1329
1330 if (ti_64bitslot_war(sc)) {
1331 printf("ti%d: bios thinks we're in a 64 bit slot, "
1332 "but we aren't", sc->ti_unit);
1333 return(EINVAL);
1334 }
1335
1336 return(0);
1337}
1338
1339/*
1340 * Initialize the general information block and firmware, and
1341 * start the CPU(s) running.
1342 */
1343static int ti_gibinit(sc)
1344 struct ti_softc *sc;
1345{
1346 struct ti_rcb *rcb;
1347 int i;
1348 struct ifnet *ifp;
1349
1350 ifp = &sc->arpcom.ac_if;
1351
1352 /* Disable interrupts for now. */
1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1354
1355 /* Tell the chip where to find the general information block. */
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1358
1359 /* Load the firmware into SRAM. */
1360 ti_loadfw(sc);
1361
1362 /* Set up the contents of the general info and ring control blocks. */
1363
1364 /* Set up the event ring and producer pointer. */
1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1366
1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1368 rcb->ti_flags = 0;
1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1370 vtophys(&sc->ti_ev_prodidx);
1371 sc->ti_ev_prodidx.ti_idx = 0;
1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1373 sc->ti_ev_saved_considx = 0;
1374
1375 /* Set up the command ring and producer mailbox. */
1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1377
1378 sc->ti_rdata->ti_cmd_ring =
1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1381 rcb->ti_flags = 0;
1382 rcb->ti_max_len = 0;
1383 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1385 }
1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1388 sc->ti_cmd_saved_prodidx = 0;
1389
1390 /*
1391 * Assign the address of the stats refresh buffer.
1392 * We re-use the current stats buffer for this to
1393 * conserve memory.
1394 */
1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1396 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1397
1398 /* Set up the standard receive ring. */
1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1401 rcb->ti_max_len = TI_FRAMELEN;
1402 rcb->ti_flags = 0;
1403#ifdef TI_CSUM_OFFLOAD
1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1405#endif
1406#if NVLAN > 0
1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1408#endif
1409
1410 /* Set up the jumbo receive ring. */
1411 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1412 TI_HOSTADDR(rcb->ti_hostaddr) =
1413 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1414 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1415 rcb->ti_flags = 0;
1416#ifdef TI_CSUM_OFFLOAD
1417 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1418#endif
1419#if NVLAN > 0
1420 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1421#endif
1422
1423 /*
1424 * Set up the mini ring. Only activated on the
1425 * Tigon 2 but the slot in the config block is
1426 * still there on the Tigon 1.
1427 */
1428 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1429 TI_HOSTADDR(rcb->ti_hostaddr) =
1430 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
|
1432 if (sc->ti_hwrev == TI_HWREV_TIGON)
1433 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1434 else
1435 rcb->ti_flags = 0;
1436#ifdef TI_CSUM_OFFLOAD
1437 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1438#endif
1439#if NVLAN > 0
1440 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1441#endif
1442
1443 /*
1444 * Set up the receive return ring.
1445 */
1446 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1447 TI_HOSTADDR(rcb->ti_hostaddr) =
1448 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1449 rcb->ti_flags = 0;
1450 rcb->ti_max_len = TI_RETURN_RING_CNT;
1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1452 vtophys(&sc->ti_return_prodidx);
1453
1454 /*
1455 * Set up the tx ring. Note: for the Tigon 2, we have the option
1456 * of putting the transmit ring in the host's address space and
1457 * letting the chip DMA it instead of leaving the ring in the NIC's
1458 * memory and accessing it through the shared memory region. We
1459 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1460 * so we have to revert to the shared memory scheme if we detect
1461 * a Tigon 1 chip.
1462 */
1463 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1464 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1465 sc->ti_rdata->ti_tx_ring_nic =
1466 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1467 }
1468 bzero((char *)sc->ti_rdata->ti_tx_ring,
1469 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1470 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1471 if (sc->ti_hwrev == TI_HWREV_TIGON)
1472 rcb->ti_flags = 0;
1473 else
1474 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1475#if NVLAN > 0
1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1477#endif
1478 rcb->ti_max_len = TI_TX_RING_CNT;
1479 if (sc->ti_hwrev == TI_HWREV_TIGON)
1480 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1481 else
1482 TI_HOSTADDR(rcb->ti_hostaddr) =
1483 vtophys(&sc->ti_rdata->ti_tx_ring);
1484 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1485 vtophys(&sc->ti_tx_considx);
1486
1487 /* Set up tuneables */
1488 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1490 (sc->ti_rx_coal_ticks / 10));
1491 else
1492 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1493 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1494 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1495 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1496 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1497 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1498
1499 /* Turn interrupts on. */
1500 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1501 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1502
1503 /* Start CPU. */
1504 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1505
1506 return(0);
1507}
1508
1509/*
1510 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1511 * against our list and return its name if we find a match.
1512 */
1513static int ti_probe(dev)
1514 device_t dev;
1515{
1516 struct ti_type *t;
1517
1518 t = ti_devs;
1519
1520 while(t->ti_name != NULL) {
1521 if ((pci_get_vendor(dev) == t->ti_vid) &&
1522 (pci_get_device(dev) == t->ti_did)) {
1523 device_set_desc(dev, t->ti_name);
1524 return(0);
1525 }
1526 t++;
1527 }
1528
1529 return(ENXIO);
1530}
1531
1532static int ti_attach(dev)
1533 device_t dev;
1534{
1535 int s;
1536 u_int32_t command;
1537 struct ifnet *ifp;
1538 struct ti_softc *sc;
1539 int unit, error = 0, rid;
1540
1541 s = splimp();
1542
1543 sc = device_get_softc(dev);
1544 unit = device_get_unit(dev);
1545 bzero(sc, sizeof(struct ti_softc));
1546
1547 /*
1548 * Map control/status registers.
1549 */
1550 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1551 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1552 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
1553 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1554
1555 if (!(command & PCIM_CMD_MEMEN)) {
1556 printf("ti%d: failed to enable memory mapping!\n", unit);
1557 error = ENXIO;
1558 goto fail;
1559 }
1560
1561 rid = TI_PCI_LOMEM;
1562 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1563 0, ~0, 1, RF_ACTIVE);
1564
1565 if (sc->ti_res == NULL) {
1566 printf ("ti%d: couldn't map memory\n", unit);
1567 error = ENXIO;
1568 goto fail;
1569 }
1570
1571 sc->ti_btag = rman_get_bustag(sc->ti_res);
1572 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1573 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1574
1575 /*
1576 * XXX FIXME: rman_get_virtual() on the alpha is currently
1577 * broken and returns a physical address instead of a kernel
1578 * virtual address. Consequently, we need to do a little
1579 * extra mangling of the vhandle on the alpha. This should
1580 * eventually be fixed! The whole idea here is to get rid
1581 * of platform dependencies.
1582 */
1583#ifdef __alpha__
1584 if (pci_cvt_to_bwx(sc->ti_vhandle))
1585 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1586 else
1587 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1588 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1589#endif
1590
1591 /* Allocate interrupt */
1592 rid = 0;
1593
1594 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1595 RF_SHAREABLE | RF_ACTIVE);
1596
1597 if (sc->ti_irq == NULL) {
1598 printf("ti%d: couldn't map interrupt\n", unit);
1599 error = ENXIO;
1600 goto fail;
1601 }
1602
1603 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1604 ti_intr, sc, &sc->ti_intrhand);
1605
1606 if (error) {
1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1608 bus_release_resource(dev, SYS_RES_MEMORY,
1609 TI_PCI_LOMEM, sc->ti_res);
1610 printf("ti%d: couldn't set up irq\n", unit);
1611 goto fail;
1612 }
1613
1614 sc->ti_unit = unit;
1615
1616 if (ti_chipinit(sc)) {
1617 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1618 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1619 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1620 bus_release_resource(dev, SYS_RES_MEMORY,
1621 TI_PCI_LOMEM, sc->ti_res);
1622 error = ENXIO;
1623 goto fail;
1624 }
1625
1626 /* Zero out the NIC's on-board SRAM. */
1627 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1628
1629 /* Init again -- zeroing memory may have clobbered some registers. */
1630 if (ti_chipinit(sc)) {
1631 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1632 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1634 bus_release_resource(dev, SYS_RES_MEMORY,
1635 TI_PCI_LOMEM, sc->ti_res);
1636 error = ENXIO;
1637 goto fail;
1638 }
1639
1640 /*
1641 * Get station address from the EEPROM. Note: the manual states
1642 * that the MAC address is at offset 0x8c, however the data is
1643 * stored as two longwords (since that's how it's loaded into
1644 * the NIC). This means the MAC address is actually preceeded
1645 * by two zero bytes. We need to skip over those.
1646 */
1647 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1648 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1649 printf("ti%d: failed to read station address\n", unit);
1650 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1651 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1652 bus_release_resource(dev, SYS_RES_MEMORY,
1653 TI_PCI_LOMEM, sc->ti_res);
1654 error = ENXIO;
1655 goto fail;
1656 }
1657
1658 /*
1659 * A Tigon chip was detected. Inform the world.
1660 */
1661 printf("ti%d: Ethernet address: %6D\n", unit,
1662 sc->arpcom.ac_enaddr, ":");
1663
1664 /* Allocate the general information block and ring buffers. */
1665 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1666 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1667
1668 if (sc->ti_rdata == NULL) {
1669 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1670 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1671 bus_release_resource(dev, SYS_RES_MEMORY,
1672 TI_PCI_LOMEM, sc->ti_res);
1673 error = ENXIO;
1674 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1675 goto fail;
1676 }
1677
1678 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1679
1680 /* Try to allocate memory for jumbo buffers. */
1681 if (ti_alloc_jumbo_mem(sc)) {
1682 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1683 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1685 bus_release_resource(dev, SYS_RES_MEMORY,
1686 TI_PCI_LOMEM, sc->ti_res);
1687 free(sc->ti_rdata, M_DEVBUF);
1688 error = ENXIO;
1689 goto fail;
1690 }
1691
1692 /* Set default tuneable values. */
1693 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1694 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1695 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1696 sc->ti_rx_max_coal_bds = 64;
1697 sc->ti_tx_max_coal_bds = 128;
1698 sc->ti_tx_buf_ratio = 21;
1699
1700 /* Set up ifnet structure */
1701 ifp = &sc->arpcom.ac_if;
1702 ifp->if_softc = sc;
1703 ifp->if_unit = sc->ti_unit;
1704 ifp->if_name = "ti";
1705 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1706 ifp->if_ioctl = ti_ioctl;
1707 ifp->if_output = ether_output;
1708 ifp->if_start = ti_start;
1709 ifp->if_watchdog = ti_watchdog;
1710 ifp->if_init = ti_init;
1711 ifp->if_mtu = ETHERMTU;
1712 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1713
1714 /* Set up ifmedia support. */
1715 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL);
1720 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1721 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1722 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1723 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1724
1725 /*
1726 * Call MI attach routines.
1727 */
1728 if_attach(ifp);
1729 ether_ifattach(ifp);
1730
1731#if NBPF > 0
1732 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1733#endif
1734
1735fail:
1736 splx(s);
1737
1738 return(error);
1739}
1740
1741static int ti_detach(dev)
1742 device_t dev;
1743{
1744 struct ti_softc *sc;
1745 struct ifnet *ifp;
1746 int s;
1747
1748 s = splimp();
1749
1750 sc = device_get_softc(dev);
1751 ifp = &sc->arpcom.ac_if;
1752
1753 if_detach(ifp);
1754 ti_stop(sc);
1755
1756 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1757 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1758 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1759
1760 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
1761 free(sc->ti_rdata, M_DEVBUF);
1762 ifmedia_removeall(&sc->ifmedia);
1763
1764 splx(s);
1765
1766 return(0);
1767}
1768
1769/*
1770 * Frame reception handling. This is called if there's a frame
1771 * on the receive return list.
1772 *
1773 * Note: we have to be able to handle three possibilities here:
1774 * 1) the frame is from the mini receive ring (can only happen)
1775 * on Tigon 2 boards)
1776 * 2) the frame is from the jumbo recieve ring
1777 * 3) the frame is from the standard receive ring
1778 */
1779
1780static void ti_rxeof(sc)
1781 struct ti_softc *sc;
1782{
1783 struct ifnet *ifp;
1784 struct ti_cmd_desc cmd;
1785
1786 ifp = &sc->arpcom.ac_if;
1787
1788 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1789 struct ti_rx_desc *cur_rx;
1790 u_int32_t rxidx;
1791 struct ether_header *eh;
1792 struct mbuf *m = NULL;
1793#if NVLAN > 0
1794 u_int16_t vlan_tag = 0;
1795 int have_tag = 0;
1796#endif
1797#ifdef TI_CSUM_OFFLOAD
1798 struct ip *ip;
1799#endif
1800
1801 cur_rx =
1802 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1803 rxidx = cur_rx->ti_idx;
1804 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1805
1806#if NVLAN > 0
1807 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1808 have_tag = 1;
1809 vlan_tag = cur_rx->ti_vlan_tag;
1810 }
1811#endif
1812
1813 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1814 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1815 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1816 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1817 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1818 ifp->if_ierrors++;
1819 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1820 continue;
1821 }
1822 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1823 ifp->if_ierrors++;
1824 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1825 continue;
1826 }
1827 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1828 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1829 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1830 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1831 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1832 ifp->if_ierrors++;
1833 ti_newbuf_mini(sc, sc->ti_mini, m);
1834 continue;
1835 }
1836 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1837 ifp->if_ierrors++;
1838 ti_newbuf_mini(sc, sc->ti_mini, m);
1839 continue;
1840 }
1841 } else {
1842 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1843 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1844 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1845 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1846 ifp->if_ierrors++;
1847 ti_newbuf_std(sc, sc->ti_std, m);
1848 continue;
1849 }
1850 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1851 ifp->if_ierrors++;
1852 ti_newbuf_std(sc, sc->ti_std, m);
1853 continue;
1854 }
1855 }
1856
1857 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1858 ifp->if_ipackets++;
1859 eh = mtod(m, struct ether_header *);
1860 m->m_pkthdr.rcvif = ifp;
1861
1862#if NBPF > 0
1863 /*
1864 * Handle BPF listeners. Let the BPF user see the packet, but
1865 * don't pass it up to the ether_input() layer unless it's
1866 * a broadcast packet, multicast packet, matches our ethernet
1867 * address or the interface is in promiscuous mode.
1868 */
1869 if (ifp->if_bpf) {
1870 bpf_mtap(ifp, m);
1871 if (ifp->if_flags & IFF_PROMISC &&
1872 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1873 ETHER_ADDR_LEN) &&
1874 (eh->ether_dhost[0] & 1) == 0)) {
1875 m_freem(m);
1876 continue;
1877 }
1878 }
1879#endif
1880
1881 /* Remove header from mbuf and pass it on. */
1882 m_adj(m, sizeof(struct ether_header));
1883
1884#ifdef TI_CSUM_OFFLOAD
1885 ip = mtod(m, struct ip *);
1886 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) &&
1887 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF)))
1888 m->m_flags |= M_HWCKSUM;
1889#endif
1890
1891#if NVLAN > 0
1892 /*
1893 * If we received a packet with a vlan tag, pass it
1894 * to vlan_input() instead of ether_input().
1895 */
1896 if (have_tag) {
1897 vlan_input_tag(eh, m, vlan_tag);
1898 have_tag = vlan_tag = 0;
1899 continue;
1900 }
1901#endif
1902 ether_input(ifp, eh, m);
1903 }
1904
1905 /* Only necessary on the Tigon 1. */
1906 if (sc->ti_hwrev == TI_HWREV_TIGON)
1907 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1908 sc->ti_rx_saved_considx);
1909
1910 TI_UPDATE_STDPROD(sc, sc->ti_std);
1911 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1912 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1913
1914 return;
1915}
1916
1917static void ti_txeof(sc)
1918 struct ti_softc *sc;
1919{
1920 struct ti_tx_desc *cur_tx = NULL;
1921 struct ifnet *ifp;
1922
1923 ifp = &sc->arpcom.ac_if;
1924
1925 /*
1926 * Go through our tx ring and free mbufs for those
1927 * frames that have been sent.
1928 */
1929 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1930 u_int32_t idx = 0;
1931
1932 idx = sc->ti_tx_saved_considx;
1933 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1934 if (idx > 383)
1935 CSR_WRITE_4(sc, TI_WINBASE,
1936 TI_TX_RING_BASE + 6144);
1937 else if (idx > 255)
1938 CSR_WRITE_4(sc, TI_WINBASE,
1939 TI_TX_RING_BASE + 4096);
1940 else if (idx > 127)
1941 CSR_WRITE_4(sc, TI_WINBASE,
1942 TI_TX_RING_BASE + 2048);
1943 else
1944 CSR_WRITE_4(sc, TI_WINBASE,
1945 TI_TX_RING_BASE);
1946 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1947 } else
1948 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1949 if (cur_tx->ti_flags & TI_BDFLAG_END)
1950 ifp->if_opackets++;
1951 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1952 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1953 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1954 }
1955 sc->ti_txcnt--;
1956 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1957 ifp->if_timer = 0;
1958 }
1959
1960 if (cur_tx != NULL)
1961 ifp->if_flags &= ~IFF_OACTIVE;
1962
1963 return;
1964}
1965
1966static void ti_intr(xsc)
1967 void *xsc;
1968{
1969 struct ti_softc *sc;
1970 struct ifnet *ifp;
1971
1972 sc = xsc;
1973 ifp = &sc->arpcom.ac_if;
1974
1975#ifdef notdef
1976 /* Avoid this for now -- checking this register is expensive. */
1977 /* Make sure this is really our interrupt. */
1978 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1979 return;
1980#endif
1981
1982 /* Ack interrupt and stop others from occuring. */
1983 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1984
1985 if (ifp->if_flags & IFF_RUNNING) {
1986 /* Check RX return ring producer/consumer */
1987 ti_rxeof(sc);
1988
1989 /* Check TX ring producer/consumer */
1990 ti_txeof(sc);
1991 }
1992
1993 ti_handle_events(sc);
1994
1995 /* Re-enable interrupts. */
1996 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1997
1998 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1999 ti_start(ifp);
2000
2001 return;
2002}
2003
2004static void ti_stats_update(sc)
2005 struct ti_softc *sc;
2006{
2007 struct ifnet *ifp;
2008
2009 ifp = &sc->arpcom.ac_if;
2010
2011 ifp->if_collisions +=
2012 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2013 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2014 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2015 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2016 ifp->if_collisions;
2017
2018 return;
2019}
2020
2021/*
2022 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2023 * pointers to descriptors.
2024 */
2025static int ti_encap(sc, m_head, txidx)
2026 struct ti_softc *sc;
2027 struct mbuf *m_head;
2028 u_int32_t *txidx;
2029{
2030 struct ti_tx_desc *f = NULL;
2031 struct mbuf *m;
2032 u_int32_t frag, cur, cnt = 0;
2033#if NVLAN > 0
2034 struct ifvlan *ifv = NULL;
2035
2036 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2037 m_head->m_pkthdr.rcvif != NULL &&
2038 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN)
2039 ifv = m_head->m_pkthdr.rcvif->if_softc;
2040#endif
2041
2042 m = m_head;
2043 cur = frag = *txidx;
2044
2045 /*
2046 * Start packing the mbufs in this chain into
2047 * the fragment pointers. Stop when we run out
2048 * of fragments or hit the end of the mbuf chain.
2049 */
2050 for (m = m_head; m != NULL; m = m->m_next) {
2051 if (m->m_len != 0) {
2052 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2053 if (frag > 383)
2054 CSR_WRITE_4(sc, TI_WINBASE,
2055 TI_TX_RING_BASE + 6144);
2056 else if (frag > 255)
2057 CSR_WRITE_4(sc, TI_WINBASE,
2058 TI_TX_RING_BASE + 4096);
2059 else if (frag > 127)
2060 CSR_WRITE_4(sc, TI_WINBASE,
2061 TI_TX_RING_BASE + 2048);
2062 else
2063 CSR_WRITE_4(sc, TI_WINBASE,
2064 TI_TX_RING_BASE);
2065 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2066 } else
2067 f = &sc->ti_rdata->ti_tx_ring[frag];
2068 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2069 break;
2070 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2071 f->ti_len = m->m_len;
2072 f->ti_flags = 0;
2073#if NVLAN > 0
2074 if (ifv != NULL) {
2075 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2076 f->ti_vlan_tag = ifv->ifv_tag;
2077 } else {
2078 f->ti_vlan_tag = 0;
2079 }
2080#endif
2081 /*
2082 * Sanity check: avoid coming within 16 descriptors
2083 * of the end of the ring.
2084 */
2085 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2086 return(ENOBUFS);
2087 cur = frag;
2088 TI_INC(frag, TI_TX_RING_CNT);
2089 cnt++;
2090 }
2091 }
2092
2093 if (m != NULL)
2094 return(ENOBUFS);
2095
2096 if (frag == sc->ti_tx_saved_considx)
2097 return(ENOBUFS);
2098
2099 if (sc->ti_hwrev == TI_HWREV_TIGON)
2100 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2101 TI_BDFLAG_END;
2102 else
2103 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2104 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2105 sc->ti_txcnt += cnt;
2106
2107 *txidx = frag;
2108
2109 return(0);
2110}
2111
2112/*
2113 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2114 * to the mbuf data regions directly in the transmit descriptors.
2115 */
2116static void ti_start(ifp)
2117 struct ifnet *ifp;
2118{
2119 struct ti_softc *sc;
2120 struct mbuf *m_head = NULL;
2121 u_int32_t prodidx = 0;
2122
2123 sc = ifp->if_softc;
2124
2125 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2126
2127 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2128 IF_DEQUEUE(&ifp->if_snd, m_head);
2129 if (m_head == NULL)
2130 break;
2131
2132 /*
2133 * Pack the data into the transmit ring. If we
2134 * don't have room, set the OACTIVE flag and wait
2135 * for the NIC to drain the ring.
2136 */
2137 if (ti_encap(sc, m_head, &prodidx)) {
2138 IF_PREPEND(&ifp->if_snd, m_head);
2139 ifp->if_flags |= IFF_OACTIVE;
2140 break;
2141 }
2142
2143 /*
2144 * If there's a BPF listener, bounce a copy of this frame
2145 * to him.
2146 */
2147#if NBPF > 0
2148 if (ifp->if_bpf)
2149 bpf_mtap(ifp, m_head);
2150#endif
2151 }
2152
2153 /* Transmit */
2154 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2155
2156 /*
2157 * Set a timeout in case the chip goes out to lunch.
2158 */
2159 ifp->if_timer = 5;
2160
2161 return;
2162}
2163
2164static void ti_init(xsc)
2165 void *xsc;
2166{
2167 struct ti_softc *sc = xsc;
2168 int s;
2169
2170 s = splimp();
2171
2172 /* Cancel pending I/O and flush buffers. */
2173 ti_stop(sc);
2174
2175 /* Init the gen info block, ring control blocks and firmware. */
2176 if (ti_gibinit(sc)) {
2177 printf("ti%d: initialization failure\n", sc->ti_unit);
2178 splx(s);
2179 return;
2180 }
2181
2182 splx(s);
2183
2184 return;
2185}
2186
2187static void ti_init2(sc)
2188 struct ti_softc *sc;
2189{
2190 struct ti_cmd_desc cmd;
2191 struct ifnet *ifp;
2192 u_int16_t *m;
2193 struct ifmedia *ifm;
2194 int tmp;
2195
2196 ifp = &sc->arpcom.ac_if;
2197
2198 /* Specify MTU and interface index. */
2199 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2200 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2201 ETHER_HDR_LEN + ETHER_CRC_LEN);
2202 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2203
2204 /* Load our MAC address. */
2205 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2206 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2207 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2208 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2209
2210 /* Enable or disable promiscuous mode as needed. */
2211 if (ifp->if_flags & IFF_PROMISC) {
2212 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2213 } else {
2214 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2215 }
2216
2217 /* Program multicast filter. */
2218 ti_setmulti(sc);
2219
2220 /*
2221 * If this is a Tigon 1, we should tell the
2222 * firmware to use software packet filtering.
2223 */
2224 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2225 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2226 }
2227
2228 /* Init RX ring. */
2229 ti_init_rx_ring_std(sc);
2230
2231 /* Init jumbo RX ring. */
2232 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2233 ti_init_rx_ring_jumbo(sc);
2234
2235 /*
2236 * If this is a Tigon 2, we can also configure the
2237 * mini ring.
2238 */
2239 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2240 ti_init_rx_ring_mini(sc);
2241
2242 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2243 sc->ti_rx_saved_considx = 0;
2244
2245 /* Init TX ring. */
2246 ti_init_tx_ring(sc);
2247
2248 /* Tell firmware we're alive. */
2249 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2250
2251 /* Enable host interrupts. */
2252 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2253
2254 ifp->if_flags |= IFF_RUNNING;
2255 ifp->if_flags &= ~IFF_OACTIVE;
2256
2257 /*
2258 * Make sure to set media properly. We have to do this
2259 * here since we have to issue commands in order to set
2260 * the link negotiation and we can't issue commands until
2261 * the firmware is running.
2262 */
2263 ifm = &sc->ifmedia;
2264 tmp = ifm->ifm_media;
2265 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2266 ti_ifmedia_upd(ifp);
2267 ifm->ifm_media = tmp;
2268
2269 return;
2270}
2271
2272/*
2273 * Set media options.
2274 */
2275static int ti_ifmedia_upd(ifp)
2276 struct ifnet *ifp;
2277{
2278 struct ti_softc *sc;
2279 struct ifmedia *ifm;
2280 struct ti_cmd_desc cmd;
2281
2282 sc = ifp->if_softc;
2283 ifm = &sc->ifmedia;
2284
2285 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2286 return(EINVAL);
2287
2288 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2289 case IFM_AUTO:
2290 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2291 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2292 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2293 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2294 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2295 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2296 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2297 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2298 break;
2299 case IFM_1000_SX:
2300 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2301 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2302 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2303 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2304 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2305 break;
2306 case IFM_100_FX:
2307 case IFM_10_FL:
2308 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2309 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2310 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) {
2311 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2312 } else {
2313 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2314 }
2315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2316 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2317 } else {
2318 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2319 }
2320 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2321 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2322 break;
2323 }
2324
2325 return(0);
2326}
2327
2328/*
2329 * Report current media status.
2330 */
2331static void ti_ifmedia_sts(ifp, ifmr)
2332 struct ifnet *ifp;
2333 struct ifmediareq *ifmr;
2334{
2335 struct ti_softc *sc;
2336
2337 sc = ifp->if_softc;
2338
2339 ifmr->ifm_status = IFM_AVALID;
2340 ifmr->ifm_active = IFM_ETHER;
2341
2342 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2343 return;
2344
2345 ifmr->ifm_status |= IFM_ACTIVE;
2346
2347 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
2348 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX;
2349 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2350 u_int32_t media;
2351 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2352 if (media & TI_LNK_100MB)
2353 ifmr->ifm_active |= IFM_100_FX;
2354 if (media & TI_LNK_10MB)
2355 ifmr->ifm_active |= IFM_10_FL;
2356 if (media & TI_LNK_FULL_DUPLEX)
2357 ifmr->ifm_active |= IFM_FDX;
2358 if (media & TI_LNK_HALF_DUPLEX)
2359 ifmr->ifm_active |= IFM_HDX;
2360 }
2361
2362 return;
2363}
2364
2365static int ti_ioctl(ifp, command, data)
2366 struct ifnet *ifp;
2367 u_long command;
2368 caddr_t data;
2369{
2370 struct ti_softc *sc = ifp->if_softc;
2371 struct ifreq *ifr = (struct ifreq *) data;
2372 int s, error = 0;
2373 struct ti_cmd_desc cmd;
2374
2375 s = splimp();
2376
2377 switch(command) {
2378 case SIOCSIFADDR:
2379 case SIOCGIFADDR:
2380 error = ether_ioctl(ifp, command, data);
2381 break;
2382 case SIOCSIFMTU:
2383 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2384 error = EINVAL;
2385 else {
2386 ifp->if_mtu = ifr->ifr_mtu;
2387 ti_init(sc);
2388 }
2389 break;
2390 case SIOCSIFFLAGS:
2391 if (ifp->if_flags & IFF_UP) {
2392 /*
2393 * If only the state of the PROMISC flag changed,
2394 * then just use the 'set promisc mode' command
2395 * instead of reinitializing the entire NIC. Doing
2396 * a full re-init means reloading the firmware and
2397 * waiting for it to start up, which may take a
2398 * second or two.
2399 */
2400 if (ifp->if_flags & IFF_RUNNING &&
2401 ifp->if_flags & IFF_PROMISC &&
2402 !(sc->ti_if_flags & IFF_PROMISC)) {
2403 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2404 TI_CMD_CODE_PROMISC_ENB, 0);
2405 } else if (ifp->if_flags & IFF_RUNNING &&
2406 !(ifp->if_flags & IFF_PROMISC) &&
2407 sc->ti_if_flags & IFF_PROMISC) {
2408 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2409 TI_CMD_CODE_PROMISC_DIS, 0);
2410 } else
2411 ti_init(sc);
2412 } else {
2413 if (ifp->if_flags & IFF_RUNNING) {
2414 ti_stop(sc);
2415 }
2416 }
2417 sc->ti_if_flags = ifp->if_flags;
2418 error = 0;
2419 break;
2420 case SIOCADDMULTI:
2421 case SIOCDELMULTI:
2422 if (ifp->if_flags & IFF_RUNNING) {
2423 ti_setmulti(sc);
2424 error = 0;
2425 }
2426 break;
2427 case SIOCSIFMEDIA:
2428 case SIOCGIFMEDIA:
2429 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2430 break;
2431 default:
2432 error = EINVAL;
2433 break;
2434 }
2435
2436 (void)splx(s);
2437
2438 return(error);
2439}
2440
2441static void ti_watchdog(ifp)
2442 struct ifnet *ifp;
2443{
2444 struct ti_softc *sc;
2445
2446 sc = ifp->if_softc;
2447
2448 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2449 ti_stop(sc);
2450 ti_init(sc);
2451
2452 ifp->if_oerrors++;
2453
2454 return;
2455}
2456
2457/*
2458 * Stop the adapter and free any mbufs allocated to the
2459 * RX and TX lists.
2460 */
2461static void ti_stop(sc)
2462 struct ti_softc *sc;
2463{
2464 struct ifnet *ifp;
2465 struct ti_cmd_desc cmd;
2466
2467 ifp = &sc->arpcom.ac_if;
2468
2469 /* Disable host interrupts. */
2470 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2471 /*
2472 * Tell firmware we're shutting down.
2473 */
2474 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2475
2476 /* Halt and reinitialize. */
2477 ti_chipinit(sc);
2478 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2479 ti_chipinit(sc);
2480
2481 /* Free the RX lists. */
2482 ti_free_rx_ring_std(sc);
2483
2484 /* Free jumbo RX list. */
2485 ti_free_rx_ring_jumbo(sc);
2486
2487 /* Free mini RX list. */
2488 ti_free_rx_ring_mini(sc);
2489
2490 /* Free TX buffers. */
2491 ti_free_tx_ring(sc);
2492
2493 sc->ti_ev_prodidx.ti_idx = 0;
2494 sc->ti_return_prodidx.ti_idx = 0;
2495 sc->ti_tx_considx.ti_idx = 0;
2496 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2497
2498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2499
2500 return;
2501}
2502
2503/*
2504 * Stop all chip I/O so that the kernel's probe routines don't
2505 * get confused by errant DMAs when rebooting.
2506 */
2507static void ti_shutdown(dev)
2508 device_t dev;
2509{
2510 struct ti_softc *sc;
2511
2512 sc = device_get_softc(dev);
2513
2514 ti_chipinit(sc);
2515
2516 return;
2517}
| 1432 if (sc->ti_hwrev == TI_HWREV_TIGON)
1433 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1434 else
1435 rcb->ti_flags = 0;
1436#ifdef TI_CSUM_OFFLOAD
1437 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM;
1438#endif
1439#if NVLAN > 0
1440 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1441#endif
1442
1443 /*
1444 * Set up the receive return ring.
1445 */
1446 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1447 TI_HOSTADDR(rcb->ti_hostaddr) =
1448 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1449 rcb->ti_flags = 0;
1450 rcb->ti_max_len = TI_RETURN_RING_CNT;
1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1452 vtophys(&sc->ti_return_prodidx);
1453
1454 /*
1455 * Set up the tx ring. Note: for the Tigon 2, we have the option
1456 * of putting the transmit ring in the host's address space and
1457 * letting the chip DMA it instead of leaving the ring in the NIC's
1458 * memory and accessing it through the shared memory region. We
1459 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1460 * so we have to revert to the shared memory scheme if we detect
1461 * a Tigon 1 chip.
1462 */
1463 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1464 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1465 sc->ti_rdata->ti_tx_ring_nic =
1466 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1467 }
1468 bzero((char *)sc->ti_rdata->ti_tx_ring,
1469 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1470 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1471 if (sc->ti_hwrev == TI_HWREV_TIGON)
1472 rcb->ti_flags = 0;
1473 else
1474 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1475#if NVLAN > 0
1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1477#endif
1478 rcb->ti_max_len = TI_TX_RING_CNT;
1479 if (sc->ti_hwrev == TI_HWREV_TIGON)
1480 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1481 else
1482 TI_HOSTADDR(rcb->ti_hostaddr) =
1483 vtophys(&sc->ti_rdata->ti_tx_ring);
1484 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1485 vtophys(&sc->ti_tx_considx);
1486
1487 /* Set up tuneables */
1488 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1490 (sc->ti_rx_coal_ticks / 10));
1491 else
1492 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1493 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1494 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1495 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1496 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1497 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1498
1499 /* Turn interrupts on. */
1500 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1501 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1502
1503 /* Start CPU. */
1504 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1505
1506 return(0);
1507}
1508
1509/*
1510 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1511 * against our list and return its name if we find a match.
1512 */
1513static int ti_probe(dev)
1514 device_t dev;
1515{
1516 struct ti_type *t;
1517
1518 t = ti_devs;
1519
1520 while(t->ti_name != NULL) {
1521 if ((pci_get_vendor(dev) == t->ti_vid) &&
1522 (pci_get_device(dev) == t->ti_did)) {
1523 device_set_desc(dev, t->ti_name);
1524 return(0);
1525 }
1526 t++;
1527 }
1528
1529 return(ENXIO);
1530}
1531
1532static int ti_attach(dev)
1533 device_t dev;
1534{
1535 int s;
1536 u_int32_t command;
1537 struct ifnet *ifp;
1538 struct ti_softc *sc;
1539 int unit, error = 0, rid;
1540
1541 s = splimp();
1542
1543 sc = device_get_softc(dev);
1544 unit = device_get_unit(dev);
1545 bzero(sc, sizeof(struct ti_softc));
1546
1547 /*
1548 * Map control/status registers.
1549 */
1550 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1551 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1552 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
1553 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1554
1555 if (!(command & PCIM_CMD_MEMEN)) {
1556 printf("ti%d: failed to enable memory mapping!\n", unit);
1557 error = ENXIO;
1558 goto fail;
1559 }
1560
1561 rid = TI_PCI_LOMEM;
1562 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1563 0, ~0, 1, RF_ACTIVE);
1564
1565 if (sc->ti_res == NULL) {
1566 printf ("ti%d: couldn't map memory\n", unit);
1567 error = ENXIO;
1568 goto fail;
1569 }
1570
1571 sc->ti_btag = rman_get_bustag(sc->ti_res);
1572 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1573 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1574
1575 /*
1576 * XXX FIXME: rman_get_virtual() on the alpha is currently
1577 * broken and returns a physical address instead of a kernel
1578 * virtual address. Consequently, we need to do a little
1579 * extra mangling of the vhandle on the alpha. This should
1580 * eventually be fixed! The whole idea here is to get rid
1581 * of platform dependencies.
1582 */
1583#ifdef __alpha__
1584 if (pci_cvt_to_bwx(sc->ti_vhandle))
1585 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1586 else
1587 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1588 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1589#endif
1590
1591 /* Allocate interrupt */
1592 rid = 0;
1593
1594 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1595 RF_SHAREABLE | RF_ACTIVE);
1596
1597 if (sc->ti_irq == NULL) {
1598 printf("ti%d: couldn't map interrupt\n", unit);
1599 error = ENXIO;
1600 goto fail;
1601 }
1602
1603 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1604 ti_intr, sc, &sc->ti_intrhand);
1605
1606 if (error) {
1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1608 bus_release_resource(dev, SYS_RES_MEMORY,
1609 TI_PCI_LOMEM, sc->ti_res);
1610 printf("ti%d: couldn't set up irq\n", unit);
1611 goto fail;
1612 }
1613
1614 sc->ti_unit = unit;
1615
1616 if (ti_chipinit(sc)) {
1617 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1618 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1619 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1620 bus_release_resource(dev, SYS_RES_MEMORY,
1621 TI_PCI_LOMEM, sc->ti_res);
1622 error = ENXIO;
1623 goto fail;
1624 }
1625
1626 /* Zero out the NIC's on-board SRAM. */
1627 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1628
1629 /* Init again -- zeroing memory may have clobbered some registers. */
1630 if (ti_chipinit(sc)) {
1631 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1632 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1634 bus_release_resource(dev, SYS_RES_MEMORY,
1635 TI_PCI_LOMEM, sc->ti_res);
1636 error = ENXIO;
1637 goto fail;
1638 }
1639
1640 /*
1641 * Get station address from the EEPROM. Note: the manual states
1642 * that the MAC address is at offset 0x8c, however the data is
1643 * stored as two longwords (since that's how it's loaded into
1644 * the NIC). This means the MAC address is actually preceeded
1645 * by two zero bytes. We need to skip over those.
1646 */
1647 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1648 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1649 printf("ti%d: failed to read station address\n", unit);
1650 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1651 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1652 bus_release_resource(dev, SYS_RES_MEMORY,
1653 TI_PCI_LOMEM, sc->ti_res);
1654 error = ENXIO;
1655 goto fail;
1656 }
1657
1658 /*
1659 * A Tigon chip was detected. Inform the world.
1660 */
1661 printf("ti%d: Ethernet address: %6D\n", unit,
1662 sc->arpcom.ac_enaddr, ":");
1663
1664 /* Allocate the general information block and ring buffers. */
1665 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1666 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1667
1668 if (sc->ti_rdata == NULL) {
1669 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1670 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1671 bus_release_resource(dev, SYS_RES_MEMORY,
1672 TI_PCI_LOMEM, sc->ti_res);
1673 error = ENXIO;
1674 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1675 goto fail;
1676 }
1677
1678 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1679
1680 /* Try to allocate memory for jumbo buffers. */
1681 if (ti_alloc_jumbo_mem(sc)) {
1682 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1683 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1685 bus_release_resource(dev, SYS_RES_MEMORY,
1686 TI_PCI_LOMEM, sc->ti_res);
1687 free(sc->ti_rdata, M_DEVBUF);
1688 error = ENXIO;
1689 goto fail;
1690 }
1691
1692 /* Set default tuneable values. */
1693 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1694 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1695 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1696 sc->ti_rx_max_coal_bds = 64;
1697 sc->ti_tx_max_coal_bds = 128;
1698 sc->ti_tx_buf_ratio = 21;
1699
1700 /* Set up ifnet structure */
1701 ifp = &sc->arpcom.ac_if;
1702 ifp->if_softc = sc;
1703 ifp->if_unit = sc->ti_unit;
1704 ifp->if_name = "ti";
1705 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1706 ifp->if_ioctl = ti_ioctl;
1707 ifp->if_output = ether_output;
1708 ifp->if_start = ti_start;
1709 ifp->if_watchdog = ti_watchdog;
1710 ifp->if_init = ti_init;
1711 ifp->if_mtu = ETHERMTU;
1712 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1713
1714 /* Set up ifmedia support. */
1715 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL);
1720 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1721 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1722 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1723 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1724
1725 /*
1726 * Call MI attach routines.
1727 */
1728 if_attach(ifp);
1729 ether_ifattach(ifp);
1730
1731#if NBPF > 0
1732 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1733#endif
1734
1735fail:
1736 splx(s);
1737
1738 return(error);
1739}
1740
1741static int ti_detach(dev)
1742 device_t dev;
1743{
1744 struct ti_softc *sc;
1745 struct ifnet *ifp;
1746 int s;
1747
1748 s = splimp();
1749
1750 sc = device_get_softc(dev);
1751 ifp = &sc->arpcom.ac_if;
1752
1753 if_detach(ifp);
1754 ti_stop(sc);
1755
1756 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1757 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1758 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1759
1760 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF);
1761 free(sc->ti_rdata, M_DEVBUF);
1762 ifmedia_removeall(&sc->ifmedia);
1763
1764 splx(s);
1765
1766 return(0);
1767}
1768
1769/*
1770 * Frame reception handling. This is called if there's a frame
1771 * on the receive return list.
1772 *
1773 * Note: we have to be able to handle three possibilities here:
1774 * 1) the frame is from the mini receive ring (can only happen)
1775 * on Tigon 2 boards)
1776 * 2) the frame is from the jumbo recieve ring
1777 * 3) the frame is from the standard receive ring
1778 */
1779
1780static void ti_rxeof(sc)
1781 struct ti_softc *sc;
1782{
1783 struct ifnet *ifp;
1784 struct ti_cmd_desc cmd;
1785
1786 ifp = &sc->arpcom.ac_if;
1787
1788 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1789 struct ti_rx_desc *cur_rx;
1790 u_int32_t rxidx;
1791 struct ether_header *eh;
1792 struct mbuf *m = NULL;
1793#if NVLAN > 0
1794 u_int16_t vlan_tag = 0;
1795 int have_tag = 0;
1796#endif
1797#ifdef TI_CSUM_OFFLOAD
1798 struct ip *ip;
1799#endif
1800
1801 cur_rx =
1802 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1803 rxidx = cur_rx->ti_idx;
1804 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1805
1806#if NVLAN > 0
1807 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1808 have_tag = 1;
1809 vlan_tag = cur_rx->ti_vlan_tag;
1810 }
1811#endif
1812
1813 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1814 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1815 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1816 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1817 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1818 ifp->if_ierrors++;
1819 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1820 continue;
1821 }
1822 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1823 ifp->if_ierrors++;
1824 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1825 continue;
1826 }
1827 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1828 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1829 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1830 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1831 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1832 ifp->if_ierrors++;
1833 ti_newbuf_mini(sc, sc->ti_mini, m);
1834 continue;
1835 }
1836 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1837 ifp->if_ierrors++;
1838 ti_newbuf_mini(sc, sc->ti_mini, m);
1839 continue;
1840 }
1841 } else {
1842 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1843 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1844 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1845 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1846 ifp->if_ierrors++;
1847 ti_newbuf_std(sc, sc->ti_std, m);
1848 continue;
1849 }
1850 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1851 ifp->if_ierrors++;
1852 ti_newbuf_std(sc, sc->ti_std, m);
1853 continue;
1854 }
1855 }
1856
1857 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1858 ifp->if_ipackets++;
1859 eh = mtod(m, struct ether_header *);
1860 m->m_pkthdr.rcvif = ifp;
1861
1862#if NBPF > 0
1863 /*
1864 * Handle BPF listeners. Let the BPF user see the packet, but
1865 * don't pass it up to the ether_input() layer unless it's
1866 * a broadcast packet, multicast packet, matches our ethernet
1867 * address or the interface is in promiscuous mode.
1868 */
1869 if (ifp->if_bpf) {
1870 bpf_mtap(ifp, m);
1871 if (ifp->if_flags & IFF_PROMISC &&
1872 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1873 ETHER_ADDR_LEN) &&
1874 (eh->ether_dhost[0] & 1) == 0)) {
1875 m_freem(m);
1876 continue;
1877 }
1878 }
1879#endif
1880
1881 /* Remove header from mbuf and pass it on. */
1882 m_adj(m, sizeof(struct ether_header));
1883
1884#ifdef TI_CSUM_OFFLOAD
1885 ip = mtod(m, struct ip *);
1886 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) &&
1887 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF)))
1888 m->m_flags |= M_HWCKSUM;
1889#endif
1890
1891#if NVLAN > 0
1892 /*
1893 * If we received a packet with a vlan tag, pass it
1894 * to vlan_input() instead of ether_input().
1895 */
1896 if (have_tag) {
1897 vlan_input_tag(eh, m, vlan_tag);
1898 have_tag = vlan_tag = 0;
1899 continue;
1900 }
1901#endif
1902 ether_input(ifp, eh, m);
1903 }
1904
1905 /* Only necessary on the Tigon 1. */
1906 if (sc->ti_hwrev == TI_HWREV_TIGON)
1907 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1908 sc->ti_rx_saved_considx);
1909
1910 TI_UPDATE_STDPROD(sc, sc->ti_std);
1911 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1912 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1913
1914 return;
1915}
1916
1917static void ti_txeof(sc)
1918 struct ti_softc *sc;
1919{
1920 struct ti_tx_desc *cur_tx = NULL;
1921 struct ifnet *ifp;
1922
1923 ifp = &sc->arpcom.ac_if;
1924
1925 /*
1926 * Go through our tx ring and free mbufs for those
1927 * frames that have been sent.
1928 */
1929 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1930 u_int32_t idx = 0;
1931
1932 idx = sc->ti_tx_saved_considx;
1933 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1934 if (idx > 383)
1935 CSR_WRITE_4(sc, TI_WINBASE,
1936 TI_TX_RING_BASE + 6144);
1937 else if (idx > 255)
1938 CSR_WRITE_4(sc, TI_WINBASE,
1939 TI_TX_RING_BASE + 4096);
1940 else if (idx > 127)
1941 CSR_WRITE_4(sc, TI_WINBASE,
1942 TI_TX_RING_BASE + 2048);
1943 else
1944 CSR_WRITE_4(sc, TI_WINBASE,
1945 TI_TX_RING_BASE);
1946 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1947 } else
1948 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1949 if (cur_tx->ti_flags & TI_BDFLAG_END)
1950 ifp->if_opackets++;
1951 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1952 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1953 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1954 }
1955 sc->ti_txcnt--;
1956 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1957 ifp->if_timer = 0;
1958 }
1959
1960 if (cur_tx != NULL)
1961 ifp->if_flags &= ~IFF_OACTIVE;
1962
1963 return;
1964}
1965
1966static void ti_intr(xsc)
1967 void *xsc;
1968{
1969 struct ti_softc *sc;
1970 struct ifnet *ifp;
1971
1972 sc = xsc;
1973 ifp = &sc->arpcom.ac_if;
1974
1975#ifdef notdef
1976 /* Avoid this for now -- checking this register is expensive. */
1977 /* Make sure this is really our interrupt. */
1978 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1979 return;
1980#endif
1981
1982 /* Ack interrupt and stop others from occuring. */
1983 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1984
1985 if (ifp->if_flags & IFF_RUNNING) {
1986 /* Check RX return ring producer/consumer */
1987 ti_rxeof(sc);
1988
1989 /* Check TX ring producer/consumer */
1990 ti_txeof(sc);
1991 }
1992
1993 ti_handle_events(sc);
1994
1995 /* Re-enable interrupts. */
1996 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1997
1998 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1999 ti_start(ifp);
2000
2001 return;
2002}
2003
2004static void ti_stats_update(sc)
2005 struct ti_softc *sc;
2006{
2007 struct ifnet *ifp;
2008
2009 ifp = &sc->arpcom.ac_if;
2010
2011 ifp->if_collisions +=
2012 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2013 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2014 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2015 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2016 ifp->if_collisions;
2017
2018 return;
2019}
2020
2021/*
2022 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2023 * pointers to descriptors.
2024 */
2025static int ti_encap(sc, m_head, txidx)
2026 struct ti_softc *sc;
2027 struct mbuf *m_head;
2028 u_int32_t *txidx;
2029{
2030 struct ti_tx_desc *f = NULL;
2031 struct mbuf *m;
2032 u_int32_t frag, cur, cnt = 0;
2033#if NVLAN > 0
2034 struct ifvlan *ifv = NULL;
2035
2036 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2037 m_head->m_pkthdr.rcvif != NULL &&
2038 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN)
2039 ifv = m_head->m_pkthdr.rcvif->if_softc;
2040#endif
2041
2042 m = m_head;
2043 cur = frag = *txidx;
2044
2045 /*
2046 * Start packing the mbufs in this chain into
2047 * the fragment pointers. Stop when we run out
2048 * of fragments or hit the end of the mbuf chain.
2049 */
2050 for (m = m_head; m != NULL; m = m->m_next) {
2051 if (m->m_len != 0) {
2052 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2053 if (frag > 383)
2054 CSR_WRITE_4(sc, TI_WINBASE,
2055 TI_TX_RING_BASE + 6144);
2056 else if (frag > 255)
2057 CSR_WRITE_4(sc, TI_WINBASE,
2058 TI_TX_RING_BASE + 4096);
2059 else if (frag > 127)
2060 CSR_WRITE_4(sc, TI_WINBASE,
2061 TI_TX_RING_BASE + 2048);
2062 else
2063 CSR_WRITE_4(sc, TI_WINBASE,
2064 TI_TX_RING_BASE);
2065 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2066 } else
2067 f = &sc->ti_rdata->ti_tx_ring[frag];
2068 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2069 break;
2070 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2071 f->ti_len = m->m_len;
2072 f->ti_flags = 0;
2073#if NVLAN > 0
2074 if (ifv != NULL) {
2075 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2076 f->ti_vlan_tag = ifv->ifv_tag;
2077 } else {
2078 f->ti_vlan_tag = 0;
2079 }
2080#endif
2081 /*
2082 * Sanity check: avoid coming within 16 descriptors
2083 * of the end of the ring.
2084 */
2085 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2086 return(ENOBUFS);
2087 cur = frag;
2088 TI_INC(frag, TI_TX_RING_CNT);
2089 cnt++;
2090 }
2091 }
2092
2093 if (m != NULL)
2094 return(ENOBUFS);
2095
2096 if (frag == sc->ti_tx_saved_considx)
2097 return(ENOBUFS);
2098
2099 if (sc->ti_hwrev == TI_HWREV_TIGON)
2100 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2101 TI_BDFLAG_END;
2102 else
2103 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2104 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2105 sc->ti_txcnt += cnt;
2106
2107 *txidx = frag;
2108
2109 return(0);
2110}
2111
2112/*
2113 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2114 * to the mbuf data regions directly in the transmit descriptors.
2115 */
2116static void ti_start(ifp)
2117 struct ifnet *ifp;
2118{
2119 struct ti_softc *sc;
2120 struct mbuf *m_head = NULL;
2121 u_int32_t prodidx = 0;
2122
2123 sc = ifp->if_softc;
2124
2125 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2126
2127 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2128 IF_DEQUEUE(&ifp->if_snd, m_head);
2129 if (m_head == NULL)
2130 break;
2131
2132 /*
2133 * Pack the data into the transmit ring. If we
2134 * don't have room, set the OACTIVE flag and wait
2135 * for the NIC to drain the ring.
2136 */
2137 if (ti_encap(sc, m_head, &prodidx)) {
2138 IF_PREPEND(&ifp->if_snd, m_head);
2139 ifp->if_flags |= IFF_OACTIVE;
2140 break;
2141 }
2142
2143 /*
2144 * If there's a BPF listener, bounce a copy of this frame
2145 * to him.
2146 */
2147#if NBPF > 0
2148 if (ifp->if_bpf)
2149 bpf_mtap(ifp, m_head);
2150#endif
2151 }
2152
2153 /* Transmit */
2154 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2155
2156 /*
2157 * Set a timeout in case the chip goes out to lunch.
2158 */
2159 ifp->if_timer = 5;
2160
2161 return;
2162}
2163
2164static void ti_init(xsc)
2165 void *xsc;
2166{
2167 struct ti_softc *sc = xsc;
2168 int s;
2169
2170 s = splimp();
2171
2172 /* Cancel pending I/O and flush buffers. */
2173 ti_stop(sc);
2174
2175 /* Init the gen info block, ring control blocks and firmware. */
2176 if (ti_gibinit(sc)) {
2177 printf("ti%d: initialization failure\n", sc->ti_unit);
2178 splx(s);
2179 return;
2180 }
2181
2182 splx(s);
2183
2184 return;
2185}
2186
2187static void ti_init2(sc)
2188 struct ti_softc *sc;
2189{
2190 struct ti_cmd_desc cmd;
2191 struct ifnet *ifp;
2192 u_int16_t *m;
2193 struct ifmedia *ifm;
2194 int tmp;
2195
2196 ifp = &sc->arpcom.ac_if;
2197
2198 /* Specify MTU and interface index. */
2199 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2200 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2201 ETHER_HDR_LEN + ETHER_CRC_LEN);
2202 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2203
2204 /* Load our MAC address. */
2205 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2206 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2207 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2208 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2209
2210 /* Enable or disable promiscuous mode as needed. */
2211 if (ifp->if_flags & IFF_PROMISC) {
2212 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2213 } else {
2214 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2215 }
2216
2217 /* Program multicast filter. */
2218 ti_setmulti(sc);
2219
2220 /*
2221 * If this is a Tigon 1, we should tell the
2222 * firmware to use software packet filtering.
2223 */
2224 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2225 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2226 }
2227
2228 /* Init RX ring. */
2229 ti_init_rx_ring_std(sc);
2230
2231 /* Init jumbo RX ring. */
2232 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2233 ti_init_rx_ring_jumbo(sc);
2234
2235 /*
2236 * If this is a Tigon 2, we can also configure the
2237 * mini ring.
2238 */
2239 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2240 ti_init_rx_ring_mini(sc);
2241
2242 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2243 sc->ti_rx_saved_considx = 0;
2244
2245 /* Init TX ring. */
2246 ti_init_tx_ring(sc);
2247
2248 /* Tell firmware we're alive. */
2249 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2250
2251 /* Enable host interrupts. */
2252 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2253
2254 ifp->if_flags |= IFF_RUNNING;
2255 ifp->if_flags &= ~IFF_OACTIVE;
2256
2257 /*
2258 * Make sure to set media properly. We have to do this
2259 * here since we have to issue commands in order to set
2260 * the link negotiation and we can't issue commands until
2261 * the firmware is running.
2262 */
2263 ifm = &sc->ifmedia;
2264 tmp = ifm->ifm_media;
2265 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2266 ti_ifmedia_upd(ifp);
2267 ifm->ifm_media = tmp;
2268
2269 return;
2270}
2271
2272/*
2273 * Set media options.
2274 */
2275static int ti_ifmedia_upd(ifp)
2276 struct ifnet *ifp;
2277{
2278 struct ti_softc *sc;
2279 struct ifmedia *ifm;
2280 struct ti_cmd_desc cmd;
2281
2282 sc = ifp->if_softc;
2283 ifm = &sc->ifmedia;
2284
2285 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2286 return(EINVAL);
2287
2288 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2289 case IFM_AUTO:
2290 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2291 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2292 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2293 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2294 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2295 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2296 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2297 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2298 break;
2299 case IFM_1000_SX:
2300 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2301 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2302 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2303 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2304 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2305 break;
2306 case IFM_100_FX:
2307 case IFM_10_FL:
2308 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2309 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2310 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) {
2311 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2312 } else {
2313 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2314 }
2315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2316 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2317 } else {
2318 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2319 }
2320 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2321 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2322 break;
2323 }
2324
2325 return(0);
2326}
2327
2328/*
2329 * Report current media status.
2330 */
2331static void ti_ifmedia_sts(ifp, ifmr)
2332 struct ifnet *ifp;
2333 struct ifmediareq *ifmr;
2334{
2335 struct ti_softc *sc;
2336
2337 sc = ifp->if_softc;
2338
2339 ifmr->ifm_status = IFM_AVALID;
2340 ifmr->ifm_active = IFM_ETHER;
2341
2342 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2343 return;
2344
2345 ifmr->ifm_status |= IFM_ACTIVE;
2346
2347 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
2348 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX;
2349 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2350 u_int32_t media;
2351 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2352 if (media & TI_LNK_100MB)
2353 ifmr->ifm_active |= IFM_100_FX;
2354 if (media & TI_LNK_10MB)
2355 ifmr->ifm_active |= IFM_10_FL;
2356 if (media & TI_LNK_FULL_DUPLEX)
2357 ifmr->ifm_active |= IFM_FDX;
2358 if (media & TI_LNK_HALF_DUPLEX)
2359 ifmr->ifm_active |= IFM_HDX;
2360 }
2361
2362 return;
2363}
2364
2365static int ti_ioctl(ifp, command, data)
2366 struct ifnet *ifp;
2367 u_long command;
2368 caddr_t data;
2369{
2370 struct ti_softc *sc = ifp->if_softc;
2371 struct ifreq *ifr = (struct ifreq *) data;
2372 int s, error = 0;
2373 struct ti_cmd_desc cmd;
2374
2375 s = splimp();
2376
2377 switch(command) {
2378 case SIOCSIFADDR:
2379 case SIOCGIFADDR:
2380 error = ether_ioctl(ifp, command, data);
2381 break;
2382 case SIOCSIFMTU:
2383 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2384 error = EINVAL;
2385 else {
2386 ifp->if_mtu = ifr->ifr_mtu;
2387 ti_init(sc);
2388 }
2389 break;
2390 case SIOCSIFFLAGS:
2391 if (ifp->if_flags & IFF_UP) {
2392 /*
2393 * If only the state of the PROMISC flag changed,
2394 * then just use the 'set promisc mode' command
2395 * instead of reinitializing the entire NIC. Doing
2396 * a full re-init means reloading the firmware and
2397 * waiting for it to start up, which may take a
2398 * second or two.
2399 */
2400 if (ifp->if_flags & IFF_RUNNING &&
2401 ifp->if_flags & IFF_PROMISC &&
2402 !(sc->ti_if_flags & IFF_PROMISC)) {
2403 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2404 TI_CMD_CODE_PROMISC_ENB, 0);
2405 } else if (ifp->if_flags & IFF_RUNNING &&
2406 !(ifp->if_flags & IFF_PROMISC) &&
2407 sc->ti_if_flags & IFF_PROMISC) {
2408 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2409 TI_CMD_CODE_PROMISC_DIS, 0);
2410 } else
2411 ti_init(sc);
2412 } else {
2413 if (ifp->if_flags & IFF_RUNNING) {
2414 ti_stop(sc);
2415 }
2416 }
2417 sc->ti_if_flags = ifp->if_flags;
2418 error = 0;
2419 break;
2420 case SIOCADDMULTI:
2421 case SIOCDELMULTI:
2422 if (ifp->if_flags & IFF_RUNNING) {
2423 ti_setmulti(sc);
2424 error = 0;
2425 }
2426 break;
2427 case SIOCSIFMEDIA:
2428 case SIOCGIFMEDIA:
2429 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2430 break;
2431 default:
2432 error = EINVAL;
2433 break;
2434 }
2435
2436 (void)splx(s);
2437
2438 return(error);
2439}
2440
2441static void ti_watchdog(ifp)
2442 struct ifnet *ifp;
2443{
2444 struct ti_softc *sc;
2445
2446 sc = ifp->if_softc;
2447
2448 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2449 ti_stop(sc);
2450 ti_init(sc);
2451
2452 ifp->if_oerrors++;
2453
2454 return;
2455}
2456
2457/*
2458 * Stop the adapter and free any mbufs allocated to the
2459 * RX and TX lists.
2460 */
2461static void ti_stop(sc)
2462 struct ti_softc *sc;
2463{
2464 struct ifnet *ifp;
2465 struct ti_cmd_desc cmd;
2466
2467 ifp = &sc->arpcom.ac_if;
2468
2469 /* Disable host interrupts. */
2470 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2471 /*
2472 * Tell firmware we're shutting down.
2473 */
2474 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2475
2476 /* Halt and reinitialize. */
2477 ti_chipinit(sc);
2478 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2479 ti_chipinit(sc);
2480
2481 /* Free the RX lists. */
2482 ti_free_rx_ring_std(sc);
2483
2484 /* Free jumbo RX list. */
2485 ti_free_rx_ring_jumbo(sc);
2486
2487 /* Free mini RX list. */
2488 ti_free_rx_ring_mini(sc);
2489
2490 /* Free TX buffers. */
2491 ti_free_tx_ring(sc);
2492
2493 sc->ti_ev_prodidx.ti_idx = 0;
2494 sc->ti_return_prodidx.ti_idx = 0;
2495 sc->ti_tx_considx.ti_idx = 0;
2496 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2497
2498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2499
2500 return;
2501}
2502
2503/*
2504 * Stop all chip I/O so that the kernel's probe routines don't
2505 * get confused by errant DMAs when rebooting.
2506 */
2507static void ti_shutdown(dev)
2508 device_t dev;
2509{
2510 struct ti_softc *sc;
2511
2512 sc = device_get_softc(dev);
2513
2514 ti_chipinit(sc);
2515
2516 return;
2517}
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