1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
37 *
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
41 */
42
43/*
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
50 * initialization.
51 *
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
55 *
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
60 * stellar example.
61 *
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
68 *
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
71 * for testing
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
77 */
78
79#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
37 *
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
41 */
42
43/*
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
50 * initialization.
51 *
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
55 *
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
60 * stellar example.
61 *
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
68 *
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
71 * for testing
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
77 */
78
79#include <sys/cdefs.h>
|
80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 227091 2011-11-04 20:25:30Z yongari $");
| 80__FBSDID("$FreeBSD: head/sys/dev/ti/if_ti.c 227092 2011-11-04 20:43:37Z yongari $");
|
81
82#include "opt_ti.h"
83
84#include <sys/param.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#include <sys/module.h>
91#include <sys/socket.h>
92#include <sys/queue.h>
93#include <sys/conf.h>
94#include <sys/sf_buf.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
101#include <net/if_types.h>
102#include <net/if_vlan_var.h>
103
104#include <net/bpf.h>
105
106#include <netinet/in_systm.h>
107#include <netinet/in.h>
108#include <netinet/ip.h>
109
110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
115/* #define TI_PRIVATE_JUMBOS */
116#ifndef TI_PRIVATE_JUMBOS
117#include <vm/vm.h>
118#include <vm/vm_page.h>
119#endif
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#include <sys/tiio.h>
125#include <dev/ti/if_tireg.h>
126#include <dev/ti/ti_fw.h>
127#include <dev/ti/ti_fw2.h>
128
129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
130/*
131 * We can only turn on header splitting if we're using extended receive
132 * BDs.
133 */
134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
137
138typedef enum {
139 TI_SWAP_HTON,
140 TI_SWAP_NTOH
141} ti_swap_type;
142
143/*
144 * Various supported device vendors/types and their names.
145 */
146
147static const struct ti_type const ti_devs[] = {
148 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
151 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
152 { TC_VENDORID, TC_DEVICEID_3C985,
153 "3Com 3c985-SX Gigabit Ethernet" },
154 { NG_VENDORID, NG_DEVICEID_GA620,
155 "Netgear GA620 1000baseSX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620T,
157 "Netgear GA620 1000baseT Gigabit Ethernet" },
158 { SGI_VENDORID, SGI_DEVICEID_TIGON,
159 "Silicon Graphics Gigabit Ethernet" },
160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
161 "Farallon PN9000SX Gigabit Ethernet" },
162 { 0, 0, NULL }
163};
164
165
166static d_open_t ti_open;
167static d_close_t ti_close;
168static d_ioctl_t ti_ioctl2;
169
170static struct cdevsw ti_cdevsw = {
171 .d_version = D_VERSION,
172 .d_flags = 0,
173 .d_open = ti_open,
174 .d_close = ti_close,
175 .d_ioctl = ti_ioctl2,
176 .d_name = "ti",
177};
178
179static int ti_probe(device_t);
180static int ti_attach(device_t);
181static int ti_detach(device_t);
182static void ti_txeof(struct ti_softc *);
183static void ti_rxeof(struct ti_softc *);
184
185static void ti_stats_update(struct ti_softc *);
186static int ti_encap(struct ti_softc *, struct mbuf **);
187
188static void ti_intr(void *);
189static void ti_start(struct ifnet *);
190static void ti_start_locked(struct ifnet *);
191static int ti_ioctl(struct ifnet *, u_long, caddr_t);
192static void ti_init(void *);
193static void ti_init_locked(void *);
194static void ti_init2(struct ti_softc *);
195static void ti_stop(struct ti_softc *);
196static void ti_watchdog(void *);
197static int ti_shutdown(device_t);
198static int ti_ifmedia_upd(struct ifnet *);
199static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
200
201static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
202static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
203static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
204
205static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
206static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
207static void ti_setmulti(struct ti_softc *);
208
209static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
210static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
211static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
212static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
213 int);
214static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
215 int, int, int);
216static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
217static void ti_loadfw(struct ti_softc *);
218static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
219static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
220static void ti_handle_events(struct ti_softc *);
221static int ti_alloc_dmamaps(struct ti_softc *);
222static void ti_free_dmamaps(struct ti_softc *);
223static int ti_alloc_jumbo_mem(struct ti_softc *);
224#ifdef TI_PRIVATE_JUMBOS
225static void *ti_jalloc(struct ti_softc *);
226static void ti_jfree(void *, void *);
227#endif /* TI_PRIVATE_JUMBOS */
228static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
229static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
230static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
231static int ti_init_rx_ring_std(struct ti_softc *);
232static void ti_free_rx_ring_std(struct ti_softc *);
233static int ti_init_rx_ring_jumbo(struct ti_softc *);
234static void ti_free_rx_ring_jumbo(struct ti_softc *);
235static int ti_init_rx_ring_mini(struct ti_softc *);
236static void ti_free_rx_ring_mini(struct ti_softc *);
237static void ti_free_tx_ring(struct ti_softc *);
238static int ti_init_tx_ring(struct ti_softc *);
239
240static int ti_64bitslot_war(struct ti_softc *);
241static int ti_chipinit(struct ti_softc *);
242static int ti_gibinit(struct ti_softc *);
243
244#ifdef TI_JUMBO_HDRSPLIT
245static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
246 int idx);
247#endif /* TI_JUMBO_HDRSPLIT */
248
249static device_method_t ti_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, ti_probe),
252 DEVMETHOD(device_attach, ti_attach),
253 DEVMETHOD(device_detach, ti_detach),
254 DEVMETHOD(device_shutdown, ti_shutdown),
255 { 0, 0 }
256};
257
258static driver_t ti_driver = {
259 "ti",
260 ti_methods,
261 sizeof(struct ti_softc)
262};
263
264static devclass_t ti_devclass;
265
266DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
267MODULE_DEPEND(ti, pci, 1, 1, 1);
268MODULE_DEPEND(ti, ether, 1, 1, 1);
269
270/*
271 * Send an instruction or address to the EEPROM, check for ACK.
272 */
273static uint32_t
274ti_eeprom_putbyte(struct ti_softc *sc, int byte)
275{
276 int i, ack = 0;
277
278 /*
279 * Make sure we're in TX mode.
280 */
281 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
282
283 /*
284 * Feed in each bit and stobe the clock.
285 */
286 for (i = 0x80; i; i >>= 1) {
287 if (byte & i) {
288 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
289 } else {
290 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
291 }
292 DELAY(1);
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
294 DELAY(1);
295 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
296 }
297
298 /*
299 * Turn off TX mode.
300 */
301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
302
303 /*
304 * Check for ack.
305 */
306 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
309
310 return (ack);
311}
312
313/*
314 * Read a byte of data stored in the EEPROM at address 'addr.'
315 * We have to send two address bytes since the EEPROM can hold
316 * more than 256 bytes of data.
317 */
318static uint8_t
319ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
320{
321 int i;
322 uint8_t byte = 0;
323
324 EEPROM_START;
325
326 /*
327 * Send write control code to EEPROM.
328 */
329 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
330 device_printf(sc->ti_dev,
331 "failed to send write command, status: %x\n",
332 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
333 return (1);
334 }
335
336 /*
337 * Send first byte of address of byte we want to read.
338 */
339 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
340 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
342 return (1);
343 }
344 /*
345 * Send second byte address of byte we want to read.
346 */
347 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
348 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
349 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
350 return (1);
351 }
352
353 EEPROM_STOP;
354 EEPROM_START;
355 /*
356 * Send read control code to EEPROM.
357 */
358 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
359 device_printf(sc->ti_dev,
360 "failed to send read command, status: %x\n",
361 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
362 return (1);
363 }
364
365 /*
366 * Start reading bits from EEPROM.
367 */
368 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
369 for (i = 0x80; i; i >>= 1) {
370 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
371 DELAY(1);
372 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
373 byte |= i;
374 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
375 DELAY(1);
376 }
377
378 EEPROM_STOP;
379
380 /*
381 * No ACK generated for read, so just return byte.
382 */
383
384 *dest = byte;
385
386 return (0);
387}
388
389/*
390 * Read a sequence of bytes from the EEPROM.
391 */
392static int
393ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
394{
395 int err = 0, i;
396 uint8_t byte = 0;
397
398 for (i = 0; i < cnt; i++) {
399 err = ti_eeprom_getbyte(sc, off + i, &byte);
400 if (err)
401 break;
402 *(dest + i) = byte;
403 }
404
405 return (err ? 1 : 0);
406}
407
408/*
409 * NIC memory read function.
410 * Can be used to copy data from NIC local memory.
411 */
412static void
413ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
414{
415 int segptr, segsize, cnt;
416 char *ptr;
417
418 segptr = addr;
419 cnt = len;
420 ptr = buf;
421
422 while (cnt) {
423 if (cnt < TI_WINLEN)
424 segsize = cnt;
425 else
426 segsize = TI_WINLEN - (segptr % TI_WINLEN);
427 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
428 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
429 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
430 segsize / 4);
431 ptr += segsize;
432 segptr += segsize;
433 cnt -= segsize;
434 }
435}
436
437
438/*
439 * NIC memory write function.
440 * Can be used to copy data into NIC local memory.
441 */
442static void
443ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
444{
445 int segptr, segsize, cnt;
446 char *ptr;
447
448 segptr = addr;
449 cnt = len;
450 ptr = buf;
451
452 while (cnt) {
453 if (cnt < TI_WINLEN)
454 segsize = cnt;
455 else
456 segsize = TI_WINLEN - (segptr % TI_WINLEN);
457 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
458 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
459 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
460 segsize / 4);
461 ptr += segsize;
462 segptr += segsize;
463 cnt -= segsize;
464 }
465}
466
467/*
468 * NIC memory read function.
469 * Can be used to clear a section of NIC local memory.
470 */
471static void
472ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
473{
474 int segptr, segsize, cnt;
475
476 segptr = addr;
477 cnt = len;
478
479 while (cnt) {
480 if (cnt < TI_WINLEN)
481 segsize = cnt;
482 else
483 segsize = TI_WINLEN - (segptr % TI_WINLEN);
484 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
485 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
486 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
487 segptr += segsize;
488 cnt -= segsize;
489 }
490}
491
492static int
493ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
494 caddr_t buf, int useraddr, int readdata)
495{
496 int segptr, segsize, cnt;
497 caddr_t ptr;
498 uint32_t origwin;
499 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
500 int resid, segresid;
501 int first_pass;
502
503 TI_LOCK_ASSERT(sc);
504
505 /*
506 * At the moment, we don't handle non-aligned cases, we just bail.
507 * If this proves to be a problem, it will be fixed.
508 */
509 if ((readdata == 0)
510 && (tigon_addr & 0x3)) {
511 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
512 "word-aligned\n", __func__, tigon_addr);
513 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
514 "yet supported\n", __func__);
515 return (EINVAL);
516 }
517
518 segptr = tigon_addr & ~0x3;
519 segresid = tigon_addr - segptr;
520
521 /*
522 * This is the non-aligned amount left over that we'll need to
523 * copy.
524 */
525 resid = len & 0x3;
526
527 /* Add in the left over amount at the front of the buffer */
528 resid += segresid;
529
530 cnt = len & ~0x3;
531 /*
532 * If resid + segresid is >= 4, add multiples of 4 to the count and
533 * decrease the residual by that much.
534 */
535 cnt += resid & ~0x3;
536 resid -= resid & ~0x3;
537
538 ptr = buf;
539
540 first_pass = 1;
541
542 /*
543 * Save the old window base value.
544 */
545 origwin = CSR_READ_4(sc, TI_WINBASE);
546
547 while (cnt) {
548 bus_size_t ti_offset;
549
550 if (cnt < TI_WINLEN)
551 segsize = cnt;
552 else
553 segsize = TI_WINLEN - (segptr % TI_WINLEN);
554 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
555
556 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
557
558 if (readdata) {
559
560 bus_space_read_region_4(sc->ti_btag,
561 sc->ti_bhandle, ti_offset,
562 (uint32_t *)tmparray,
563 segsize >> 2);
564 if (useraddr) {
565 /*
566 * Yeah, this is a little on the kludgy
567 * side, but at least this code is only
568 * used for debugging.
569 */
570 ti_bcopy_swap(tmparray, tmparray2, segsize,
571 TI_SWAP_NTOH);
572
573 TI_UNLOCK(sc);
574 if (first_pass) {
575 copyout(&tmparray2[segresid], ptr,
576 segsize - segresid);
577 first_pass = 0;
578 } else
579 copyout(tmparray2, ptr, segsize);
580 TI_LOCK(sc);
581 } else {
582 if (first_pass) {
583
584 ti_bcopy_swap(tmparray, tmparray2,
585 segsize, TI_SWAP_NTOH);
586 TI_UNLOCK(sc);
587 bcopy(&tmparray2[segresid], ptr,
588 segsize - segresid);
589 TI_LOCK(sc);
590 first_pass = 0;
591 } else
592 ti_bcopy_swap(tmparray, ptr, segsize,
593 TI_SWAP_NTOH);
594 }
595
596 } else {
597 if (useraddr) {
598 TI_UNLOCK(sc);
599 copyin(ptr, tmparray2, segsize);
600 TI_LOCK(sc);
601 ti_bcopy_swap(tmparray2, tmparray, segsize,
602 TI_SWAP_HTON);
603 } else
604 ti_bcopy_swap(ptr, tmparray, segsize,
605 TI_SWAP_HTON);
606
607 bus_space_write_region_4(sc->ti_btag,
608 sc->ti_bhandle, ti_offset,
609 (uint32_t *)tmparray,
610 segsize >> 2);
611 }
612 segptr += segsize;
613 ptr += segsize;
614 cnt -= segsize;
615 }
616
617 /*
618 * Handle leftover, non-word-aligned bytes.
619 */
620 if (resid != 0) {
621 uint32_t tmpval, tmpval2;
622 bus_size_t ti_offset;
623
624 /*
625 * Set the segment pointer.
626 */
627 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
628
629 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
630
631 /*
632 * First, grab whatever is in our source/destination.
633 * We'll obviously need this for reads, but also for
634 * writes, since we'll be doing read/modify/write.
635 */
636 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
637 ti_offset, &tmpval, 1);
638
639 /*
640 * Next, translate this from little-endian to big-endian
641 * (at least on i386 boxes).
642 */
643 tmpval2 = ntohl(tmpval);
644
645 if (readdata) {
646 /*
647 * If we're reading, just copy the leftover number
648 * of bytes from the host byte order buffer to
649 * the user's buffer.
650 */
651 if (useraddr) {
652 TI_UNLOCK(sc);
653 copyout(&tmpval2, ptr, resid);
654 TI_LOCK(sc);
655 } else
656 bcopy(&tmpval2, ptr, resid);
657 } else {
658 /*
659 * If we're writing, first copy the bytes to be
660 * written into the network byte order buffer,
661 * leaving the rest of the buffer with whatever was
662 * originally in there. Then, swap the bytes
663 * around into host order and write them out.
664 *
665 * XXX KDM the read side of this has been verified
666 * to work, but the write side of it has not been
667 * verified. So user beware.
668 */
669 if (useraddr) {
670 TI_UNLOCK(sc);
671 copyin(ptr, &tmpval2, resid);
672 TI_LOCK(sc);
673 } else
674 bcopy(ptr, &tmpval2, resid);
675
676 tmpval = htonl(tmpval2);
677
678 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
679 ti_offset, &tmpval, 1);
680 }
681 }
682
683 CSR_WRITE_4(sc, TI_WINBASE, origwin);
684
685 return (0);
686}
687
688static int
689ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
690 caddr_t buf, int useraddr, int readdata, int cpu)
691{
692 uint32_t segptr;
693 int cnt;
694 uint32_t tmpval, tmpval2;
695 caddr_t ptr;
696
697 TI_LOCK_ASSERT(sc);
698
699 /*
700 * At the moment, we don't handle non-aligned cases, we just bail.
701 * If this proves to be a problem, it will be fixed.
702 */
703 if (tigon_addr & 0x3) {
704 device_printf(sc->ti_dev, "%s: tigon address %#x "
705 "isn't word-aligned\n", __func__, tigon_addr);
706 return (EINVAL);
707 }
708
709 if (len & 0x3) {
710 device_printf(sc->ti_dev, "%s: transfer length %d "
711 "isn't word-aligned\n", __func__, len);
712 return (EINVAL);
713 }
714
715 segptr = tigon_addr;
716 cnt = len;
717 ptr = buf;
718
719 while (cnt) {
720 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
721
722 if (readdata) {
723 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
724
725 tmpval = ntohl(tmpval2);
726
727 /*
728 * Note: I've used this debugging interface
729 * extensively with Alteon's 12.3.15 firmware,
730 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
731 *
732 * When you compile the firmware without
733 * optimization, which is necessary sometimes in
734 * order to properly step through it, you sometimes
735 * read out a bogus value of 0xc0017c instead of
736 * whatever was supposed to be in that scratchpad
737 * location. That value is on the stack somewhere,
738 * but I've never been able to figure out what was
739 * causing the problem.
740 *
741 * The address seems to pop up in random places,
742 * often not in the same place on two subsequent
743 * reads.
744 *
745 * In any case, the underlying data doesn't seem
746 * to be affected, just the value read out.
747 *
748 * KDM, 3/7/2000
749 */
750
751 if (tmpval2 == 0xc0017c)
752 device_printf(sc->ti_dev, "found 0xc0017c at "
753 "%#x (tmpval2)\n", segptr);
754
755 if (tmpval == 0xc0017c)
756 device_printf(sc->ti_dev, "found 0xc0017c at "
757 "%#x (tmpval)\n", segptr);
758
759 if (useraddr)
760 copyout(&tmpval, ptr, 4);
761 else
762 bcopy(&tmpval, ptr, 4);
763 } else {
764 if (useraddr)
765 copyin(ptr, &tmpval2, 4);
766 else
767 bcopy(ptr, &tmpval2, 4);
768
769 tmpval = htonl(tmpval2);
770
771 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
772 }
773
774 cnt -= 4;
775 segptr += 4;
776 ptr += 4;
777 }
778
779 return (0);
780}
781
782static int
783ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
784{
785 const uint8_t *tmpsrc;
786 uint8_t *tmpdst;
787 size_t tmplen;
788
789 if (len & 0x3) {
790 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
791 len);
792 return (-1);
793 }
794
795 tmpsrc = src;
796 tmpdst = dst;
797 tmplen = len;
798
799 while (tmplen) {
800 if (swap_type == TI_SWAP_NTOH)
801 *(uint32_t *)tmpdst =
802 ntohl(*(const uint32_t *)tmpsrc);
803 else
804 *(uint32_t *)tmpdst =
805 htonl(*(const uint32_t *)tmpsrc);
806
807 tmpsrc += 4;
808 tmpdst += 4;
809 tmplen -= 4;
810 }
811
812 return (0);
813}
814
815/*
816 * Load firmware image into the NIC. Check that the firmware revision
817 * is acceptable and see if we want the firmware for the Tigon 1 or
818 * Tigon 2.
819 */
820static void
821ti_loadfw(struct ti_softc *sc)
822{
823
824 TI_LOCK_ASSERT(sc);
825
826 switch (sc->ti_hwrev) {
827 case TI_HWREV_TIGON:
828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
830 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
831 device_printf(sc->ti_dev, "firmware revision mismatch; "
832 "want %d.%d.%d, got %d.%d.%d\n",
833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
834 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
835 tigonFwReleaseMinor, tigonFwReleaseFix);
836 return;
837 }
838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
841 tigonFwRodata);
842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
845 break;
846 case TI_HWREV_TIGON_II:
847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
850 device_printf(sc->ti_dev, "firmware revision mismatch; "
851 "want %d.%d.%d, got %d.%d.%d\n",
852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
854 tigon2FwReleaseMinor, tigon2FwReleaseFix);
855 return;
856 }
857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
858 tigon2FwText);
859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
860 tigon2FwData);
861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
862 tigon2FwRodata);
863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
866 break;
867 default:
868 device_printf(sc->ti_dev,
869 "can't load firmware: unknown hardware rev\n");
870 break;
871 }
872}
873
874/*
875 * Send the NIC a command via the command ring.
876 */
877static void
878ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
879{
880 int index;
881
882 index = sc->ti_cmd_saved_prodidx;
883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 TI_INC(index, TI_CMD_RING_CNT);
885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
886 sc->ti_cmd_saved_prodidx = index;
887}
888
889/*
890 * Send the NIC an extended command. The 'len' parameter specifies the
891 * number of command slots to include after the initial command.
892 */
893static void
894ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
895{
896 int index;
897 int i;
898
899 index = sc->ti_cmd_saved_prodidx;
900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
901 TI_INC(index, TI_CMD_RING_CNT);
902 for (i = 0; i < len; i++) {
903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
904 *(uint32_t *)(&arg[i * 4]));
905 TI_INC(index, TI_CMD_RING_CNT);
906 }
907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
908 sc->ti_cmd_saved_prodidx = index;
909}
910
911/*
912 * Handle events that have triggered interrupts.
913 */
914static void
915ti_handle_events(struct ti_softc *sc)
916{
917 struct ti_event_desc *e;
918
919 if (sc->ti_rdata->ti_event_ring == NULL)
920 return;
921
922 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
923 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
924 switch (TI_EVENT_EVENT(e)) {
925 case TI_EV_LINKSTAT_CHANGED:
926 sc->ti_linkstat = TI_EVENT_CODE(e);
| 81
82#include "opt_ti.h"
83
84#include <sys/param.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#include <sys/module.h>
91#include <sys/socket.h>
92#include <sys/queue.h>
93#include <sys/conf.h>
94#include <sys/sf_buf.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
101#include <net/if_types.h>
102#include <net/if_vlan_var.h>
103
104#include <net/bpf.h>
105
106#include <netinet/in_systm.h>
107#include <netinet/in.h>
108#include <netinet/ip.h>
109
110#include <machine/bus.h>
111#include <machine/resource.h>
112#include <sys/bus.h>
113#include <sys/rman.h>
114
115/* #define TI_PRIVATE_JUMBOS */
116#ifndef TI_PRIVATE_JUMBOS
117#include <vm/vm.h>
118#include <vm/vm_page.h>
119#endif
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#include <sys/tiio.h>
125#include <dev/ti/if_tireg.h>
126#include <dev/ti/ti_fw.h>
127#include <dev/ti/ti_fw2.h>
128
129#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
130/*
131 * We can only turn on header splitting if we're using extended receive
132 * BDs.
133 */
134#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
135#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
136#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
137
138typedef enum {
139 TI_SWAP_HTON,
140 TI_SWAP_NTOH
141} ti_swap_type;
142
143/*
144 * Various supported device vendors/types and their names.
145 */
146
147static const struct ti_type const ti_devs[] = {
148 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
149 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
150 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
151 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
152 { TC_VENDORID, TC_DEVICEID_3C985,
153 "3Com 3c985-SX Gigabit Ethernet" },
154 { NG_VENDORID, NG_DEVICEID_GA620,
155 "Netgear GA620 1000baseSX Gigabit Ethernet" },
156 { NG_VENDORID, NG_DEVICEID_GA620T,
157 "Netgear GA620 1000baseT Gigabit Ethernet" },
158 { SGI_VENDORID, SGI_DEVICEID_TIGON,
159 "Silicon Graphics Gigabit Ethernet" },
160 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
161 "Farallon PN9000SX Gigabit Ethernet" },
162 { 0, 0, NULL }
163};
164
165
166static d_open_t ti_open;
167static d_close_t ti_close;
168static d_ioctl_t ti_ioctl2;
169
170static struct cdevsw ti_cdevsw = {
171 .d_version = D_VERSION,
172 .d_flags = 0,
173 .d_open = ti_open,
174 .d_close = ti_close,
175 .d_ioctl = ti_ioctl2,
176 .d_name = "ti",
177};
178
179static int ti_probe(device_t);
180static int ti_attach(device_t);
181static int ti_detach(device_t);
182static void ti_txeof(struct ti_softc *);
183static void ti_rxeof(struct ti_softc *);
184
185static void ti_stats_update(struct ti_softc *);
186static int ti_encap(struct ti_softc *, struct mbuf **);
187
188static void ti_intr(void *);
189static void ti_start(struct ifnet *);
190static void ti_start_locked(struct ifnet *);
191static int ti_ioctl(struct ifnet *, u_long, caddr_t);
192static void ti_init(void *);
193static void ti_init_locked(void *);
194static void ti_init2(struct ti_softc *);
195static void ti_stop(struct ti_softc *);
196static void ti_watchdog(void *);
197static int ti_shutdown(device_t);
198static int ti_ifmedia_upd(struct ifnet *);
199static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
200
201static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
202static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
203static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
204
205static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
206static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
207static void ti_setmulti(struct ti_softc *);
208
209static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
210static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
211static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
212static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
213 int);
214static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
215 int, int, int);
216static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
217static void ti_loadfw(struct ti_softc *);
218static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
219static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
220static void ti_handle_events(struct ti_softc *);
221static int ti_alloc_dmamaps(struct ti_softc *);
222static void ti_free_dmamaps(struct ti_softc *);
223static int ti_alloc_jumbo_mem(struct ti_softc *);
224#ifdef TI_PRIVATE_JUMBOS
225static void *ti_jalloc(struct ti_softc *);
226static void ti_jfree(void *, void *);
227#endif /* TI_PRIVATE_JUMBOS */
228static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
229static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
230static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
231static int ti_init_rx_ring_std(struct ti_softc *);
232static void ti_free_rx_ring_std(struct ti_softc *);
233static int ti_init_rx_ring_jumbo(struct ti_softc *);
234static void ti_free_rx_ring_jumbo(struct ti_softc *);
235static int ti_init_rx_ring_mini(struct ti_softc *);
236static void ti_free_rx_ring_mini(struct ti_softc *);
237static void ti_free_tx_ring(struct ti_softc *);
238static int ti_init_tx_ring(struct ti_softc *);
239
240static int ti_64bitslot_war(struct ti_softc *);
241static int ti_chipinit(struct ti_softc *);
242static int ti_gibinit(struct ti_softc *);
243
244#ifdef TI_JUMBO_HDRSPLIT
245static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
246 int idx);
247#endif /* TI_JUMBO_HDRSPLIT */
248
249static device_method_t ti_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, ti_probe),
252 DEVMETHOD(device_attach, ti_attach),
253 DEVMETHOD(device_detach, ti_detach),
254 DEVMETHOD(device_shutdown, ti_shutdown),
255 { 0, 0 }
256};
257
258static driver_t ti_driver = {
259 "ti",
260 ti_methods,
261 sizeof(struct ti_softc)
262};
263
264static devclass_t ti_devclass;
265
266DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
267MODULE_DEPEND(ti, pci, 1, 1, 1);
268MODULE_DEPEND(ti, ether, 1, 1, 1);
269
270/*
271 * Send an instruction or address to the EEPROM, check for ACK.
272 */
273static uint32_t
274ti_eeprom_putbyte(struct ti_softc *sc, int byte)
275{
276 int i, ack = 0;
277
278 /*
279 * Make sure we're in TX mode.
280 */
281 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
282
283 /*
284 * Feed in each bit and stobe the clock.
285 */
286 for (i = 0x80; i; i >>= 1) {
287 if (byte & i) {
288 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
289 } else {
290 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
291 }
292 DELAY(1);
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
294 DELAY(1);
295 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
296 }
297
298 /*
299 * Turn off TX mode.
300 */
301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
302
303 /*
304 * Check for ack.
305 */
306 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
309
310 return (ack);
311}
312
313/*
314 * Read a byte of data stored in the EEPROM at address 'addr.'
315 * We have to send two address bytes since the EEPROM can hold
316 * more than 256 bytes of data.
317 */
318static uint8_t
319ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
320{
321 int i;
322 uint8_t byte = 0;
323
324 EEPROM_START;
325
326 /*
327 * Send write control code to EEPROM.
328 */
329 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
330 device_printf(sc->ti_dev,
331 "failed to send write command, status: %x\n",
332 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
333 return (1);
334 }
335
336 /*
337 * Send first byte of address of byte we want to read.
338 */
339 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
340 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
341 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
342 return (1);
343 }
344 /*
345 * Send second byte address of byte we want to read.
346 */
347 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
348 device_printf(sc->ti_dev, "failed to send address, status: %x\n",
349 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
350 return (1);
351 }
352
353 EEPROM_STOP;
354 EEPROM_START;
355 /*
356 * Send read control code to EEPROM.
357 */
358 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
359 device_printf(sc->ti_dev,
360 "failed to send read command, status: %x\n",
361 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
362 return (1);
363 }
364
365 /*
366 * Start reading bits from EEPROM.
367 */
368 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
369 for (i = 0x80; i; i >>= 1) {
370 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
371 DELAY(1);
372 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
373 byte |= i;
374 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
375 DELAY(1);
376 }
377
378 EEPROM_STOP;
379
380 /*
381 * No ACK generated for read, so just return byte.
382 */
383
384 *dest = byte;
385
386 return (0);
387}
388
389/*
390 * Read a sequence of bytes from the EEPROM.
391 */
392static int
393ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
394{
395 int err = 0, i;
396 uint8_t byte = 0;
397
398 for (i = 0; i < cnt; i++) {
399 err = ti_eeprom_getbyte(sc, off + i, &byte);
400 if (err)
401 break;
402 *(dest + i) = byte;
403 }
404
405 return (err ? 1 : 0);
406}
407
408/*
409 * NIC memory read function.
410 * Can be used to copy data from NIC local memory.
411 */
412static void
413ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
414{
415 int segptr, segsize, cnt;
416 char *ptr;
417
418 segptr = addr;
419 cnt = len;
420 ptr = buf;
421
422 while (cnt) {
423 if (cnt < TI_WINLEN)
424 segsize = cnt;
425 else
426 segsize = TI_WINLEN - (segptr % TI_WINLEN);
427 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
428 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
429 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
430 segsize / 4);
431 ptr += segsize;
432 segptr += segsize;
433 cnt -= segsize;
434 }
435}
436
437
438/*
439 * NIC memory write function.
440 * Can be used to copy data into NIC local memory.
441 */
442static void
443ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
444{
445 int segptr, segsize, cnt;
446 char *ptr;
447
448 segptr = addr;
449 cnt = len;
450 ptr = buf;
451
452 while (cnt) {
453 if (cnt < TI_WINLEN)
454 segsize = cnt;
455 else
456 segsize = TI_WINLEN - (segptr % TI_WINLEN);
457 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
458 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
459 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
460 segsize / 4);
461 ptr += segsize;
462 segptr += segsize;
463 cnt -= segsize;
464 }
465}
466
467/*
468 * NIC memory read function.
469 * Can be used to clear a section of NIC local memory.
470 */
471static void
472ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
473{
474 int segptr, segsize, cnt;
475
476 segptr = addr;
477 cnt = len;
478
479 while (cnt) {
480 if (cnt < TI_WINLEN)
481 segsize = cnt;
482 else
483 segsize = TI_WINLEN - (segptr % TI_WINLEN);
484 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
485 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
486 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
487 segptr += segsize;
488 cnt -= segsize;
489 }
490}
491
492static int
493ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
494 caddr_t buf, int useraddr, int readdata)
495{
496 int segptr, segsize, cnt;
497 caddr_t ptr;
498 uint32_t origwin;
499 uint8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
500 int resid, segresid;
501 int first_pass;
502
503 TI_LOCK_ASSERT(sc);
504
505 /*
506 * At the moment, we don't handle non-aligned cases, we just bail.
507 * If this proves to be a problem, it will be fixed.
508 */
509 if ((readdata == 0)
510 && (tigon_addr & 0x3)) {
511 device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
512 "word-aligned\n", __func__, tigon_addr);
513 device_printf(sc->ti_dev, "%s: unaligned writes aren't "
514 "yet supported\n", __func__);
515 return (EINVAL);
516 }
517
518 segptr = tigon_addr & ~0x3;
519 segresid = tigon_addr - segptr;
520
521 /*
522 * This is the non-aligned amount left over that we'll need to
523 * copy.
524 */
525 resid = len & 0x3;
526
527 /* Add in the left over amount at the front of the buffer */
528 resid += segresid;
529
530 cnt = len & ~0x3;
531 /*
532 * If resid + segresid is >= 4, add multiples of 4 to the count and
533 * decrease the residual by that much.
534 */
535 cnt += resid & ~0x3;
536 resid -= resid & ~0x3;
537
538 ptr = buf;
539
540 first_pass = 1;
541
542 /*
543 * Save the old window base value.
544 */
545 origwin = CSR_READ_4(sc, TI_WINBASE);
546
547 while (cnt) {
548 bus_size_t ti_offset;
549
550 if (cnt < TI_WINLEN)
551 segsize = cnt;
552 else
553 segsize = TI_WINLEN - (segptr % TI_WINLEN);
554 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
555
556 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
557
558 if (readdata) {
559
560 bus_space_read_region_4(sc->ti_btag,
561 sc->ti_bhandle, ti_offset,
562 (uint32_t *)tmparray,
563 segsize >> 2);
564 if (useraddr) {
565 /*
566 * Yeah, this is a little on the kludgy
567 * side, but at least this code is only
568 * used for debugging.
569 */
570 ti_bcopy_swap(tmparray, tmparray2, segsize,
571 TI_SWAP_NTOH);
572
573 TI_UNLOCK(sc);
574 if (first_pass) {
575 copyout(&tmparray2[segresid], ptr,
576 segsize - segresid);
577 first_pass = 0;
578 } else
579 copyout(tmparray2, ptr, segsize);
580 TI_LOCK(sc);
581 } else {
582 if (first_pass) {
583
584 ti_bcopy_swap(tmparray, tmparray2,
585 segsize, TI_SWAP_NTOH);
586 TI_UNLOCK(sc);
587 bcopy(&tmparray2[segresid], ptr,
588 segsize - segresid);
589 TI_LOCK(sc);
590 first_pass = 0;
591 } else
592 ti_bcopy_swap(tmparray, ptr, segsize,
593 TI_SWAP_NTOH);
594 }
595
596 } else {
597 if (useraddr) {
598 TI_UNLOCK(sc);
599 copyin(ptr, tmparray2, segsize);
600 TI_LOCK(sc);
601 ti_bcopy_swap(tmparray2, tmparray, segsize,
602 TI_SWAP_HTON);
603 } else
604 ti_bcopy_swap(ptr, tmparray, segsize,
605 TI_SWAP_HTON);
606
607 bus_space_write_region_4(sc->ti_btag,
608 sc->ti_bhandle, ti_offset,
609 (uint32_t *)tmparray,
610 segsize >> 2);
611 }
612 segptr += segsize;
613 ptr += segsize;
614 cnt -= segsize;
615 }
616
617 /*
618 * Handle leftover, non-word-aligned bytes.
619 */
620 if (resid != 0) {
621 uint32_t tmpval, tmpval2;
622 bus_size_t ti_offset;
623
624 /*
625 * Set the segment pointer.
626 */
627 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
628
629 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
630
631 /*
632 * First, grab whatever is in our source/destination.
633 * We'll obviously need this for reads, but also for
634 * writes, since we'll be doing read/modify/write.
635 */
636 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
637 ti_offset, &tmpval, 1);
638
639 /*
640 * Next, translate this from little-endian to big-endian
641 * (at least on i386 boxes).
642 */
643 tmpval2 = ntohl(tmpval);
644
645 if (readdata) {
646 /*
647 * If we're reading, just copy the leftover number
648 * of bytes from the host byte order buffer to
649 * the user's buffer.
650 */
651 if (useraddr) {
652 TI_UNLOCK(sc);
653 copyout(&tmpval2, ptr, resid);
654 TI_LOCK(sc);
655 } else
656 bcopy(&tmpval2, ptr, resid);
657 } else {
658 /*
659 * If we're writing, first copy the bytes to be
660 * written into the network byte order buffer,
661 * leaving the rest of the buffer with whatever was
662 * originally in there. Then, swap the bytes
663 * around into host order and write them out.
664 *
665 * XXX KDM the read side of this has been verified
666 * to work, but the write side of it has not been
667 * verified. So user beware.
668 */
669 if (useraddr) {
670 TI_UNLOCK(sc);
671 copyin(ptr, &tmpval2, resid);
672 TI_LOCK(sc);
673 } else
674 bcopy(ptr, &tmpval2, resid);
675
676 tmpval = htonl(tmpval2);
677
678 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
679 ti_offset, &tmpval, 1);
680 }
681 }
682
683 CSR_WRITE_4(sc, TI_WINBASE, origwin);
684
685 return (0);
686}
687
688static int
689ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
690 caddr_t buf, int useraddr, int readdata, int cpu)
691{
692 uint32_t segptr;
693 int cnt;
694 uint32_t tmpval, tmpval2;
695 caddr_t ptr;
696
697 TI_LOCK_ASSERT(sc);
698
699 /*
700 * At the moment, we don't handle non-aligned cases, we just bail.
701 * If this proves to be a problem, it will be fixed.
702 */
703 if (tigon_addr & 0x3) {
704 device_printf(sc->ti_dev, "%s: tigon address %#x "
705 "isn't word-aligned\n", __func__, tigon_addr);
706 return (EINVAL);
707 }
708
709 if (len & 0x3) {
710 device_printf(sc->ti_dev, "%s: transfer length %d "
711 "isn't word-aligned\n", __func__, len);
712 return (EINVAL);
713 }
714
715 segptr = tigon_addr;
716 cnt = len;
717 ptr = buf;
718
719 while (cnt) {
720 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
721
722 if (readdata) {
723 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
724
725 tmpval = ntohl(tmpval2);
726
727 /*
728 * Note: I've used this debugging interface
729 * extensively with Alteon's 12.3.15 firmware,
730 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
731 *
732 * When you compile the firmware without
733 * optimization, which is necessary sometimes in
734 * order to properly step through it, you sometimes
735 * read out a bogus value of 0xc0017c instead of
736 * whatever was supposed to be in that scratchpad
737 * location. That value is on the stack somewhere,
738 * but I've never been able to figure out what was
739 * causing the problem.
740 *
741 * The address seems to pop up in random places,
742 * often not in the same place on two subsequent
743 * reads.
744 *
745 * In any case, the underlying data doesn't seem
746 * to be affected, just the value read out.
747 *
748 * KDM, 3/7/2000
749 */
750
751 if (tmpval2 == 0xc0017c)
752 device_printf(sc->ti_dev, "found 0xc0017c at "
753 "%#x (tmpval2)\n", segptr);
754
755 if (tmpval == 0xc0017c)
756 device_printf(sc->ti_dev, "found 0xc0017c at "
757 "%#x (tmpval)\n", segptr);
758
759 if (useraddr)
760 copyout(&tmpval, ptr, 4);
761 else
762 bcopy(&tmpval, ptr, 4);
763 } else {
764 if (useraddr)
765 copyin(ptr, &tmpval2, 4);
766 else
767 bcopy(ptr, &tmpval2, 4);
768
769 tmpval = htonl(tmpval2);
770
771 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
772 }
773
774 cnt -= 4;
775 segptr += 4;
776 ptr += 4;
777 }
778
779 return (0);
780}
781
782static int
783ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
784{
785 const uint8_t *tmpsrc;
786 uint8_t *tmpdst;
787 size_t tmplen;
788
789 if (len & 0x3) {
790 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
791 len);
792 return (-1);
793 }
794
795 tmpsrc = src;
796 tmpdst = dst;
797 tmplen = len;
798
799 while (tmplen) {
800 if (swap_type == TI_SWAP_NTOH)
801 *(uint32_t *)tmpdst =
802 ntohl(*(const uint32_t *)tmpsrc);
803 else
804 *(uint32_t *)tmpdst =
805 htonl(*(const uint32_t *)tmpsrc);
806
807 tmpsrc += 4;
808 tmpdst += 4;
809 tmplen -= 4;
810 }
811
812 return (0);
813}
814
815/*
816 * Load firmware image into the NIC. Check that the firmware revision
817 * is acceptable and see if we want the firmware for the Tigon 1 or
818 * Tigon 2.
819 */
820static void
821ti_loadfw(struct ti_softc *sc)
822{
823
824 TI_LOCK_ASSERT(sc);
825
826 switch (sc->ti_hwrev) {
827 case TI_HWREV_TIGON:
828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
830 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
831 device_printf(sc->ti_dev, "firmware revision mismatch; "
832 "want %d.%d.%d, got %d.%d.%d\n",
833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
834 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
835 tigonFwReleaseMinor, tigonFwReleaseFix);
836 return;
837 }
838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
841 tigonFwRodata);
842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
845 break;
846 case TI_HWREV_TIGON_II:
847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
850 device_printf(sc->ti_dev, "firmware revision mismatch; "
851 "want %d.%d.%d, got %d.%d.%d\n",
852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
854 tigon2FwReleaseMinor, tigon2FwReleaseFix);
855 return;
856 }
857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
858 tigon2FwText);
859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
860 tigon2FwData);
861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
862 tigon2FwRodata);
863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
866 break;
867 default:
868 device_printf(sc->ti_dev,
869 "can't load firmware: unknown hardware rev\n");
870 break;
871 }
872}
873
874/*
875 * Send the NIC a command via the command ring.
876 */
877static void
878ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
879{
880 int index;
881
882 index = sc->ti_cmd_saved_prodidx;
883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 TI_INC(index, TI_CMD_RING_CNT);
885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
886 sc->ti_cmd_saved_prodidx = index;
887}
888
889/*
890 * Send the NIC an extended command. The 'len' parameter specifies the
891 * number of command slots to include after the initial command.
892 */
893static void
894ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
895{
896 int index;
897 int i;
898
899 index = sc->ti_cmd_saved_prodidx;
900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
901 TI_INC(index, TI_CMD_RING_CNT);
902 for (i = 0; i < len; i++) {
903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
904 *(uint32_t *)(&arg[i * 4]));
905 TI_INC(index, TI_CMD_RING_CNT);
906 }
907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
908 sc->ti_cmd_saved_prodidx = index;
909}
910
911/*
912 * Handle events that have triggered interrupts.
913 */
914static void
915ti_handle_events(struct ti_softc *sc)
916{
917 struct ti_event_desc *e;
918
919 if (sc->ti_rdata->ti_event_ring == NULL)
920 return;
921
922 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
923 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
924 switch (TI_EVENT_EVENT(e)) {
925 case TI_EV_LINKSTAT_CHANGED:
926 sc->ti_linkstat = TI_EVENT_CODE(e);
|
927 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
928 device_printf(sc->ti_dev, "10/100 link up\n");
929 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
930 device_printf(sc->ti_dev, "gigabit link up\n");
931 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
932 device_printf(sc->ti_dev, "link down\n");
| 927 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
928 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
929 sc->ti_ifp->if_baudrate = IF_Mbps(100);
930 if (bootverbose)
931 device_printf(sc->ti_dev,
932 "10/100 link up\n");
933 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
934 if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
935 sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
936 if (bootverbose)
937 device_printf(sc->ti_dev,
938 "gigabit link up\n");
939 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
940 if_link_state_change(sc->ti_ifp,
941 LINK_STATE_DOWN);
942 sc->ti_ifp->if_baudrate = 0;
943 if (bootverbose)
944 device_printf(sc->ti_dev,
945 "link down\n");
946 }
|
933 break;
934 case TI_EV_ERROR:
935 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
936 device_printf(sc->ti_dev, "invalid command\n");
937 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
938 device_printf(sc->ti_dev, "unknown command\n");
939 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
940 device_printf(sc->ti_dev, "bad config data\n");
941 break;
942 case TI_EV_FIRMWARE_UP:
943 ti_init2(sc);
944 break;
945 case TI_EV_STATS_UPDATED:
946 ti_stats_update(sc);
947 break;
948 case TI_EV_RESET_JUMBO_RING:
949 case TI_EV_MCAST_UPDATED:
950 /* Who cares. */
951 break;
952 default:
953 device_printf(sc->ti_dev, "unknown event: %d\n",
954 TI_EVENT_EVENT(e));
955 break;
956 }
957 /* Advance the consumer index. */
958 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
959 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
960 }
961}
962
963static int
964ti_alloc_dmamaps(struct ti_softc *sc)
965{
966 int i;
967
968 for (i = 0; i < TI_TX_RING_CNT; i++) {
969 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
970 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
971 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
972 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
973 return (ENOBUFS);
974 }
975 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
976 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
977 &sc->ti_cdata.ti_rx_std_maps[i]))
978 return (ENOBUFS);
979 }
980
981 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
982 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
983 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
984 return (ENOBUFS);
985 }
986 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
987 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
988 &sc->ti_cdata.ti_rx_mini_maps[i]))
989 return (ENOBUFS);
990 }
991
992 return (0);
993}
994
995static void
996ti_free_dmamaps(struct ti_softc *sc)
997{
998 int i;
999
1000 if (sc->ti_mbuftx_dmat)
1001 for (i = 0; i < TI_TX_RING_CNT; i++)
1002 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1003 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1005 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1006 }
1007
1008 if (sc->ti_mbufrx_dmat)
1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1010 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1011 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1012 sc->ti_cdata.ti_rx_std_maps[i]);
1013 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1014 }
1015
1016 if (sc->ti_jumbo_dmat)
1017 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1018 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1019 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1020 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1021 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1022 }
1023 if (sc->ti_mbufrx_dmat)
1024 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1025 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1026 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1027 sc->ti_cdata.ti_rx_mini_maps[i]);
1028 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1029 }
1030}
1031
1032#ifdef TI_PRIVATE_JUMBOS
1033
1034/*
1035 * Memory management for the jumbo receive ring is a pain in the
1036 * butt. We need to allocate at least 9018 bytes of space per frame,
1037 * _and_ it has to be contiguous (unless you use the extended
1038 * jumbo descriptor format). Using malloc() all the time won't
1039 * work: malloc() allocates memory in powers of two, which means we
1040 * would end up wasting a considerable amount of space by allocating
1041 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1042 * to do our own memory management.
1043 *
1044 * The driver needs to allocate a contiguous chunk of memory at boot
1045 * time. We then chop this up ourselves into 9K pieces and use them
1046 * as external mbuf storage.
1047 *
1048 * One issue here is how much memory to allocate. The jumbo ring has
1049 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1050 * RAM. This is a bit much, especially considering we also need
1051 * RAM for the standard ring and mini ring (on the Tigon 2). To
1052 * save space, we only actually allocate enough memory for 64 slots
1053 * by default, which works out to between 500 and 600K. This can
1054 * be tuned by changing a #define in if_tireg.h.
1055 */
1056
1057static int
1058ti_alloc_jumbo_mem(struct ti_softc *sc)
1059{
1060 struct ti_jpool_entry *entry;
1061 caddr_t ptr;
1062 int i;
1063
1064 /*
1065 * Grab a big chunk o' storage. Since we are chopping this pool up
1066 * into ~9k chunks, there doesn't appear to be a need to use page
1067 * alignment.
1068 */
1069 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1070 1, 0, /* algnmnt, boundary */
1071 BUS_SPACE_MAXADDR, /* lowaddr */
1072 BUS_SPACE_MAXADDR, /* highaddr */
1073 NULL, NULL, /* filter, filterarg */
1074 TI_JMEM, /* maxsize */
1075 1, /* nsegments */
1076 TI_JMEM, /* maxsegsize */
1077 0, /* flags */
1078 NULL, NULL, /* lockfunc, lockarg */
1079 &sc->ti_jumbo_dmat) != 0) {
1080 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1081 return (ENOBUFS);
1082 }
1083
1084 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1085 (void**)&sc->ti_cdata.ti_jumbo_buf,
1086 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1087 &sc->ti_jumbo_dmamap) != 0) {
1088 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1089 return (ENOBUFS);
1090 }
1091
1092 SLIST_INIT(&sc->ti_jfree_listhead);
1093 SLIST_INIT(&sc->ti_jinuse_listhead);
1094
1095 /*
1096 * Now divide it up into 9K pieces and save the addresses
1097 * in an array.
1098 */
1099 ptr = sc->ti_cdata.ti_jumbo_buf;
1100 for (i = 0; i < TI_JSLOTS; i++) {
1101 sc->ti_cdata.ti_jslots[i] = ptr;
1102 ptr += TI_JLEN;
1103 entry = malloc(sizeof(struct ti_jpool_entry),
1104 M_DEVBUF, M_NOWAIT);
1105 if (entry == NULL) {
1106 device_printf(sc->ti_dev, "no memory for jumbo "
1107 "buffer queue!\n");
1108 return (ENOBUFS);
1109 }
1110 entry->slot = i;
1111 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1112 }
1113
1114 return (0);
1115}
1116
1117/*
1118 * Allocate a jumbo buffer.
1119 */
1120static void *ti_jalloc(struct ti_softc *sc)
1121{
1122 struct ti_jpool_entry *entry;
1123
1124 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1125
1126 if (entry == NULL) {
1127 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1128 return (NULL);
1129 }
1130
1131 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1132 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1133 return (sc->ti_cdata.ti_jslots[entry->slot]);
1134}
1135
1136/*
1137 * Release a jumbo buffer.
1138 */
1139static void
1140ti_jfree(void *buf, void *args)
1141{
1142 struct ti_softc *sc;
1143 int i;
1144 struct ti_jpool_entry *entry;
1145
1146 /* Extract the softc struct pointer. */
1147 sc = (struct ti_softc *)args;
1148
1149 if (sc == NULL)
1150 panic("ti_jfree: didn't get softc pointer!");
1151
1152 /* calculate the slot this buffer belongs to */
1153 i = ((vm_offset_t)buf
1154 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1155
1156 if ((i < 0) || (i >= TI_JSLOTS))
1157 panic("ti_jfree: asked to free buffer that we don't manage!");
1158
1159 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1160 if (entry == NULL)
1161 panic("ti_jfree: buffer not in use!");
1162 entry->slot = i;
1163 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1164 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1165}
1166
1167#else
1168
1169static int
1170ti_alloc_jumbo_mem(struct ti_softc *sc)
1171{
1172
1173 /*
1174 * The VM system will take care of providing aligned pages. Alignment
1175 * is set to 1 here so that busdma resources won't be wasted.
1176 */
1177 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1178 1, 0, /* algnmnt, boundary */
1179 BUS_SPACE_MAXADDR, /* lowaddr */
1180 BUS_SPACE_MAXADDR, /* highaddr */
1181 NULL, NULL, /* filter, filterarg */
1182 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1183 4, /* nsegments */
1184 PAGE_SIZE, /* maxsegsize */
1185 0, /* flags */
1186 NULL, NULL, /* lockfunc, lockarg */
1187 &sc->ti_jumbo_dmat) != 0) {
1188 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1189 return (ENOBUFS);
1190 }
1191
1192 return (0);
1193}
1194
1195#endif /* TI_PRIVATE_JUMBOS */
1196
1197/*
1198 * Intialize a standard receive ring descriptor.
1199 */
1200static int
1201ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
1202{
1203 bus_dmamap_t map;
1204 bus_dma_segment_t segs;
1205 struct mbuf *m_new = NULL;
1206 struct ti_rx_desc *r;
1207 int nsegs;
1208
1209 nsegs = 0;
1210 if (m == NULL) {
1211 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1212 if (m_new == NULL)
1213 return (ENOBUFS);
1214
1215 MCLGET(m_new, M_DONTWAIT);
1216 if (!(m_new->m_flags & M_EXT)) {
1217 m_freem(m_new);
1218 return (ENOBUFS);
1219 }
1220 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1221 } else {
1222 m_new = m;
1223 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1224 m_new->m_data = m_new->m_ext.ext_buf;
1225 }
1226
1227 m_adj(m_new, ETHER_ALIGN);
1228 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1229 r = &sc->ti_rdata->ti_rx_std_ring[i];
1230 map = sc->ti_cdata.ti_rx_std_maps[i];
1231 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1232 &nsegs, 0))
1233 return (ENOBUFS);
1234 if (nsegs != 1)
1235 return (ENOBUFS);
1236 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1237 r->ti_len = segs.ds_len;
1238 r->ti_type = TI_BDTYPE_RECV_BD;
1239 r->ti_flags = 0;
1240 if (sc->ti_ifp->if_hwassist)
1241 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1242 r->ti_idx = i;
1243
1244 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1245 return (0);
1246}
1247
1248/*
1249 * Intialize a mini receive ring descriptor. This only applies to
1250 * the Tigon 2.
1251 */
1252static int
1253ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
1254{
1255 bus_dma_segment_t segs;
1256 bus_dmamap_t map;
1257 struct mbuf *m_new = NULL;
1258 struct ti_rx_desc *r;
1259 int nsegs;
1260
1261 nsegs = 0;
1262 if (m == NULL) {
1263 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1264 if (m_new == NULL) {
1265 return (ENOBUFS);
1266 }
1267 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1268 } else {
1269 m_new = m;
1270 m_new->m_data = m_new->m_pktdat;
1271 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1272 }
1273
1274 m_adj(m_new, ETHER_ALIGN);
1275 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1276 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1277 map = sc->ti_cdata.ti_rx_mini_maps[i];
1278 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1279 &nsegs, 0))
1280 return (ENOBUFS);
1281 if (nsegs != 1)
1282 return (ENOBUFS);
1283 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1284 r->ti_len = segs.ds_len;
1285 r->ti_type = TI_BDTYPE_RECV_BD;
1286 r->ti_flags = TI_BDFLAG_MINI_RING;
1287 if (sc->ti_ifp->if_hwassist)
1288 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1289 r->ti_idx = i;
1290
1291 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1292 return (0);
1293}
1294
1295#ifdef TI_PRIVATE_JUMBOS
1296
1297/*
1298 * Initialize a jumbo receive ring descriptor. This allocates
1299 * a jumbo buffer from the pool managed internally by the driver.
1300 */
1301static int
1302ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
1303{
1304 bus_dmamap_t map;
1305 struct mbuf *m_new = NULL;
1306 struct ti_rx_desc *r;
1307 int nsegs;
1308 bus_dma_segment_t segs;
1309
1310 if (m == NULL) {
1311 caddr_t *buf = NULL;
1312
1313 /* Allocate the mbuf. */
1314 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1315 if (m_new == NULL) {
1316 return (ENOBUFS);
1317 }
1318
1319 /* Allocate the jumbo buffer */
1320 buf = ti_jalloc(sc);
1321 if (buf == NULL) {
1322 m_freem(m_new);
1323 device_printf(sc->ti_dev, "jumbo allocation failed "
1324 "-- packet dropped!\n");
1325 return (ENOBUFS);
1326 }
1327
1328 /* Attach the buffer to the mbuf. */
1329 m_new->m_data = (void *) buf;
1330 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1331 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf,
1332 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1333 } else {
1334 m_new = m;
1335 m_new->m_data = m_new->m_ext.ext_buf;
1336 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1337 }
1338
1339 m_adj(m_new, ETHER_ALIGN);
1340 /* Set up the descriptor. */
1341 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1342 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1343 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1344 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1345 &nsegs, 0))
1346 return (ENOBUFS);
1347 if (nsegs != 1)
1348 return (ENOBUFS);
1349 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1350 r->ti_len = segs.ds_len;
1351 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1352 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1353 if (sc->ti_ifp->if_hwassist)
1354 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1355 r->ti_idx = i;
1356
1357 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1358 return (0);
1359}
1360
1361#else
1362
1363#if (PAGE_SIZE == 4096)
1364#define NPAYLOAD 2
1365#else
1366#define NPAYLOAD 1
1367#endif
1368
1369#define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1370#define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1371#define NFS_HDR_LEN (UDP_HDR_LEN)
1372static int HDR_LEN = TCP_HDR_LEN;
1373
1374/*
1375 * Initialize a jumbo receive ring descriptor. This allocates
1376 * a jumbo buffer from the pool managed internally by the driver.
1377 */
1378static int
1379ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1380{
1381 bus_dmamap_t map;
1382 struct mbuf *cur, *m_new = NULL;
1383 struct mbuf *m[3] = {NULL, NULL, NULL};
1384 struct ti_rx_desc_ext *r;
1385 vm_page_t frame;
1386 static int color;
1387 /* 1 extra buf to make nobufs easy*/
1388 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1389 int i;
1390 bus_dma_segment_t segs[4];
1391 int nsegs;
1392
1393 if (m_old != NULL) {
1394 m_new = m_old;
1395 cur = m_old->m_next;
1396 for (i = 0; i <= NPAYLOAD; i++){
1397 m[i] = cur;
1398 cur = cur->m_next;
1399 }
1400 } else {
1401 /* Allocate the mbufs. */
1402 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1403 if (m_new == NULL) {
1404 device_printf(sc->ti_dev, "mbuf allocation failed "
1405 "-- packet dropped!\n");
1406 goto nobufs;
1407 }
1408 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1409 if (m[NPAYLOAD] == NULL) {
1410 device_printf(sc->ti_dev, "cluster mbuf allocation "
1411 "failed -- packet dropped!\n");
1412 goto nobufs;
1413 }
1414 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1415 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1416 device_printf(sc->ti_dev, "mbuf allocation failed "
1417 "-- packet dropped!\n");
1418 goto nobufs;
1419 }
1420 m[NPAYLOAD]->m_len = MCLBYTES;
1421
1422 for (i = 0; i < NPAYLOAD; i++){
1423 MGET(m[i], M_DONTWAIT, MT_DATA);
1424 if (m[i] == NULL) {
1425 device_printf(sc->ti_dev, "mbuf allocation "
1426 "failed -- packet dropped!\n");
1427 goto nobufs;
1428 }
1429 frame = vm_page_alloc(NULL, color++,
1430 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1431 VM_ALLOC_WIRED);
1432 if (frame == NULL) {
1433 device_printf(sc->ti_dev, "buffer allocation "
1434 "failed -- packet dropped!\n");
1435 printf(" index %d page %d\n", idx, i);
1436 goto nobufs;
1437 }
1438 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1439 if (sf[i] == NULL) {
1440 vm_page_unwire(frame, 0);
1441 vm_page_free(frame);
1442 device_printf(sc->ti_dev, "buffer allocation "
1443 "failed -- packet dropped!\n");
1444 printf(" index %d page %d\n", idx, i);
1445 goto nobufs;
1446 }
1447 }
1448 for (i = 0; i < NPAYLOAD; i++){
1449 /* Attach the buffer to the mbuf. */
1450 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1451 m[i]->m_len = PAGE_SIZE;
1452 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1453 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1454 0, EXT_DISPOSABLE);
1455 m[i]->m_next = m[i+1];
1456 }
1457 /* link the buffers to the header */
1458 m_new->m_next = m[0];
1459 m_new->m_data += ETHER_ALIGN;
1460 if (sc->ti_hdrsplit)
1461 m_new->m_len = MHLEN - ETHER_ALIGN;
1462 else
1463 m_new->m_len = HDR_LEN;
1464 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1465 }
1466
1467 /* Set up the descriptor. */
1468 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1469 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1470 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1471 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1472 &nsegs, 0))
1473 return (ENOBUFS);
1474 if ((nsegs < 1) || (nsegs > 4))
1475 return (ENOBUFS);
1476 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1477 r->ti_len0 = m_new->m_len;
1478
1479 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1480 r->ti_len1 = PAGE_SIZE;
1481
1482 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1483 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1484
1485 if (PAGE_SIZE == 4096) {
1486 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1487 r->ti_len3 = MCLBYTES;
1488 } else {
1489 r->ti_len3 = 0;
1490 }
1491 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1492
1493 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1494
1495 if (sc->ti_ifp->if_hwassist)
1496 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1497
1498 r->ti_idx = idx;
1499
1500 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1501 return (0);
1502
1503nobufs:
1504
1505 /*
1506 * Warning! :
1507 * This can only be called before the mbufs are strung together.
1508 * If the mbufs are strung together, m_freem() will free the chain,
1509 * so that the later mbufs will be freed multiple times.
1510 */
1511 if (m_new)
1512 m_freem(m_new);
1513
1514 for (i = 0; i < 3; i++) {
1515 if (m[i])
1516 m_freem(m[i]);
1517 if (sf[i])
1518 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1519 }
1520 return (ENOBUFS);
1521}
1522#endif
1523
1524/*
1525 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1526 * that's 1MB or memory, which is a lot. For now, we fill only the first
1527 * 256 ring entries and hope that our CPU is fast enough to keep up with
1528 * the NIC.
1529 */
1530static int
1531ti_init_rx_ring_std(struct ti_softc *sc)
1532{
1533 int i;
1534 struct ti_cmd_desc cmd;
1535
1536 for (i = 0; i < TI_SSLOTS; i++) {
1537 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1538 return (ENOBUFS);
1539 };
1540
1541 TI_UPDATE_STDPROD(sc, i - 1);
1542 sc->ti_std = i - 1;
1543
1544 return (0);
1545}
1546
1547static void
1548ti_free_rx_ring_std(struct ti_softc *sc)
1549{
1550 bus_dmamap_t map;
1551 int i;
1552
1553 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1554 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1555 map = sc->ti_cdata.ti_rx_std_maps[i];
1556 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1557 BUS_DMASYNC_POSTREAD);
1558 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1559 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1560 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1561 }
1562 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1563 sizeof(struct ti_rx_desc));
1564 }
1565}
1566
1567static int
1568ti_init_rx_ring_jumbo(struct ti_softc *sc)
1569{
1570 struct ti_cmd_desc cmd;
1571 int i;
1572
1573 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1574 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1575 return (ENOBUFS);
1576 };
1577
1578 TI_UPDATE_JUMBOPROD(sc, i - 1);
1579 sc->ti_jumbo = i - 1;
1580
1581 return (0);
1582}
1583
1584static void
1585ti_free_rx_ring_jumbo(struct ti_softc *sc)
1586{
1587 bus_dmamap_t map;
1588 int i;
1589
1590 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1591 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1592 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1593 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1594 BUS_DMASYNC_POSTREAD);
1595 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1596 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1597 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1598 }
1599 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1600 sizeof(struct ti_rx_desc));
1601 }
1602}
1603
1604static int
1605ti_init_rx_ring_mini(struct ti_softc *sc)
1606{
1607 int i;
1608
1609 for (i = 0; i < TI_MSLOTS; i++) {
1610 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1611 return (ENOBUFS);
1612 };
1613
1614 TI_UPDATE_MINIPROD(sc, i - 1);
1615 sc->ti_mini = i - 1;
1616
1617 return (0);
1618}
1619
1620static void
1621ti_free_rx_ring_mini(struct ti_softc *sc)
1622{
1623 bus_dmamap_t map;
1624 int i;
1625
1626 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1627 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1628 map = sc->ti_cdata.ti_rx_mini_maps[i];
1629 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1630 BUS_DMASYNC_POSTREAD);
1631 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1632 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1633 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1634 }
1635 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1636 sizeof(struct ti_rx_desc));
1637 }
1638}
1639
1640static void
1641ti_free_tx_ring(struct ti_softc *sc)
1642{
1643 struct ti_txdesc *txd;
1644 int i;
1645
1646 if (sc->ti_rdata->ti_tx_ring == NULL)
1647 return;
1648
1649 for (i = 0; i < TI_TX_RING_CNT; i++) {
1650 txd = &sc->ti_cdata.ti_txdesc[i];
1651 if (txd->tx_m != NULL) {
1652 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1653 BUS_DMASYNC_POSTWRITE);
1654 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1655 m_freem(txd->tx_m);
1656 txd->tx_m = NULL;
1657 }
1658 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1659 sizeof(struct ti_tx_desc));
1660 }
1661}
1662
1663static int
1664ti_init_tx_ring(struct ti_softc *sc)
1665{
1666 struct ti_txdesc *txd;
1667 int i;
1668
1669 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1670 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1671 for (i = 0; i < TI_TX_RING_CNT; i++) {
1672 txd = &sc->ti_cdata.ti_txdesc[i];
1673 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1674 }
1675 sc->ti_txcnt = 0;
1676 sc->ti_tx_saved_considx = 0;
1677 sc->ti_tx_saved_prodidx = 0;
1678 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1679 return (0);
1680}
1681
1682/*
1683 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1684 * but we have to support the old way too so that Tigon 1 cards will
1685 * work.
1686 */
1687static void
1688ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1689{
1690 struct ti_cmd_desc cmd;
1691 uint16_t *m;
1692 uint32_t ext[2] = {0, 0};
1693
1694 m = (uint16_t *)&addr->octet[0];
1695
1696 switch (sc->ti_hwrev) {
1697 case TI_HWREV_TIGON:
1698 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1699 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1700 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1701 break;
1702 case TI_HWREV_TIGON_II:
1703 ext[0] = htons(m[0]);
1704 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1705 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1706 break;
1707 default:
1708 device_printf(sc->ti_dev, "unknown hwrev\n");
1709 break;
1710 }
1711}
1712
1713static void
1714ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1715{
1716 struct ti_cmd_desc cmd;
1717 uint16_t *m;
1718 uint32_t ext[2] = {0, 0};
1719
1720 m = (uint16_t *)&addr->octet[0];
1721
1722 switch (sc->ti_hwrev) {
1723 case TI_HWREV_TIGON:
1724 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1725 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1726 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1727 break;
1728 case TI_HWREV_TIGON_II:
1729 ext[0] = htons(m[0]);
1730 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1731 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1732 break;
1733 default:
1734 device_printf(sc->ti_dev, "unknown hwrev\n");
1735 break;
1736 }
1737}
1738
1739/*
1740 * Configure the Tigon's multicast address filter.
1741 *
1742 * The actual multicast table management is a bit of a pain, thanks to
1743 * slight brain damage on the part of both Alteon and us. With our
1744 * multicast code, we are only alerted when the multicast address table
1745 * changes and at that point we only have the current list of addresses:
1746 * we only know the current state, not the previous state, so we don't
1747 * actually know what addresses were removed or added. The firmware has
1748 * state, but we can't get our grubby mits on it, and there is no 'delete
1749 * all multicast addresses' command. Hence, we have to maintain our own
1750 * state so we know what addresses have been programmed into the NIC at
1751 * any given time.
1752 */
1753static void
1754ti_setmulti(struct ti_softc *sc)
1755{
1756 struct ifnet *ifp;
1757 struct ifmultiaddr *ifma;
1758 struct ti_cmd_desc cmd;
1759 struct ti_mc_entry *mc;
1760 uint32_t intrs;
1761
1762 TI_LOCK_ASSERT(sc);
1763
1764 ifp = sc->ti_ifp;
1765
1766 if (ifp->if_flags & IFF_ALLMULTI) {
1767 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1768 return;
1769 } else {
1770 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1771 }
1772
1773 /* Disable interrupts. */
1774 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1775 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1776
1777 /* First, zot all the existing filters. */
1778 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1779 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1780 ti_del_mcast(sc, &mc->mc_addr);
1781 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1782 free(mc, M_DEVBUF);
1783 }
1784
1785 /* Now program new ones. */
1786 if_maddr_rlock(ifp);
1787 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1788 if (ifma->ifma_addr->sa_family != AF_LINK)
1789 continue;
1790 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1791 if (mc == NULL) {
1792 device_printf(sc->ti_dev,
1793 "no memory for mcast filter entry\n");
1794 continue;
1795 }
1796 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1797 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1798 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1799 ti_add_mcast(sc, &mc->mc_addr);
1800 }
1801 if_maddr_runlock(ifp);
1802
1803 /* Re-enable interrupts. */
1804 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1805}
1806
1807/*
1808 * Check to see if the BIOS has configured us for a 64 bit slot when
1809 * we aren't actually in one. If we detect this condition, we can work
1810 * around it on the Tigon 2 by setting a bit in the PCI state register,
1811 * but for the Tigon 1 we must give up and abort the interface attach.
1812 */
1813static int ti_64bitslot_war(struct ti_softc *sc)
1814{
1815
1816 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1817 CSR_WRITE_4(sc, 0x600, 0);
1818 CSR_WRITE_4(sc, 0x604, 0);
1819 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1820 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1821 if (sc->ti_hwrev == TI_HWREV_TIGON)
1822 return (EINVAL);
1823 else {
1824 TI_SETBIT(sc, TI_PCI_STATE,
1825 TI_PCISTATE_32BIT_BUS);
1826 return (0);
1827 }
1828 }
1829 }
1830
1831 return (0);
1832}
1833
1834/*
1835 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1836 * self-test results.
1837 */
1838static int
1839ti_chipinit(struct ti_softc *sc)
1840{
1841 uint32_t cacheline;
1842 uint32_t pci_writemax = 0;
1843 uint32_t hdrsplit;
1844
1845 /* Initialize link to down state. */
1846 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1847
1848 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1849 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1850 else
1851 sc->ti_ifp->if_hwassist = 0;
1852
1853 /* Set endianness before we access any non-PCI registers. */
1854#if 0 && BYTE_ORDER == BIG_ENDIAN
1855 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1856 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1857#else
1858 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1859 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1860#endif
1861
1862 /* Check the ROM failed bit to see if self-tests passed. */
1863 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1864 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1865 return (ENODEV);
1866 }
1867
1868 /* Halt the CPU. */
1869 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1870
1871 /* Figure out the hardware revision. */
1872 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1873 case TI_REV_TIGON_I:
1874 sc->ti_hwrev = TI_HWREV_TIGON;
1875 break;
1876 case TI_REV_TIGON_II:
1877 sc->ti_hwrev = TI_HWREV_TIGON_II;
1878 break;
1879 default:
1880 device_printf(sc->ti_dev, "unsupported chip revision\n");
1881 return (ENODEV);
1882 }
1883
1884 /* Do special setup for Tigon 2. */
1885 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1886 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1887 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1888 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1889 }
1890
1891 /*
1892 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1893 * can't do header splitting.
1894 */
1895#ifdef TI_JUMBO_HDRSPLIT
1896 if (sc->ti_hwrev != TI_HWREV_TIGON)
1897 sc->ti_hdrsplit = 1;
1898 else
1899 device_printf(sc->ti_dev,
1900 "can't do header splitting on a Tigon I board\n");
1901#endif /* TI_JUMBO_HDRSPLIT */
1902
1903 /* Set up the PCI state register. */
1904 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1905 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1906 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1907 }
1908
1909 /* Clear the read/write max DMA parameters. */
1910 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1911 TI_PCISTATE_READ_MAXDMA));
1912
1913 /* Get cache line size. */
1914 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1915
1916 /*
1917 * If the system has set enabled the PCI memory write
1918 * and invalidate command in the command register, set
1919 * the write max parameter accordingly. This is necessary
1920 * to use MWI with the Tigon 2.
1921 */
1922 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1923 switch (cacheline) {
1924 case 1:
1925 case 4:
1926 case 8:
1927 case 16:
1928 case 32:
1929 case 64:
1930 break;
1931 default:
1932 /* Disable PCI memory write and invalidate. */
1933 if (bootverbose)
1934 device_printf(sc->ti_dev, "cache line size %d"
1935 " not supported; disabling PCI MWI\n",
1936 cacheline);
1937 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1938 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1939 break;
1940 }
1941 }
1942
1943 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1944
1945 /* This sets the min dma param all the way up (0xff). */
1946 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1947
1948 if (sc->ti_hdrsplit)
1949 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1950 else
1951 hdrsplit = 0;
1952
1953 /* Configure DMA variables. */
1954#if BYTE_ORDER == BIG_ENDIAN
1955 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1956 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1957 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1958 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1959#else /* BYTE_ORDER */
1960 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1961 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1962 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1963#endif /* BYTE_ORDER */
1964
1965 /*
1966 * Only allow 1 DMA channel to be active at a time.
1967 * I don't think this is a good idea, but without it
1968 * the firmware racks up lots of nicDmaReadRingFull
1969 * errors. This is not compatible with hardware checksums.
1970 */
1971 if (sc->ti_ifp->if_hwassist == 0)
1972 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1973
1974 /* Recommended settings from Tigon manual. */
1975 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1976 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1977
1978 if (ti_64bitslot_war(sc)) {
1979 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
1980 "but we aren't");
1981 return (EINVAL);
1982 }
1983
1984 return (0);
1985}
1986
1987/*
1988 * Initialize the general information block and firmware, and
1989 * start the CPU(s) running.
1990 */
1991static int
1992ti_gibinit(struct ti_softc *sc)
1993{
1994 struct ifnet *ifp;
1995 struct ti_rcb *rcb;
1996 uint32_t rdphys;
1997 int i;
1998
1999 TI_LOCK_ASSERT(sc);
2000
2001 ifp = sc->ti_ifp;
2002 rdphys = sc->ti_rdata_phys;
2003
2004 /* Disable interrupts for now. */
2005 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2006
2007 /*
2008 * Tell the chip where to find the general information block.
2009 * While this struct could go into >4GB memory, we allocate it in a
2010 * single slab with the other descriptors, and those don't seem to
2011 * support being located in a 64-bit region.
2012 */
2013 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2014 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2015
2016 /* Load the firmware into SRAM. */
2017 ti_loadfw(sc);
2018
2019 /* Set up the contents of the general info and ring control blocks. */
2020
2021 /* Set up the event ring and producer pointer. */
2022 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2023
2024 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2025 rcb->ti_flags = 0;
2026 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2027 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2028 sc->ti_ev_prodidx.ti_idx = 0;
2029 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2030 sc->ti_ev_saved_considx = 0;
2031
2032 /* Set up the command ring and producer mailbox. */
2033 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2034
2035 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2036 rcb->ti_flags = 0;
2037 rcb->ti_max_len = 0;
2038 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2039 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2040 }
2041 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2042 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2043 sc->ti_cmd_saved_prodidx = 0;
2044
2045 /*
2046 * Assign the address of the stats refresh buffer.
2047 * We re-use the current stats buffer for this to
2048 * conserve memory.
2049 */
2050 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2051 rdphys + TI_RD_OFF(ti_info.ti_stats);
2052
2053 /* Set up the standard receive ring. */
2054 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2055 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2056 rcb->ti_max_len = TI_FRAMELEN;
2057 rcb->ti_flags = 0;
2058 if (sc->ti_ifp->if_hwassist)
2059 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2060 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2061 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2062
2063 /* Set up the jumbo receive ring. */
2064 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2065 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2066
2067#ifdef TI_PRIVATE_JUMBOS
2068 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2069 rcb->ti_flags = 0;
2070#else
2071 rcb->ti_max_len = PAGE_SIZE;
2072 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2073#endif
2074 if (sc->ti_ifp->if_hwassist)
2075 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2076 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2077 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2078
2079 /*
2080 * Set up the mini ring. Only activated on the
2081 * Tigon 2 but the slot in the config block is
2082 * still there on the Tigon 1.
2083 */
2084 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2085 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2086 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2087 if (sc->ti_hwrev == TI_HWREV_TIGON)
2088 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2089 else
2090 rcb->ti_flags = 0;
2091 if (sc->ti_ifp->if_hwassist)
2092 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2093 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2094 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2095
2096 /*
2097 * Set up the receive return ring.
2098 */
2099 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2100 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2101 rcb->ti_flags = 0;
2102 rcb->ti_max_len = TI_RETURN_RING_CNT;
2103 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2104 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2105
2106 /*
2107 * Set up the tx ring. Note: for the Tigon 2, we have the option
2108 * of putting the transmit ring in the host's address space and
2109 * letting the chip DMA it instead of leaving the ring in the NIC's
2110 * memory and accessing it through the shared memory region. We
2111 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2112 * so we have to revert to the shared memory scheme if we detect
2113 * a Tigon 1 chip.
2114 */
2115 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2116 bzero((char *)sc->ti_rdata->ti_tx_ring,
2117 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2118 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2119 if (sc->ti_hwrev == TI_HWREV_TIGON)
2120 rcb->ti_flags = 0;
2121 else
2122 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2123 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2124 if (sc->ti_ifp->if_hwassist)
2125 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2126 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2127 rcb->ti_max_len = TI_TX_RING_CNT;
2128 if (sc->ti_hwrev == TI_HWREV_TIGON)
2129 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2130 else
2131 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2132 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2133 rdphys + TI_RD_OFF(ti_tx_considx_r);
2134
2135 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2136 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2137
2138 /* Set up tuneables */
2139#if 0
2140 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2141 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2142 (sc->ti_rx_coal_ticks / 10));
2143 else
2144#endif
2145 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2146 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2147 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2148 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2149 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2150 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2151
2152 /* Turn interrupts on. */
2153 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2154 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2155
2156 /* Start CPU. */
2157 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2158
2159 return (0);
2160}
2161
2162static void
2163ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2164{
2165 struct ti_softc *sc;
2166
2167 sc = arg;
2168 if (error || nseg != 1)
2169 return;
2170
2171 /*
2172 * All of the Tigon data structures need to live at <4GB. This
2173 * cast is fine since busdma was told about this constraint.
2174 */
2175 sc->ti_rdata_phys = segs[0].ds_addr;
2176 return;
2177}
2178
2179/*
2180 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2181 * against our list and return its name if we find a match.
2182 */
2183static int
2184ti_probe(device_t dev)
2185{
2186 const struct ti_type *t;
2187
2188 t = ti_devs;
2189
2190 while (t->ti_name != NULL) {
2191 if ((pci_get_vendor(dev) == t->ti_vid) &&
2192 (pci_get_device(dev) == t->ti_did)) {
2193 device_set_desc(dev, t->ti_name);
2194 return (BUS_PROBE_DEFAULT);
2195 }
2196 t++;
2197 }
2198
2199 return (ENXIO);
2200}
2201
2202static int
2203ti_attach(device_t dev)
2204{
2205 struct ifnet *ifp;
2206 struct ti_softc *sc;
2207 int error = 0, rid;
2208 u_char eaddr[6];
2209
2210 sc = device_get_softc(dev);
2211 sc->ti_unit = device_get_unit(dev);
2212 sc->ti_dev = dev;
2213
2214 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2215 MTX_DEF);
2216 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2217 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2218 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2219 if (ifp == NULL) {
2220 device_printf(dev, "can not if_alloc()\n");
2221 error = ENOSPC;
2222 goto fail;
2223 }
2224 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2225 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2226 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2227
2228 /*
2229 * Map control/status registers.
2230 */
2231 pci_enable_busmaster(dev);
2232
2233 rid = TI_PCI_LOMEM;
2234 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2235 RF_ACTIVE);
2236
2237 if (sc->ti_res == NULL) {
2238 device_printf(dev, "couldn't map memory\n");
2239 error = ENXIO;
2240 goto fail;
2241 }
2242
2243 sc->ti_btag = rman_get_bustag(sc->ti_res);
2244 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2245
2246 /* Allocate interrupt */
2247 rid = 0;
2248
2249 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2250 RF_SHAREABLE | RF_ACTIVE);
2251
2252 if (sc->ti_irq == NULL) {
2253 device_printf(dev, "couldn't map interrupt\n");
2254 error = ENXIO;
2255 goto fail;
2256 }
2257
2258 if (ti_chipinit(sc)) {
2259 device_printf(dev, "chip initialization failed\n");
2260 error = ENXIO;
2261 goto fail;
2262 }
2263
2264 /* Zero out the NIC's on-board SRAM. */
2265 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2266
2267 /* Init again -- zeroing memory may have clobbered some registers. */
2268 if (ti_chipinit(sc)) {
2269 device_printf(dev, "chip initialization failed\n");
2270 error = ENXIO;
2271 goto fail;
2272 }
2273
2274 /*
2275 * Get station address from the EEPROM. Note: the manual states
2276 * that the MAC address is at offset 0x8c, however the data is
2277 * stored as two longwords (since that's how it's loaded into
2278 * the NIC). This means the MAC address is actually preceded
2279 * by two zero bytes. We need to skip over those.
2280 */
2281 if (ti_read_eeprom(sc, eaddr,
2282 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2283 device_printf(dev, "failed to read station address\n");
2284 error = ENXIO;
2285 goto fail;
2286 }
2287
2288 /* Allocate the general information block and ring buffers. */
2289 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2290 1, 0, /* algnmnt, boundary */
2291 BUS_SPACE_MAXADDR, /* lowaddr */
2292 BUS_SPACE_MAXADDR, /* highaddr */
2293 NULL, NULL, /* filter, filterarg */
2294 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2295 0, /* nsegments */
2296 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2297 0, /* flags */
2298 NULL, NULL, /* lockfunc, lockarg */
2299 &sc->ti_parent_dmat) != 0) {
2300 device_printf(dev, "Failed to allocate parent dmat\n");
2301 error = ENOMEM;
2302 goto fail;
2303 }
2304
2305 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2306 PAGE_SIZE, 0, /* algnmnt, boundary */
2307 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2308 BUS_SPACE_MAXADDR, /* highaddr */
2309 NULL, NULL, /* filter, filterarg */
2310 sizeof(struct ti_ring_data), /* maxsize */
2311 1, /* nsegments */
2312 sizeof(struct ti_ring_data), /* maxsegsize */
2313 0, /* flags */
2314 NULL, NULL, /* lockfunc, lockarg */
2315 &sc->ti_rdata_dmat) != 0) {
2316 device_printf(dev, "Failed to allocate rdata dmat\n");
2317 error = ENOMEM;
2318 goto fail;
2319 }
2320
2321 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2322 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2323 &sc->ti_rdata_dmamap) != 0) {
2324 device_printf(dev, "Failed to allocate rdata memory\n");
2325 error = ENOMEM;
2326 goto fail;
2327 }
2328
2329 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2330 sc->ti_rdata, sizeof(struct ti_ring_data),
2331 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2332 device_printf(dev, "Failed to load rdata segments\n");
2333 error = ENOMEM;
2334 goto fail;
2335 }
2336
2337 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2338
2339 /* Try to allocate memory for jumbo buffers. */
2340 if (ti_alloc_jumbo_mem(sc)) {
2341 device_printf(dev, "jumbo buffer allocation failed\n");
2342 error = ENXIO;
2343 goto fail;
2344 }
2345
2346 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2347 1, 0, /* algnmnt, boundary */
2348 BUS_SPACE_MAXADDR, /* lowaddr */
2349 BUS_SPACE_MAXADDR, /* highaddr */
2350 NULL, NULL, /* filter, filterarg */
2351 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2352 TI_MAXTXSEGS, /* nsegments */
2353 MCLBYTES, /* maxsegsize */
2354 0, /* flags */
2355 NULL, NULL, /* lockfunc, lockarg */
2356 &sc->ti_mbuftx_dmat) != 0) {
2357 device_printf(dev, "Failed to allocate rdata dmat\n");
2358 error = ENOMEM;
2359 goto fail;
2360 }
2361
2362 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2363 1, 0, /* algnmnt, boundary */
2364 BUS_SPACE_MAXADDR, /* lowaddr */
2365 BUS_SPACE_MAXADDR, /* highaddr */
2366 NULL, NULL, /* filter, filterarg */
2367 MCLBYTES, /* maxsize */
2368 1, /* nsegments */
2369 MCLBYTES, /* maxsegsize */
2370 0, /* flags */
2371 NULL, NULL, /* lockfunc, lockarg */
2372 &sc->ti_mbufrx_dmat) != 0) {
2373 device_printf(dev, "Failed to allocate rdata dmat\n");
2374 error = ENOMEM;
2375 goto fail;
2376 }
2377
2378 if (ti_alloc_dmamaps(sc)) {
2379 device_printf(dev, "dma map creation failed\n");
2380 error = ENXIO;
2381 goto fail;
2382 }
2383
2384 /*
2385 * We really need a better way to tell a 1000baseTX card
2386 * from a 1000baseSX one, since in theory there could be
2387 * OEMed 1000baseTX cards from lame vendors who aren't
2388 * clever enough to change the PCI ID. For the moment
2389 * though, the AceNIC is the only copper card available.
2390 */
2391 if (pci_get_vendor(dev) == ALT_VENDORID &&
2392 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2393 sc->ti_copper = 1;
2394 /* Ok, it's not the only copper card available. */
2395 if (pci_get_vendor(dev) == NG_VENDORID &&
2396 pci_get_device(dev) == NG_DEVICEID_GA620T)
2397 sc->ti_copper = 1;
2398
2399 /* Set default tuneable values. */
2400 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2401#if 0
2402 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2403#endif
2404 sc->ti_rx_coal_ticks = 170;
2405 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2406 sc->ti_rx_max_coal_bds = 64;
2407#if 0
2408 sc->ti_tx_max_coal_bds = 128;
2409#endif
2410 sc->ti_tx_max_coal_bds = 32;
2411 sc->ti_tx_buf_ratio = 21;
2412
2413 /* Set up ifnet structure */
2414 ifp->if_softc = sc;
2415 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2417 ifp->if_ioctl = ti_ioctl;
2418 ifp->if_start = ti_start;
2419 ifp->if_init = ti_init;
| 947 break;
948 case TI_EV_ERROR:
949 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
950 device_printf(sc->ti_dev, "invalid command\n");
951 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
952 device_printf(sc->ti_dev, "unknown command\n");
953 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
954 device_printf(sc->ti_dev, "bad config data\n");
955 break;
956 case TI_EV_FIRMWARE_UP:
957 ti_init2(sc);
958 break;
959 case TI_EV_STATS_UPDATED:
960 ti_stats_update(sc);
961 break;
962 case TI_EV_RESET_JUMBO_RING:
963 case TI_EV_MCAST_UPDATED:
964 /* Who cares. */
965 break;
966 default:
967 device_printf(sc->ti_dev, "unknown event: %d\n",
968 TI_EVENT_EVENT(e));
969 break;
970 }
971 /* Advance the consumer index. */
972 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
973 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
974 }
975}
976
977static int
978ti_alloc_dmamaps(struct ti_softc *sc)
979{
980 int i;
981
982 for (i = 0; i < TI_TX_RING_CNT; i++) {
983 sc->ti_cdata.ti_txdesc[i].tx_m = NULL;
984 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
985 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0,
986 &sc->ti_cdata.ti_txdesc[i].tx_dmamap))
987 return (ENOBUFS);
988 }
989 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
990 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
991 &sc->ti_cdata.ti_rx_std_maps[i]))
992 return (ENOBUFS);
993 }
994
995 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
996 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0,
997 &sc->ti_cdata.ti_rx_jumbo_maps[i]))
998 return (ENOBUFS);
999 }
1000 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1001 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0,
1002 &sc->ti_cdata.ti_rx_mini_maps[i]))
1003 return (ENOBUFS);
1004 }
1005
1006 return (0);
1007}
1008
1009static void
1010ti_free_dmamaps(struct ti_softc *sc)
1011{
1012 int i;
1013
1014 if (sc->ti_mbuftx_dmat)
1015 for (i = 0; i < TI_TX_RING_CNT; i++)
1016 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1017 bus_dmamap_destroy(sc->ti_mbuftx_dmat,
1018 sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1019 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0;
1020 }
1021
1022 if (sc->ti_mbufrx_dmat)
1023 for (i = 0; i < TI_STD_RX_RING_CNT; i++)
1024 if (sc->ti_cdata.ti_rx_std_maps[i]) {
1025 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1026 sc->ti_cdata.ti_rx_std_maps[i]);
1027 sc->ti_cdata.ti_rx_std_maps[i] = 0;
1028 }
1029
1030 if (sc->ti_jumbo_dmat)
1031 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++)
1032 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1033 bus_dmamap_destroy(sc->ti_jumbo_dmat,
1034 sc->ti_cdata.ti_rx_jumbo_maps[i]);
1035 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0;
1036 }
1037 if (sc->ti_mbufrx_dmat)
1038 for (i = 0; i < TI_MINI_RX_RING_CNT; i++)
1039 if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1040 bus_dmamap_destroy(sc->ti_mbufrx_dmat,
1041 sc->ti_cdata.ti_rx_mini_maps[i]);
1042 sc->ti_cdata.ti_rx_mini_maps[i] = 0;
1043 }
1044}
1045
1046#ifdef TI_PRIVATE_JUMBOS
1047
1048/*
1049 * Memory management for the jumbo receive ring is a pain in the
1050 * butt. We need to allocate at least 9018 bytes of space per frame,
1051 * _and_ it has to be contiguous (unless you use the extended
1052 * jumbo descriptor format). Using malloc() all the time won't
1053 * work: malloc() allocates memory in powers of two, which means we
1054 * would end up wasting a considerable amount of space by allocating
1055 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
1056 * to do our own memory management.
1057 *
1058 * The driver needs to allocate a contiguous chunk of memory at boot
1059 * time. We then chop this up ourselves into 9K pieces and use them
1060 * as external mbuf storage.
1061 *
1062 * One issue here is how much memory to allocate. The jumbo ring has
1063 * 256 slots in it, but at 9K per slot than can consume over 2MB of
1064 * RAM. This is a bit much, especially considering we also need
1065 * RAM for the standard ring and mini ring (on the Tigon 2). To
1066 * save space, we only actually allocate enough memory for 64 slots
1067 * by default, which works out to between 500 and 600K. This can
1068 * be tuned by changing a #define in if_tireg.h.
1069 */
1070
1071static int
1072ti_alloc_jumbo_mem(struct ti_softc *sc)
1073{
1074 struct ti_jpool_entry *entry;
1075 caddr_t ptr;
1076 int i;
1077
1078 /*
1079 * Grab a big chunk o' storage. Since we are chopping this pool up
1080 * into ~9k chunks, there doesn't appear to be a need to use page
1081 * alignment.
1082 */
1083 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1084 1, 0, /* algnmnt, boundary */
1085 BUS_SPACE_MAXADDR, /* lowaddr */
1086 BUS_SPACE_MAXADDR, /* highaddr */
1087 NULL, NULL, /* filter, filterarg */
1088 TI_JMEM, /* maxsize */
1089 1, /* nsegments */
1090 TI_JMEM, /* maxsegsize */
1091 0, /* flags */
1092 NULL, NULL, /* lockfunc, lockarg */
1093 &sc->ti_jumbo_dmat) != 0) {
1094 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1095 return (ENOBUFS);
1096 }
1097
1098 if (bus_dmamem_alloc(sc->ti_jumbo_dmat,
1099 (void**)&sc->ti_cdata.ti_jumbo_buf,
1100 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
1101 &sc->ti_jumbo_dmamap) != 0) {
1102 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n");
1103 return (ENOBUFS);
1104 }
1105
1106 SLIST_INIT(&sc->ti_jfree_listhead);
1107 SLIST_INIT(&sc->ti_jinuse_listhead);
1108
1109 /*
1110 * Now divide it up into 9K pieces and save the addresses
1111 * in an array.
1112 */
1113 ptr = sc->ti_cdata.ti_jumbo_buf;
1114 for (i = 0; i < TI_JSLOTS; i++) {
1115 sc->ti_cdata.ti_jslots[i] = ptr;
1116 ptr += TI_JLEN;
1117 entry = malloc(sizeof(struct ti_jpool_entry),
1118 M_DEVBUF, M_NOWAIT);
1119 if (entry == NULL) {
1120 device_printf(sc->ti_dev, "no memory for jumbo "
1121 "buffer queue!\n");
1122 return (ENOBUFS);
1123 }
1124 entry->slot = i;
1125 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1126 }
1127
1128 return (0);
1129}
1130
1131/*
1132 * Allocate a jumbo buffer.
1133 */
1134static void *ti_jalloc(struct ti_softc *sc)
1135{
1136 struct ti_jpool_entry *entry;
1137
1138 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1139
1140 if (entry == NULL) {
1141 device_printf(sc->ti_dev, "no free jumbo buffers\n");
1142 return (NULL);
1143 }
1144
1145 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1146 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1147 return (sc->ti_cdata.ti_jslots[entry->slot]);
1148}
1149
1150/*
1151 * Release a jumbo buffer.
1152 */
1153static void
1154ti_jfree(void *buf, void *args)
1155{
1156 struct ti_softc *sc;
1157 int i;
1158 struct ti_jpool_entry *entry;
1159
1160 /* Extract the softc struct pointer. */
1161 sc = (struct ti_softc *)args;
1162
1163 if (sc == NULL)
1164 panic("ti_jfree: didn't get softc pointer!");
1165
1166 /* calculate the slot this buffer belongs to */
1167 i = ((vm_offset_t)buf
1168 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1169
1170 if ((i < 0) || (i >= TI_JSLOTS))
1171 panic("ti_jfree: asked to free buffer that we don't manage!");
1172
1173 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1174 if (entry == NULL)
1175 panic("ti_jfree: buffer not in use!");
1176 entry->slot = i;
1177 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1178 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1179}
1180
1181#else
1182
1183static int
1184ti_alloc_jumbo_mem(struct ti_softc *sc)
1185{
1186
1187 /*
1188 * The VM system will take care of providing aligned pages. Alignment
1189 * is set to 1 here so that busdma resources won't be wasted.
1190 */
1191 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
1192 1, 0, /* algnmnt, boundary */
1193 BUS_SPACE_MAXADDR, /* lowaddr */
1194 BUS_SPACE_MAXADDR, /* highaddr */
1195 NULL, NULL, /* filter, filterarg */
1196 PAGE_SIZE * 4 /*XXX*/, /* maxsize */
1197 4, /* nsegments */
1198 PAGE_SIZE, /* maxsegsize */
1199 0, /* flags */
1200 NULL, NULL, /* lockfunc, lockarg */
1201 &sc->ti_jumbo_dmat) != 0) {
1202 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n");
1203 return (ENOBUFS);
1204 }
1205
1206 return (0);
1207}
1208
1209#endif /* TI_PRIVATE_JUMBOS */
1210
1211/*
1212 * Intialize a standard receive ring descriptor.
1213 */
1214static int
1215ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
1216{
1217 bus_dmamap_t map;
1218 bus_dma_segment_t segs;
1219 struct mbuf *m_new = NULL;
1220 struct ti_rx_desc *r;
1221 int nsegs;
1222
1223 nsegs = 0;
1224 if (m == NULL) {
1225 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1226 if (m_new == NULL)
1227 return (ENOBUFS);
1228
1229 MCLGET(m_new, M_DONTWAIT);
1230 if (!(m_new->m_flags & M_EXT)) {
1231 m_freem(m_new);
1232 return (ENOBUFS);
1233 }
1234 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1235 } else {
1236 m_new = m;
1237 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1238 m_new->m_data = m_new->m_ext.ext_buf;
1239 }
1240
1241 m_adj(m_new, ETHER_ALIGN);
1242 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1243 r = &sc->ti_rdata->ti_rx_std_ring[i];
1244 map = sc->ti_cdata.ti_rx_std_maps[i];
1245 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1246 &nsegs, 0))
1247 return (ENOBUFS);
1248 if (nsegs != 1)
1249 return (ENOBUFS);
1250 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1251 r->ti_len = segs.ds_len;
1252 r->ti_type = TI_BDTYPE_RECV_BD;
1253 r->ti_flags = 0;
1254 if (sc->ti_ifp->if_hwassist)
1255 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1256 r->ti_idx = i;
1257
1258 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1259 return (0);
1260}
1261
1262/*
1263 * Intialize a mini receive ring descriptor. This only applies to
1264 * the Tigon 2.
1265 */
1266static int
1267ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
1268{
1269 bus_dma_segment_t segs;
1270 bus_dmamap_t map;
1271 struct mbuf *m_new = NULL;
1272 struct ti_rx_desc *r;
1273 int nsegs;
1274
1275 nsegs = 0;
1276 if (m == NULL) {
1277 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1278 if (m_new == NULL) {
1279 return (ENOBUFS);
1280 }
1281 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1282 } else {
1283 m_new = m;
1284 m_new->m_data = m_new->m_pktdat;
1285 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1286 }
1287
1288 m_adj(m_new, ETHER_ALIGN);
1289 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1290 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1291 map = sc->ti_cdata.ti_rx_mini_maps[i];
1292 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs,
1293 &nsegs, 0))
1294 return (ENOBUFS);
1295 if (nsegs != 1)
1296 return (ENOBUFS);
1297 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1298 r->ti_len = segs.ds_len;
1299 r->ti_type = TI_BDTYPE_RECV_BD;
1300 r->ti_flags = TI_BDFLAG_MINI_RING;
1301 if (sc->ti_ifp->if_hwassist)
1302 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1303 r->ti_idx = i;
1304
1305 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD);
1306 return (0);
1307}
1308
1309#ifdef TI_PRIVATE_JUMBOS
1310
1311/*
1312 * Initialize a jumbo receive ring descriptor. This allocates
1313 * a jumbo buffer from the pool managed internally by the driver.
1314 */
1315static int
1316ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
1317{
1318 bus_dmamap_t map;
1319 struct mbuf *m_new = NULL;
1320 struct ti_rx_desc *r;
1321 int nsegs;
1322 bus_dma_segment_t segs;
1323
1324 if (m == NULL) {
1325 caddr_t *buf = NULL;
1326
1327 /* Allocate the mbuf. */
1328 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1329 if (m_new == NULL) {
1330 return (ENOBUFS);
1331 }
1332
1333 /* Allocate the jumbo buffer */
1334 buf = ti_jalloc(sc);
1335 if (buf == NULL) {
1336 m_freem(m_new);
1337 device_printf(sc->ti_dev, "jumbo allocation failed "
1338 "-- packet dropped!\n");
1339 return (ENOBUFS);
1340 }
1341
1342 /* Attach the buffer to the mbuf. */
1343 m_new->m_data = (void *) buf;
1344 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1345 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, buf,
1346 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1347 } else {
1348 m_new = m;
1349 m_new->m_data = m_new->m_ext.ext_buf;
1350 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1351 }
1352
1353 m_adj(m_new, ETHER_ALIGN);
1354 /* Set up the descriptor. */
1355 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1356 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1357 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1358 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs,
1359 &nsegs, 0))
1360 return (ENOBUFS);
1361 if (nsegs != 1)
1362 return (ENOBUFS);
1363 ti_hostaddr64(&r->ti_addr, segs.ds_addr);
1364 r->ti_len = segs.ds_len;
1365 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1366 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1367 if (sc->ti_ifp->if_hwassist)
1368 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1369 r->ti_idx = i;
1370
1371 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1372 return (0);
1373}
1374
1375#else
1376
1377#if (PAGE_SIZE == 4096)
1378#define NPAYLOAD 2
1379#else
1380#define NPAYLOAD 1
1381#endif
1382
1383#define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1384#define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1385#define NFS_HDR_LEN (UDP_HDR_LEN)
1386static int HDR_LEN = TCP_HDR_LEN;
1387
1388/*
1389 * Initialize a jumbo receive ring descriptor. This allocates
1390 * a jumbo buffer from the pool managed internally by the driver.
1391 */
1392static int
1393ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1394{
1395 bus_dmamap_t map;
1396 struct mbuf *cur, *m_new = NULL;
1397 struct mbuf *m[3] = {NULL, NULL, NULL};
1398 struct ti_rx_desc_ext *r;
1399 vm_page_t frame;
1400 static int color;
1401 /* 1 extra buf to make nobufs easy*/
1402 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1403 int i;
1404 bus_dma_segment_t segs[4];
1405 int nsegs;
1406
1407 if (m_old != NULL) {
1408 m_new = m_old;
1409 cur = m_old->m_next;
1410 for (i = 0; i <= NPAYLOAD; i++){
1411 m[i] = cur;
1412 cur = cur->m_next;
1413 }
1414 } else {
1415 /* Allocate the mbufs. */
1416 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1417 if (m_new == NULL) {
1418 device_printf(sc->ti_dev, "mbuf allocation failed "
1419 "-- packet dropped!\n");
1420 goto nobufs;
1421 }
1422 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1423 if (m[NPAYLOAD] == NULL) {
1424 device_printf(sc->ti_dev, "cluster mbuf allocation "
1425 "failed -- packet dropped!\n");
1426 goto nobufs;
1427 }
1428 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1429 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1430 device_printf(sc->ti_dev, "mbuf allocation failed "
1431 "-- packet dropped!\n");
1432 goto nobufs;
1433 }
1434 m[NPAYLOAD]->m_len = MCLBYTES;
1435
1436 for (i = 0; i < NPAYLOAD; i++){
1437 MGET(m[i], M_DONTWAIT, MT_DATA);
1438 if (m[i] == NULL) {
1439 device_printf(sc->ti_dev, "mbuf allocation "
1440 "failed -- packet dropped!\n");
1441 goto nobufs;
1442 }
1443 frame = vm_page_alloc(NULL, color++,
1444 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1445 VM_ALLOC_WIRED);
1446 if (frame == NULL) {
1447 device_printf(sc->ti_dev, "buffer allocation "
1448 "failed -- packet dropped!\n");
1449 printf(" index %d page %d\n", idx, i);
1450 goto nobufs;
1451 }
1452 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1453 if (sf[i] == NULL) {
1454 vm_page_unwire(frame, 0);
1455 vm_page_free(frame);
1456 device_printf(sc->ti_dev, "buffer allocation "
1457 "failed -- packet dropped!\n");
1458 printf(" index %d page %d\n", idx, i);
1459 goto nobufs;
1460 }
1461 }
1462 for (i = 0; i < NPAYLOAD; i++){
1463 /* Attach the buffer to the mbuf. */
1464 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1465 m[i]->m_len = PAGE_SIZE;
1466 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1467 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1468 0, EXT_DISPOSABLE);
1469 m[i]->m_next = m[i+1];
1470 }
1471 /* link the buffers to the header */
1472 m_new->m_next = m[0];
1473 m_new->m_data += ETHER_ALIGN;
1474 if (sc->ti_hdrsplit)
1475 m_new->m_len = MHLEN - ETHER_ALIGN;
1476 else
1477 m_new->m_len = HDR_LEN;
1478 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1479 }
1480
1481 /* Set up the descriptor. */
1482 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1483 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1484 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1485 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs,
1486 &nsegs, 0))
1487 return (ENOBUFS);
1488 if ((nsegs < 1) || (nsegs > 4))
1489 return (ENOBUFS);
1490 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1491 r->ti_len0 = m_new->m_len;
1492
1493 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1494 r->ti_len1 = PAGE_SIZE;
1495
1496 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1497 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1498
1499 if (PAGE_SIZE == 4096) {
1500 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1501 r->ti_len3 = MCLBYTES;
1502 } else {
1503 r->ti_len3 = 0;
1504 }
1505 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1506
1507 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1508
1509 if (sc->ti_ifp->if_hwassist)
1510 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1511
1512 r->ti_idx = idx;
1513
1514 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD);
1515 return (0);
1516
1517nobufs:
1518
1519 /*
1520 * Warning! :
1521 * This can only be called before the mbufs are strung together.
1522 * If the mbufs are strung together, m_freem() will free the chain,
1523 * so that the later mbufs will be freed multiple times.
1524 */
1525 if (m_new)
1526 m_freem(m_new);
1527
1528 for (i = 0; i < 3; i++) {
1529 if (m[i])
1530 m_freem(m[i]);
1531 if (sf[i])
1532 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1533 }
1534 return (ENOBUFS);
1535}
1536#endif
1537
1538/*
1539 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1540 * that's 1MB or memory, which is a lot. For now, we fill only the first
1541 * 256 ring entries and hope that our CPU is fast enough to keep up with
1542 * the NIC.
1543 */
1544static int
1545ti_init_rx_ring_std(struct ti_softc *sc)
1546{
1547 int i;
1548 struct ti_cmd_desc cmd;
1549
1550 for (i = 0; i < TI_SSLOTS; i++) {
1551 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1552 return (ENOBUFS);
1553 };
1554
1555 TI_UPDATE_STDPROD(sc, i - 1);
1556 sc->ti_std = i - 1;
1557
1558 return (0);
1559}
1560
1561static void
1562ti_free_rx_ring_std(struct ti_softc *sc)
1563{
1564 bus_dmamap_t map;
1565 int i;
1566
1567 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1568 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1569 map = sc->ti_cdata.ti_rx_std_maps[i];
1570 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1571 BUS_DMASYNC_POSTREAD);
1572 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1573 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1574 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1575 }
1576 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1577 sizeof(struct ti_rx_desc));
1578 }
1579}
1580
1581static int
1582ti_init_rx_ring_jumbo(struct ti_softc *sc)
1583{
1584 struct ti_cmd_desc cmd;
1585 int i;
1586
1587 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1588 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1589 return (ENOBUFS);
1590 };
1591
1592 TI_UPDATE_JUMBOPROD(sc, i - 1);
1593 sc->ti_jumbo = i - 1;
1594
1595 return (0);
1596}
1597
1598static void
1599ti_free_rx_ring_jumbo(struct ti_softc *sc)
1600{
1601 bus_dmamap_t map;
1602 int i;
1603
1604 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1605 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1606 map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1607 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
1608 BUS_DMASYNC_POSTREAD);
1609 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
1610 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1611 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1612 }
1613 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1614 sizeof(struct ti_rx_desc));
1615 }
1616}
1617
1618static int
1619ti_init_rx_ring_mini(struct ti_softc *sc)
1620{
1621 int i;
1622
1623 for (i = 0; i < TI_MSLOTS; i++) {
1624 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1625 return (ENOBUFS);
1626 };
1627
1628 TI_UPDATE_MINIPROD(sc, i - 1);
1629 sc->ti_mini = i - 1;
1630
1631 return (0);
1632}
1633
1634static void
1635ti_free_rx_ring_mini(struct ti_softc *sc)
1636{
1637 bus_dmamap_t map;
1638 int i;
1639
1640 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1641 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1642 map = sc->ti_cdata.ti_rx_mini_maps[i];
1643 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
1644 BUS_DMASYNC_POSTREAD);
1645 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
1646 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1647 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1648 }
1649 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1650 sizeof(struct ti_rx_desc));
1651 }
1652}
1653
1654static void
1655ti_free_tx_ring(struct ti_softc *sc)
1656{
1657 struct ti_txdesc *txd;
1658 int i;
1659
1660 if (sc->ti_rdata->ti_tx_ring == NULL)
1661 return;
1662
1663 for (i = 0; i < TI_TX_RING_CNT; i++) {
1664 txd = &sc->ti_cdata.ti_txdesc[i];
1665 if (txd->tx_m != NULL) {
1666 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
1667 BUS_DMASYNC_POSTWRITE);
1668 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
1669 m_freem(txd->tx_m);
1670 txd->tx_m = NULL;
1671 }
1672 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1673 sizeof(struct ti_tx_desc));
1674 }
1675}
1676
1677static int
1678ti_init_tx_ring(struct ti_softc *sc)
1679{
1680 struct ti_txdesc *txd;
1681 int i;
1682
1683 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1684 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1685 for (i = 0; i < TI_TX_RING_CNT; i++) {
1686 txd = &sc->ti_cdata.ti_txdesc[i];
1687 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1688 }
1689 sc->ti_txcnt = 0;
1690 sc->ti_tx_saved_considx = 0;
1691 sc->ti_tx_saved_prodidx = 0;
1692 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1693 return (0);
1694}
1695
1696/*
1697 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1698 * but we have to support the old way too so that Tigon 1 cards will
1699 * work.
1700 */
1701static void
1702ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1703{
1704 struct ti_cmd_desc cmd;
1705 uint16_t *m;
1706 uint32_t ext[2] = {0, 0};
1707
1708 m = (uint16_t *)&addr->octet[0];
1709
1710 switch (sc->ti_hwrev) {
1711 case TI_HWREV_TIGON:
1712 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1713 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1714 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1715 break;
1716 case TI_HWREV_TIGON_II:
1717 ext[0] = htons(m[0]);
1718 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1719 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1720 break;
1721 default:
1722 device_printf(sc->ti_dev, "unknown hwrev\n");
1723 break;
1724 }
1725}
1726
1727static void
1728ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1729{
1730 struct ti_cmd_desc cmd;
1731 uint16_t *m;
1732 uint32_t ext[2] = {0, 0};
1733
1734 m = (uint16_t *)&addr->octet[0];
1735
1736 switch (sc->ti_hwrev) {
1737 case TI_HWREV_TIGON:
1738 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1739 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1740 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1741 break;
1742 case TI_HWREV_TIGON_II:
1743 ext[0] = htons(m[0]);
1744 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1745 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1746 break;
1747 default:
1748 device_printf(sc->ti_dev, "unknown hwrev\n");
1749 break;
1750 }
1751}
1752
1753/*
1754 * Configure the Tigon's multicast address filter.
1755 *
1756 * The actual multicast table management is a bit of a pain, thanks to
1757 * slight brain damage on the part of both Alteon and us. With our
1758 * multicast code, we are only alerted when the multicast address table
1759 * changes and at that point we only have the current list of addresses:
1760 * we only know the current state, not the previous state, so we don't
1761 * actually know what addresses were removed or added. The firmware has
1762 * state, but we can't get our grubby mits on it, and there is no 'delete
1763 * all multicast addresses' command. Hence, we have to maintain our own
1764 * state so we know what addresses have been programmed into the NIC at
1765 * any given time.
1766 */
1767static void
1768ti_setmulti(struct ti_softc *sc)
1769{
1770 struct ifnet *ifp;
1771 struct ifmultiaddr *ifma;
1772 struct ti_cmd_desc cmd;
1773 struct ti_mc_entry *mc;
1774 uint32_t intrs;
1775
1776 TI_LOCK_ASSERT(sc);
1777
1778 ifp = sc->ti_ifp;
1779
1780 if (ifp->if_flags & IFF_ALLMULTI) {
1781 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1782 return;
1783 } else {
1784 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1785 }
1786
1787 /* Disable interrupts. */
1788 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1789 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1790
1791 /* First, zot all the existing filters. */
1792 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1793 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1794 ti_del_mcast(sc, &mc->mc_addr);
1795 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1796 free(mc, M_DEVBUF);
1797 }
1798
1799 /* Now program new ones. */
1800 if_maddr_rlock(ifp);
1801 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1802 if (ifma->ifma_addr->sa_family != AF_LINK)
1803 continue;
1804 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1805 if (mc == NULL) {
1806 device_printf(sc->ti_dev,
1807 "no memory for mcast filter entry\n");
1808 continue;
1809 }
1810 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1811 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1812 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1813 ti_add_mcast(sc, &mc->mc_addr);
1814 }
1815 if_maddr_runlock(ifp);
1816
1817 /* Re-enable interrupts. */
1818 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1819}
1820
1821/*
1822 * Check to see if the BIOS has configured us for a 64 bit slot when
1823 * we aren't actually in one. If we detect this condition, we can work
1824 * around it on the Tigon 2 by setting a bit in the PCI state register,
1825 * but for the Tigon 1 we must give up and abort the interface attach.
1826 */
1827static int ti_64bitslot_war(struct ti_softc *sc)
1828{
1829
1830 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1831 CSR_WRITE_4(sc, 0x600, 0);
1832 CSR_WRITE_4(sc, 0x604, 0);
1833 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1834 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1835 if (sc->ti_hwrev == TI_HWREV_TIGON)
1836 return (EINVAL);
1837 else {
1838 TI_SETBIT(sc, TI_PCI_STATE,
1839 TI_PCISTATE_32BIT_BUS);
1840 return (0);
1841 }
1842 }
1843 }
1844
1845 return (0);
1846}
1847
1848/*
1849 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1850 * self-test results.
1851 */
1852static int
1853ti_chipinit(struct ti_softc *sc)
1854{
1855 uint32_t cacheline;
1856 uint32_t pci_writemax = 0;
1857 uint32_t hdrsplit;
1858
1859 /* Initialize link to down state. */
1860 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1861
1862 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1863 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1864 else
1865 sc->ti_ifp->if_hwassist = 0;
1866
1867 /* Set endianness before we access any non-PCI registers. */
1868#if 0 && BYTE_ORDER == BIG_ENDIAN
1869 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1870 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1871#else
1872 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1873 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1874#endif
1875
1876 /* Check the ROM failed bit to see if self-tests passed. */
1877 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1878 device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
1879 return (ENODEV);
1880 }
1881
1882 /* Halt the CPU. */
1883 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1884
1885 /* Figure out the hardware revision. */
1886 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1887 case TI_REV_TIGON_I:
1888 sc->ti_hwrev = TI_HWREV_TIGON;
1889 break;
1890 case TI_REV_TIGON_II:
1891 sc->ti_hwrev = TI_HWREV_TIGON_II;
1892 break;
1893 default:
1894 device_printf(sc->ti_dev, "unsupported chip revision\n");
1895 return (ENODEV);
1896 }
1897
1898 /* Do special setup for Tigon 2. */
1899 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1900 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1901 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1902 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1903 }
1904
1905 /*
1906 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1907 * can't do header splitting.
1908 */
1909#ifdef TI_JUMBO_HDRSPLIT
1910 if (sc->ti_hwrev != TI_HWREV_TIGON)
1911 sc->ti_hdrsplit = 1;
1912 else
1913 device_printf(sc->ti_dev,
1914 "can't do header splitting on a Tigon I board\n");
1915#endif /* TI_JUMBO_HDRSPLIT */
1916
1917 /* Set up the PCI state register. */
1918 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1919 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1920 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1921 }
1922
1923 /* Clear the read/write max DMA parameters. */
1924 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1925 TI_PCISTATE_READ_MAXDMA));
1926
1927 /* Get cache line size. */
1928 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1929
1930 /*
1931 * If the system has set enabled the PCI memory write
1932 * and invalidate command in the command register, set
1933 * the write max parameter accordingly. This is necessary
1934 * to use MWI with the Tigon 2.
1935 */
1936 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1937 switch (cacheline) {
1938 case 1:
1939 case 4:
1940 case 8:
1941 case 16:
1942 case 32:
1943 case 64:
1944 break;
1945 default:
1946 /* Disable PCI memory write and invalidate. */
1947 if (bootverbose)
1948 device_printf(sc->ti_dev, "cache line size %d"
1949 " not supported; disabling PCI MWI\n",
1950 cacheline);
1951 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1952 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1953 break;
1954 }
1955 }
1956
1957 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1958
1959 /* This sets the min dma param all the way up (0xff). */
1960 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1961
1962 if (sc->ti_hdrsplit)
1963 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1964 else
1965 hdrsplit = 0;
1966
1967 /* Configure DMA variables. */
1968#if BYTE_ORDER == BIG_ENDIAN
1969 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1970 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1971 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1972 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1973#else /* BYTE_ORDER */
1974 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1975 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1976 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1977#endif /* BYTE_ORDER */
1978
1979 /*
1980 * Only allow 1 DMA channel to be active at a time.
1981 * I don't think this is a good idea, but without it
1982 * the firmware racks up lots of nicDmaReadRingFull
1983 * errors. This is not compatible with hardware checksums.
1984 */
1985 if (sc->ti_ifp->if_hwassist == 0)
1986 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1987
1988 /* Recommended settings from Tigon manual. */
1989 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1990 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1991
1992 if (ti_64bitslot_war(sc)) {
1993 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
1994 "but we aren't");
1995 return (EINVAL);
1996 }
1997
1998 return (0);
1999}
2000
2001/*
2002 * Initialize the general information block and firmware, and
2003 * start the CPU(s) running.
2004 */
2005static int
2006ti_gibinit(struct ti_softc *sc)
2007{
2008 struct ifnet *ifp;
2009 struct ti_rcb *rcb;
2010 uint32_t rdphys;
2011 int i;
2012
2013 TI_LOCK_ASSERT(sc);
2014
2015 ifp = sc->ti_ifp;
2016 rdphys = sc->ti_rdata_phys;
2017
2018 /* Disable interrupts for now. */
2019 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2020
2021 /*
2022 * Tell the chip where to find the general information block.
2023 * While this struct could go into >4GB memory, we allocate it in a
2024 * single slab with the other descriptors, and those don't seem to
2025 * support being located in a 64-bit region.
2026 */
2027 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
2028 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
2029
2030 /* Load the firmware into SRAM. */
2031 ti_loadfw(sc);
2032
2033 /* Set up the contents of the general info and ring control blocks. */
2034
2035 /* Set up the event ring and producer pointer. */
2036 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
2037
2038 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
2039 rcb->ti_flags = 0;
2040 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
2041 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
2042 sc->ti_ev_prodidx.ti_idx = 0;
2043 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2044 sc->ti_ev_saved_considx = 0;
2045
2046 /* Set up the command ring and producer mailbox. */
2047 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
2048
2049 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
2050 rcb->ti_flags = 0;
2051 rcb->ti_max_len = 0;
2052 for (i = 0; i < TI_CMD_RING_CNT; i++) {
2053 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2054 }
2055 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2056 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2057 sc->ti_cmd_saved_prodidx = 0;
2058
2059 /*
2060 * Assign the address of the stats refresh buffer.
2061 * We re-use the current stats buffer for this to
2062 * conserve memory.
2063 */
2064 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
2065 rdphys + TI_RD_OFF(ti_info.ti_stats);
2066
2067 /* Set up the standard receive ring. */
2068 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
2069 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
2070 rcb->ti_max_len = TI_FRAMELEN;
2071 rcb->ti_flags = 0;
2072 if (sc->ti_ifp->if_hwassist)
2073 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2074 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2075 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2076
2077 /* Set up the jumbo receive ring. */
2078 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
2079 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
2080
2081#ifdef TI_PRIVATE_JUMBOS
2082 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
2083 rcb->ti_flags = 0;
2084#else
2085 rcb->ti_max_len = PAGE_SIZE;
2086 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2087#endif
2088 if (sc->ti_ifp->if_hwassist)
2089 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2090 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2091 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2092
2093 /*
2094 * Set up the mini ring. Only activated on the
2095 * Tigon 2 but the slot in the config block is
2096 * still there on the Tigon 1.
2097 */
2098 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
2099 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
2100 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2101 if (sc->ti_hwrev == TI_HWREV_TIGON)
2102 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2103 else
2104 rcb->ti_flags = 0;
2105 if (sc->ti_ifp->if_hwassist)
2106 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2107 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2108 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2109
2110 /*
2111 * Set up the receive return ring.
2112 */
2113 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
2114 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
2115 rcb->ti_flags = 0;
2116 rcb->ti_max_len = TI_RETURN_RING_CNT;
2117 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
2118 rdphys + TI_RD_OFF(ti_return_prodidx_r);
2119
2120 /*
2121 * Set up the tx ring. Note: for the Tigon 2, we have the option
2122 * of putting the transmit ring in the host's address space and
2123 * letting the chip DMA it instead of leaving the ring in the NIC's
2124 * memory and accessing it through the shared memory region. We
2125 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2126 * so we have to revert to the shared memory scheme if we detect
2127 * a Tigon 1 chip.
2128 */
2129 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2130 bzero((char *)sc->ti_rdata->ti_tx_ring,
2131 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
2132 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
2133 if (sc->ti_hwrev == TI_HWREV_TIGON)
2134 rcb->ti_flags = 0;
2135 else
2136 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2137 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2138 if (sc->ti_ifp->if_hwassist)
2139 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2140 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2141 rcb->ti_max_len = TI_TX_RING_CNT;
2142 if (sc->ti_hwrev == TI_HWREV_TIGON)
2143 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
2144 else
2145 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
2146 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
2147 rdphys + TI_RD_OFF(ti_tx_considx_r);
2148
2149 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2150 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2151
2152 /* Set up tuneables */
2153#if 0
2154 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2155 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2156 (sc->ti_rx_coal_ticks / 10));
2157 else
2158#endif
2159 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2160 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2161 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2162 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2163 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2164 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2165
2166 /* Turn interrupts on. */
2167 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2168 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2169
2170 /* Start CPU. */
2171 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2172
2173 return (0);
2174}
2175
2176static void
2177ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2178{
2179 struct ti_softc *sc;
2180
2181 sc = arg;
2182 if (error || nseg != 1)
2183 return;
2184
2185 /*
2186 * All of the Tigon data structures need to live at <4GB. This
2187 * cast is fine since busdma was told about this constraint.
2188 */
2189 sc->ti_rdata_phys = segs[0].ds_addr;
2190 return;
2191}
2192
2193/*
2194 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2195 * against our list and return its name if we find a match.
2196 */
2197static int
2198ti_probe(device_t dev)
2199{
2200 const struct ti_type *t;
2201
2202 t = ti_devs;
2203
2204 while (t->ti_name != NULL) {
2205 if ((pci_get_vendor(dev) == t->ti_vid) &&
2206 (pci_get_device(dev) == t->ti_did)) {
2207 device_set_desc(dev, t->ti_name);
2208 return (BUS_PROBE_DEFAULT);
2209 }
2210 t++;
2211 }
2212
2213 return (ENXIO);
2214}
2215
2216static int
2217ti_attach(device_t dev)
2218{
2219 struct ifnet *ifp;
2220 struct ti_softc *sc;
2221 int error = 0, rid;
2222 u_char eaddr[6];
2223
2224 sc = device_get_softc(dev);
2225 sc->ti_unit = device_get_unit(dev);
2226 sc->ti_dev = dev;
2227
2228 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2229 MTX_DEF);
2230 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2231 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2232 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2233 if (ifp == NULL) {
2234 device_printf(dev, "can not if_alloc()\n");
2235 error = ENOSPC;
2236 goto fail;
2237 }
2238 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2239 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2240 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2241
2242 /*
2243 * Map control/status registers.
2244 */
2245 pci_enable_busmaster(dev);
2246
2247 rid = TI_PCI_LOMEM;
2248 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2249 RF_ACTIVE);
2250
2251 if (sc->ti_res == NULL) {
2252 device_printf(dev, "couldn't map memory\n");
2253 error = ENXIO;
2254 goto fail;
2255 }
2256
2257 sc->ti_btag = rman_get_bustag(sc->ti_res);
2258 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2259
2260 /* Allocate interrupt */
2261 rid = 0;
2262
2263 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2264 RF_SHAREABLE | RF_ACTIVE);
2265
2266 if (sc->ti_irq == NULL) {
2267 device_printf(dev, "couldn't map interrupt\n");
2268 error = ENXIO;
2269 goto fail;
2270 }
2271
2272 if (ti_chipinit(sc)) {
2273 device_printf(dev, "chip initialization failed\n");
2274 error = ENXIO;
2275 goto fail;
2276 }
2277
2278 /* Zero out the NIC's on-board SRAM. */
2279 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2280
2281 /* Init again -- zeroing memory may have clobbered some registers. */
2282 if (ti_chipinit(sc)) {
2283 device_printf(dev, "chip initialization failed\n");
2284 error = ENXIO;
2285 goto fail;
2286 }
2287
2288 /*
2289 * Get station address from the EEPROM. Note: the manual states
2290 * that the MAC address is at offset 0x8c, however the data is
2291 * stored as two longwords (since that's how it's loaded into
2292 * the NIC). This means the MAC address is actually preceded
2293 * by two zero bytes. We need to skip over those.
2294 */
2295 if (ti_read_eeprom(sc, eaddr,
2296 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2297 device_printf(dev, "failed to read station address\n");
2298 error = ENXIO;
2299 goto fail;
2300 }
2301
2302 /* Allocate the general information block and ring buffers. */
2303 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
2304 1, 0, /* algnmnt, boundary */
2305 BUS_SPACE_MAXADDR, /* lowaddr */
2306 BUS_SPACE_MAXADDR, /* highaddr */
2307 NULL, NULL, /* filter, filterarg */
2308 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2309 0, /* nsegments */
2310 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2311 0, /* flags */
2312 NULL, NULL, /* lockfunc, lockarg */
2313 &sc->ti_parent_dmat) != 0) {
2314 device_printf(dev, "Failed to allocate parent dmat\n");
2315 error = ENOMEM;
2316 goto fail;
2317 }
2318
2319 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2320 PAGE_SIZE, 0, /* algnmnt, boundary */
2321 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2322 BUS_SPACE_MAXADDR, /* highaddr */
2323 NULL, NULL, /* filter, filterarg */
2324 sizeof(struct ti_ring_data), /* maxsize */
2325 1, /* nsegments */
2326 sizeof(struct ti_ring_data), /* maxsegsize */
2327 0, /* flags */
2328 NULL, NULL, /* lockfunc, lockarg */
2329 &sc->ti_rdata_dmat) != 0) {
2330 device_printf(dev, "Failed to allocate rdata dmat\n");
2331 error = ENOMEM;
2332 goto fail;
2333 }
2334
2335 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2336 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2337 &sc->ti_rdata_dmamap) != 0) {
2338 device_printf(dev, "Failed to allocate rdata memory\n");
2339 error = ENOMEM;
2340 goto fail;
2341 }
2342
2343 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2344 sc->ti_rdata, sizeof(struct ti_ring_data),
2345 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2346 device_printf(dev, "Failed to load rdata segments\n");
2347 error = ENOMEM;
2348 goto fail;
2349 }
2350
2351 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2352
2353 /* Try to allocate memory for jumbo buffers. */
2354 if (ti_alloc_jumbo_mem(sc)) {
2355 device_printf(dev, "jumbo buffer allocation failed\n");
2356 error = ENXIO;
2357 goto fail;
2358 }
2359
2360 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2361 1, 0, /* algnmnt, boundary */
2362 BUS_SPACE_MAXADDR, /* lowaddr */
2363 BUS_SPACE_MAXADDR, /* highaddr */
2364 NULL, NULL, /* filter, filterarg */
2365 MCLBYTES * TI_MAXTXSEGS,/* maxsize */
2366 TI_MAXTXSEGS, /* nsegments */
2367 MCLBYTES, /* maxsegsize */
2368 0, /* flags */
2369 NULL, NULL, /* lockfunc, lockarg */
2370 &sc->ti_mbuftx_dmat) != 0) {
2371 device_printf(dev, "Failed to allocate rdata dmat\n");
2372 error = ENOMEM;
2373 goto fail;
2374 }
2375
2376 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2377 1, 0, /* algnmnt, boundary */
2378 BUS_SPACE_MAXADDR, /* lowaddr */
2379 BUS_SPACE_MAXADDR, /* highaddr */
2380 NULL, NULL, /* filter, filterarg */
2381 MCLBYTES, /* maxsize */
2382 1, /* nsegments */
2383 MCLBYTES, /* maxsegsize */
2384 0, /* flags */
2385 NULL, NULL, /* lockfunc, lockarg */
2386 &sc->ti_mbufrx_dmat) != 0) {
2387 device_printf(dev, "Failed to allocate rdata dmat\n");
2388 error = ENOMEM;
2389 goto fail;
2390 }
2391
2392 if (ti_alloc_dmamaps(sc)) {
2393 device_printf(dev, "dma map creation failed\n");
2394 error = ENXIO;
2395 goto fail;
2396 }
2397
2398 /*
2399 * We really need a better way to tell a 1000baseTX card
2400 * from a 1000baseSX one, since in theory there could be
2401 * OEMed 1000baseTX cards from lame vendors who aren't
2402 * clever enough to change the PCI ID. For the moment
2403 * though, the AceNIC is the only copper card available.
2404 */
2405 if (pci_get_vendor(dev) == ALT_VENDORID &&
2406 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2407 sc->ti_copper = 1;
2408 /* Ok, it's not the only copper card available. */
2409 if (pci_get_vendor(dev) == NG_VENDORID &&
2410 pci_get_device(dev) == NG_DEVICEID_GA620T)
2411 sc->ti_copper = 1;
2412
2413 /* Set default tuneable values. */
2414 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2415#if 0
2416 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2417#endif
2418 sc->ti_rx_coal_ticks = 170;
2419 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2420 sc->ti_rx_max_coal_bds = 64;
2421#if 0
2422 sc->ti_tx_max_coal_bds = 128;
2423#endif
2424 sc->ti_tx_max_coal_bds = 32;
2425 sc->ti_tx_buf_ratio = 21;
2426
2427 /* Set up ifnet structure */
2428 ifp->if_softc = sc;
2429 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2431 ifp->if_ioctl = ti_ioctl;
2432 ifp->if_start = ti_start;
2433 ifp->if_init = ti_init;
|
2420 ifp->if_baudrate = 1000000000;
| 2434 ifp->if_baudrate = IF_Gbps(1UL);
|
2421 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2422
2423 /* Set up ifmedia support. */
2424 if (sc->ti_copper) {
2425 /*
2426 * Copper cards allow manual 10/100 mode selection,
2427 * but not manual 1000baseTX mode selection. Why?
2428 * Becuase currently there's no way to specify the
2429 * master/slave setting through the firmware interface,
2430 * so Alteon decided to just bag it and handle it
2431 * via autonegotiation.
2432 */
2433 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2434 ifmedia_add(&sc->ifmedia,
2435 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2436 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2437 ifmedia_add(&sc->ifmedia,
2438 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2439 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2440 ifmedia_add(&sc->ifmedia,
2441 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2442 } else {
2443 /* Fiber cards don't support 10/100 modes. */
2444 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2445 ifmedia_add(&sc->ifmedia,
2446 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2447 }
2448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2449 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2450
2451 /*
2452 * We're assuming here that card initialization is a sequential
2453 * thing. If it isn't, multiple cards probing at the same time
2454 * could stomp on the list of softcs here.
2455 */
2456
2457 /* Register the device */
2458 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2459 0600, "ti%d", sc->ti_unit);
2460 sc->dev->si_drv1 = sc;
2461
2462 /*
2463 * Call MI attach routine.
2464 */
2465 ether_ifattach(ifp, eaddr);
2466
| 2435 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2436
2437 /* Set up ifmedia support. */
2438 if (sc->ti_copper) {
2439 /*
2440 * Copper cards allow manual 10/100 mode selection,
2441 * but not manual 1000baseTX mode selection. Why?
2442 * Becuase currently there's no way to specify the
2443 * master/slave setting through the firmware interface,
2444 * so Alteon decided to just bag it and handle it
2445 * via autonegotiation.
2446 */
2447 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2448 ifmedia_add(&sc->ifmedia,
2449 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2450 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2451 ifmedia_add(&sc->ifmedia,
2452 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2453 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2454 ifmedia_add(&sc->ifmedia,
2455 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2456 } else {
2457 /* Fiber cards don't support 10/100 modes. */
2458 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2459 ifmedia_add(&sc->ifmedia,
2460 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2461 }
2462 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2463 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2464
2465 /*
2466 * We're assuming here that card initialization is a sequential
2467 * thing. If it isn't, multiple cards probing at the same time
2468 * could stomp on the list of softcs here.
2469 */
2470
2471 /* Register the device */
2472 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2473 0600, "ti%d", sc->ti_unit);
2474 sc->dev->si_drv1 = sc;
2475
2476 /*
2477 * Call MI attach routine.
2478 */
2479 ether_ifattach(ifp, eaddr);
2480
|
| 2481 /* Driver supports link state tracking. */
2482 ifp->if_capabilities |= IFCAP_LINKSTATE;
2483 ifp->if_capenable |= IFCAP_LINKSTATE;
2484
|
2467 /* Hook interrupt last to avoid having to lock softc */
2468 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2469 NULL, ti_intr, sc, &sc->ti_intrhand);
2470
2471 if (error) {
2472 device_printf(dev, "couldn't set up irq\n");
2473 goto fail;
2474 }
2475
2476fail:
2477 if (error)
2478 ti_detach(dev);
2479
2480 return (error);
2481}
2482
2483/*
2484 * Shutdown hardware and free up resources. This can be called any
2485 * time after the mutex has been initialized. It is called in both
2486 * the error case in attach and the normal detach case so it needs
2487 * to be careful about only freeing resources that have actually been
2488 * allocated.
2489 */
2490static int
2491ti_detach(device_t dev)
2492{
2493 struct ti_softc *sc;
2494 struct ifnet *ifp;
2495
2496 sc = device_get_softc(dev);
2497 if (sc->dev)
2498 destroy_dev(sc->dev);
2499 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2500 ifp = sc->ti_ifp;
2501 if (device_is_attached(dev)) {
2502 ether_ifdetach(ifp);
2503 TI_LOCK(sc);
2504 ti_stop(sc);
2505 TI_UNLOCK(sc);
2506 }
2507
2508 /* These should only be active if attach succeeded */
2509 callout_drain(&sc->ti_watchdog);
2510 bus_generic_detach(dev);
2511 ti_free_dmamaps(sc);
2512 ifmedia_removeall(&sc->ifmedia);
2513
2514#ifdef TI_PRIVATE_JUMBOS
2515 if (sc->ti_cdata.ti_jumbo_buf)
2516 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2517 sc->ti_jumbo_dmamap);
2518#endif
2519 if (sc->ti_jumbo_dmat)
2520 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2521 if (sc->ti_mbuftx_dmat)
2522 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2523 if (sc->ti_mbufrx_dmat)
2524 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2525 if (sc->ti_rdata && sc->ti_rdata_dmamap)
2526 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap);
2527 if (sc->ti_rdata)
2528 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2529 sc->ti_rdata_dmamap);
2530 if (sc->ti_rdata_dmat)
2531 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2532 if (sc->ti_parent_dmat)
2533 bus_dma_tag_destroy(sc->ti_parent_dmat);
2534 if (sc->ti_intrhand)
2535 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2536 if (sc->ti_irq)
2537 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2538 if (sc->ti_res) {
2539 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2540 sc->ti_res);
2541 }
2542 if (ifp)
2543 if_free(ifp);
2544
2545 mtx_destroy(&sc->ti_mtx);
2546
2547 return (0);
2548}
2549
2550#ifdef TI_JUMBO_HDRSPLIT
2551/*
2552 * If hdr_len is 0, that means that header splitting wasn't done on
2553 * this packet for some reason. The two most likely reasons are that
2554 * the protocol isn't a supported protocol for splitting, or this
2555 * packet had a fragment offset that wasn't 0.
2556 *
2557 * The header length, if it is non-zero, will always be the length of
2558 * the headers on the packet, but that length could be longer than the
2559 * first mbuf. So we take the minimum of the two as the actual
2560 * length.
2561 */
2562static __inline void
2563ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2564{
2565 int i = 0;
2566 int lengths[4] = {0, 0, 0, 0};
2567 struct mbuf *m, *mp;
2568
2569 if (hdr_len != 0)
2570 top->m_len = min(hdr_len, top->m_len);
2571 pkt_len -= top->m_len;
2572 lengths[i++] = top->m_len;
2573
2574 mp = top;
2575 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2576 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2577 pkt_len -= m->m_len;
2578 lengths[i++] = m->m_len;
2579 mp = m;
2580 }
2581
2582#if 0
2583 if (hdr_len != 0)
2584 printf("got split packet: ");
2585 else
2586 printf("got non-split packet: ");
2587
2588 printf("%d,%d,%d,%d = %d\n", lengths[0],
2589 lengths[1], lengths[2], lengths[3],
2590 lengths[0] + lengths[1] + lengths[2] +
2591 lengths[3]);
2592#endif
2593
2594 if (pkt_len)
2595 panic("header splitting didn't");
2596
2597 if (m) {
2598 m_freem(m);
2599 mp->m_next = NULL;
2600
2601 }
2602 if (mp->m_next != NULL)
2603 panic("ti_hdr_split: last mbuf in chain should be null");
2604}
2605#endif /* TI_JUMBO_HDRSPLIT */
2606
2607/*
2608 * Frame reception handling. This is called if there's a frame
2609 * on the receive return list.
2610 *
2611 * Note: we have to be able to handle three possibilities here:
2612 * 1) the frame is from the mini receive ring (can only happen)
2613 * on Tigon 2 boards)
2614 * 2) the frame is from the jumbo recieve ring
2615 * 3) the frame is from the standard receive ring
2616 */
2617
2618static void
2619ti_rxeof(struct ti_softc *sc)
2620{
2621 struct ifnet *ifp;
2622 bus_dmamap_t map;
2623 struct ti_cmd_desc cmd;
2624
2625 TI_LOCK_ASSERT(sc);
2626
2627 ifp = sc->ti_ifp;
2628
2629 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2630 struct ti_rx_desc *cur_rx;
2631 struct mbuf *m = NULL;
2632 uint32_t rxidx;
2633 uint16_t vlan_tag = 0;
2634 int have_tag = 0;
2635
2636 cur_rx =
2637 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2638 rxidx = cur_rx->ti_idx;
2639 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2640
2641 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2642 have_tag = 1;
2643 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2644 }
2645
2646 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2647
2648 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2649 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2650 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2651 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2652 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2653 BUS_DMASYNC_POSTREAD);
2654 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2655 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2656 ifp->if_ierrors++;
2657 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2658 continue;
2659 }
2660 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2661 ifp->if_ierrors++;
2662 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2663 continue;
2664 }
2665#ifdef TI_PRIVATE_JUMBOS
2666 m->m_len = cur_rx->ti_len;
2667#else /* TI_PRIVATE_JUMBOS */
2668#ifdef TI_JUMBO_HDRSPLIT
2669 if (sc->ti_hdrsplit)
2670 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2671 cur_rx->ti_len, rxidx);
2672 else
2673#endif /* TI_JUMBO_HDRSPLIT */
2674 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2675#endif /* TI_PRIVATE_JUMBOS */
2676 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2677 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2678 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2679 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2680 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2681 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2682 BUS_DMASYNC_POSTREAD);
2683 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2684 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2685 ifp->if_ierrors++;
2686 ti_newbuf_mini(sc, sc->ti_mini, m);
2687 continue;
2688 }
2689 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2690 ifp->if_ierrors++;
2691 ti_newbuf_mini(sc, sc->ti_mini, m);
2692 continue;
2693 }
2694 m->m_len = cur_rx->ti_len;
2695 } else {
2696 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2697 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2698 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2699 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2700 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2701 BUS_DMASYNC_POSTREAD);
2702 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2703 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2704 ifp->if_ierrors++;
2705 ti_newbuf_std(sc, sc->ti_std, m);
2706 continue;
2707 }
2708 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2709 ifp->if_ierrors++;
2710 ti_newbuf_std(sc, sc->ti_std, m);
2711 continue;
2712 }
2713 m->m_len = cur_rx->ti_len;
2714 }
2715
2716 m->m_pkthdr.len = cur_rx->ti_len;
2717 ifp->if_ipackets++;
2718 m->m_pkthdr.rcvif = ifp;
2719
2720 if (ifp->if_hwassist) {
2721 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2722 CSUM_DATA_VALID;
2723 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2724 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2725 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2726 }
2727
2728 /*
2729 * If we received a packet with a vlan tag,
2730 * tag it before passing the packet upward.
2731 */
2732 if (have_tag) {
2733 m->m_pkthdr.ether_vtag = vlan_tag;
2734 m->m_flags |= M_VLANTAG;
2735 }
2736 TI_UNLOCK(sc);
2737 (*ifp->if_input)(ifp, m);
2738 TI_LOCK(sc);
2739 }
2740
2741 /* Only necessary on the Tigon 1. */
2742 if (sc->ti_hwrev == TI_HWREV_TIGON)
2743 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2744 sc->ti_rx_saved_considx);
2745
2746 TI_UPDATE_STDPROD(sc, sc->ti_std);
2747 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2748 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2749}
2750
2751static void
2752ti_txeof(struct ti_softc *sc)
2753{
2754 struct ti_txdesc *txd;
2755 struct ti_tx_desc txdesc;
2756 struct ti_tx_desc *cur_tx = NULL;
2757 struct ifnet *ifp;
2758 int idx;
2759
2760 ifp = sc->ti_ifp;
2761
2762 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2763 if (txd == NULL)
2764 return;
2765 /*
2766 * Go through our tx ring and free mbufs for those
2767 * frames that have been sent.
2768 */
2769 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2770 TI_INC(idx, TI_TX_RING_CNT)) {
2771 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2772 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2773 sizeof(txdesc), &txdesc);
2774 cur_tx = &txdesc;
2775 } else
2776 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2777 sc->ti_txcnt--;
2778 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2779 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2780 continue;
2781 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2782 BUS_DMASYNC_POSTWRITE);
2783 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2784
2785 ifp->if_opackets++;
2786 m_freem(txd->tx_m);
2787 txd->tx_m = NULL;
2788 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2789 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2790 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2791 }
2792 sc->ti_tx_saved_considx = idx;
2793
2794 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2795}
2796
2797static void
2798ti_intr(void *xsc)
2799{
2800 struct ti_softc *sc;
2801 struct ifnet *ifp;
2802
2803 sc = xsc;
2804 TI_LOCK(sc);
2805 ifp = sc->ti_ifp;
2806
2807/*#ifdef notdef*/
2808 /* Avoid this for now -- checking this register is expensive. */
2809 /* Make sure this is really our interrupt. */
2810 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2811 TI_UNLOCK(sc);
2812 return;
2813 }
2814/*#endif*/
2815
2816 /* Ack interrupt and stop others from occuring. */
2817 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2818
2819 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2820 /* Check RX return ring producer/consumer */
2821 ti_rxeof(sc);
2822
2823 /* Check TX ring producer/consumer */
2824 ti_txeof(sc);
2825 }
2826
2827 ti_handle_events(sc);
2828
2829 /* Re-enable interrupts. */
2830 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2831
2832 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2833 ifp->if_snd.ifq_head != NULL)
2834 ti_start_locked(ifp);
2835
2836 TI_UNLOCK(sc);
2837}
2838
2839static void
2840ti_stats_update(struct ti_softc *sc)
2841{
2842 struct ifnet *ifp;
2843
2844 ifp = sc->ti_ifp;
2845
2846 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2847 BUS_DMASYNC_POSTREAD);
2848
2849 ifp->if_collisions +=
2850 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2851 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2852 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2853 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2854 ifp->if_collisions;
2855
2856 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2857 BUS_DMASYNC_PREREAD);
2858}
2859
2860/*
2861 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2862 * pointers to descriptors.
2863 */
2864static int
2865ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2866{
2867 struct ti_txdesc *txd;
2868 struct ti_tx_desc *f;
2869 struct ti_tx_desc txdesc;
2870 struct mbuf *m;
2871 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2872 uint16_t csum_flags;
2873 int error, frag, i, nseg;
2874
2875 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2876 return (ENOBUFS);
2877
2878 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2879 *m_head, txsegs, &nseg, 0);
2880 if (error == EFBIG) {
2881 m = m_defrag(*m_head, M_DONTWAIT);
2882 if (m == NULL) {
2883 m_freem(*m_head);
2884 *m_head = NULL;
2885 return (ENOMEM);
2886 }
2887 *m_head = m;
2888 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2889 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2890 if (error) {
2891 m_freem(*m_head);
2892 *m_head = NULL;
2893 return (error);
2894 }
2895 } else if (error != 0)
2896 return (error);
2897 if (nseg == 0) {
2898 m_freem(*m_head);
2899 *m_head = NULL;
2900 return (EIO);
2901 }
2902
2903 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2904 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2905 return (ENOBUFS);
2906 }
2907
2908 m = *m_head;
2909 csum_flags = 0;
2910 if (m->m_pkthdr.csum_flags) {
2911 if (m->m_pkthdr.csum_flags & CSUM_IP)
2912 csum_flags |= TI_BDFLAG_IP_CKSUM;
2913 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2914 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2915 if (m->m_flags & M_LASTFRAG)
2916 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2917 else if (m->m_flags & M_FRAG)
2918 csum_flags |= TI_BDFLAG_IP_FRAG;
2919 }
2920
2921 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2922 BUS_DMASYNC_PREWRITE);
2923 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2924 BUS_DMASYNC_PREWRITE);
2925
2926 frag = sc->ti_tx_saved_prodidx;
2927 for (i = 0; i < nseg; i++) {
2928 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2929 bzero(&txdesc, sizeof(txdesc));
2930 f = &txdesc;
2931 } else
2932 f = &sc->ti_rdata->ti_tx_ring[frag];
2933 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2934 f->ti_len = txsegs[i].ds_len;
2935 f->ti_flags = csum_flags;
2936 if (m->m_flags & M_VLANTAG) {
2937 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2938 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff;
2939 } else {
2940 f->ti_vlan_tag = 0;
2941 }
2942
2943 if (sc->ti_hwrev == TI_HWREV_TIGON)
2944 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2945 sizeof(txdesc), sizeof(txdesc), &txdesc);
2946 TI_INC(frag, TI_TX_RING_CNT);
2947 }
2948
2949 sc->ti_tx_saved_prodidx = frag;
2950 /* set TI_BDFLAG_END on the last descriptor */
2951 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2952 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2953 txdesc.ti_flags |= TI_BDFLAG_END;
2954 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2955 sizeof(txdesc), &txdesc);
2956 } else
2957 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
2958
2959 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
2960 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
2961 txd->tx_m = m;
2962 sc->ti_txcnt += nseg;
2963
2964 return (0);
2965}
2966
2967static void
2968ti_start(struct ifnet *ifp)
2969{
2970 struct ti_softc *sc;
2971
2972 sc = ifp->if_softc;
2973 TI_LOCK(sc);
2974 ti_start_locked(ifp);
2975 TI_UNLOCK(sc);
2976}
2977
2978/*
2979 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2980 * to the mbuf data regions directly in the transmit descriptors.
2981 */
2982static void
2983ti_start_locked(struct ifnet *ifp)
2984{
2985 struct ti_softc *sc;
2986 struct mbuf *m_head = NULL;
2987 int enq = 0;
2988
2989 sc = ifp->if_softc;
2990
2991 for (; ifp->if_snd.ifq_head != NULL &&
2992 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
2993 IF_DEQUEUE(&ifp->if_snd, m_head);
2994 if (m_head == NULL)
2995 break;
2996
2997 /*
2998 * XXX
2999 * safety overkill. If this is a fragmented packet chain
3000 * with delayed TCP/UDP checksums, then only encapsulate
3001 * it if we have enough descriptors to handle the entire
3002 * chain at once.
3003 * (paranoia -- may not actually be needed)
3004 */
3005 if (m_head->m_flags & M_FIRSTFRAG &&
3006 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3007 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3008 m_head->m_pkthdr.csum_data + 16) {
3009 IF_PREPEND(&ifp->if_snd, m_head);
3010 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3011 break;
3012 }
3013 }
3014
3015 /*
3016 * Pack the data into the transmit ring. If we
3017 * don't have room, set the OACTIVE flag and wait
3018 * for the NIC to drain the ring.
3019 */
3020 if (ti_encap(sc, &m_head)) {
3021 if (m_head == NULL)
3022 break;
3023 IF_PREPEND(&ifp->if_snd, m_head);
3024 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3025 break;
3026 }
3027
3028 enq++;
3029 /*
3030 * If there's a BPF listener, bounce a copy of this frame
3031 * to him.
3032 */
3033 ETHER_BPF_MTAP(ifp, m_head);
3034 }
3035
3036 if (enq > 0) {
3037 /* Transmit */
3038 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3039
3040 /*
3041 * Set a timeout in case the chip goes out to lunch.
3042 */
3043 sc->ti_timer = 5;
3044 }
3045}
3046
3047static void
3048ti_init(void *xsc)
3049{
3050 struct ti_softc *sc;
3051
3052 sc = xsc;
3053 TI_LOCK(sc);
3054 ti_init_locked(sc);
3055 TI_UNLOCK(sc);
3056}
3057
3058static void
3059ti_init_locked(void *xsc)
3060{
3061 struct ti_softc *sc = xsc;
3062
3063 /* Cancel pending I/O and flush buffers. */
3064 ti_stop(sc);
3065
3066 /* Init the gen info block, ring control blocks and firmware. */
3067 if (ti_gibinit(sc)) {
3068 device_printf(sc->ti_dev, "initialization failure\n");
3069 return;
3070 }
3071}
3072
3073static void ti_init2(struct ti_softc *sc)
3074{
3075 struct ti_cmd_desc cmd;
3076 struct ifnet *ifp;
3077 uint8_t *ea;
3078 struct ifmedia *ifm;
3079 int tmp;
3080
3081 TI_LOCK_ASSERT(sc);
3082
3083 ifp = sc->ti_ifp;
3084
3085 /* Specify MTU and interface index. */
3086 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3087 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3088 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3089 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3090
3091 /* Load our MAC address. */
3092 ea = IF_LLADDR(sc->ti_ifp);
3093 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3094 CSR_WRITE_4(sc, TI_GCR_PAR1,
3095 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3096 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3097
3098 /* Enable or disable promiscuous mode as needed. */
3099 if (ifp->if_flags & IFF_PROMISC) {
3100 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3101 } else {
3102 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3103 }
3104
3105 /* Program multicast filter. */
3106 ti_setmulti(sc);
3107
3108 /*
3109 * If this is a Tigon 1, we should tell the
3110 * firmware to use software packet filtering.
3111 */
3112 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3113 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3114 }
3115
3116 /* Init RX ring. */
3117 ti_init_rx_ring_std(sc);
3118
3119 /* Init jumbo RX ring. */
3120 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3121 ti_init_rx_ring_jumbo(sc);
3122
3123 /*
3124 * If this is a Tigon 2, we can also configure the
3125 * mini ring.
3126 */
3127 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3128 ti_init_rx_ring_mini(sc);
3129
3130 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3131 sc->ti_rx_saved_considx = 0;
3132
3133 /* Init TX ring. */
3134 ti_init_tx_ring(sc);
3135
3136 /* Tell firmware we're alive. */
3137 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3138
3139 /* Enable host interrupts. */
3140 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3141
3142 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3143 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3144 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3145
3146 /*
3147 * Make sure to set media properly. We have to do this
3148 * here since we have to issue commands in order to set
3149 * the link negotiation and we can't issue commands until
3150 * the firmware is running.
3151 */
3152 ifm = &sc->ifmedia;
3153 tmp = ifm->ifm_media;
3154 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3155 ti_ifmedia_upd(ifp);
3156 ifm->ifm_media = tmp;
3157}
3158
3159/*
3160 * Set media options.
3161 */
3162static int
3163ti_ifmedia_upd(struct ifnet *ifp)
3164{
3165 struct ti_softc *sc;
3166 struct ifmedia *ifm;
3167 struct ti_cmd_desc cmd;
3168 uint32_t flowctl;
3169
3170 sc = ifp->if_softc;
3171 ifm = &sc->ifmedia;
3172
3173 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3174 return (EINVAL);
3175
3176 flowctl = 0;
3177
3178 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3179 case IFM_AUTO:
3180 /*
3181 * Transmit flow control doesn't work on the Tigon 1.
3182 */
3183 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3184
3185 /*
3186 * Transmit flow control can also cause problems on the
3187 * Tigon 2, apparantly with both the copper and fiber
3188 * boards. The symptom is that the interface will just
3189 * hang. This was reproduced with Alteon 180 switches.
3190 */
3191#if 0
3192 if (sc->ti_hwrev != TI_HWREV_TIGON)
3193 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3194#endif
3195
3196 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3197 TI_GLNK_FULL_DUPLEX| flowctl |
3198 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3199
3200 flowctl = TI_LNK_RX_FLOWCTL_Y;
3201#if 0
3202 if (sc->ti_hwrev != TI_HWREV_TIGON)
3203 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3204#endif
3205
3206 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3207 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3208 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3209 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3210 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3211 break;
3212 case IFM_1000_SX:
3213 case IFM_1000_T:
3214 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3215#if 0
3216 if (sc->ti_hwrev != TI_HWREV_TIGON)
3217 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3218#endif
3219
3220 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3221 flowctl |TI_GLNK_ENB);
3222 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3223 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3224 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3225 }
3226 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3227 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3228 break;
3229 case IFM_100_FX:
3230 case IFM_10_FL:
3231 case IFM_100_TX:
3232 case IFM_10_T:
3233 flowctl = TI_LNK_RX_FLOWCTL_Y;
3234#if 0
3235 if (sc->ti_hwrev != TI_HWREV_TIGON)
3236 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3237#endif
3238
3239 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3240 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3241 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3242 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3243 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3244 } else {
3245 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3246 }
3247 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3248 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3249 } else {
3250 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3251 }
3252 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3253 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3254 break;
3255 }
3256
3257 return (0);
3258}
3259
3260/*
3261 * Report current media status.
3262 */
3263static void
3264ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3265{
3266 struct ti_softc *sc;
3267 uint32_t media = 0;
3268
3269 sc = ifp->if_softc;
3270
3271 ifmr->ifm_status = IFM_AVALID;
3272 ifmr->ifm_active = IFM_ETHER;
3273
3274 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3275 return;
3276
3277 ifmr->ifm_status |= IFM_ACTIVE;
3278
3279 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3280 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3281 if (sc->ti_copper)
3282 ifmr->ifm_active |= IFM_1000_T;
3283 else
3284 ifmr->ifm_active |= IFM_1000_SX;
3285 if (media & TI_GLNK_FULL_DUPLEX)
3286 ifmr->ifm_active |= IFM_FDX;
3287 else
3288 ifmr->ifm_active |= IFM_HDX;
3289 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3290 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3291 if (sc->ti_copper) {
3292 if (media & TI_LNK_100MB)
3293 ifmr->ifm_active |= IFM_100_TX;
3294 if (media & TI_LNK_10MB)
3295 ifmr->ifm_active |= IFM_10_T;
3296 } else {
3297 if (media & TI_LNK_100MB)
3298 ifmr->ifm_active |= IFM_100_FX;
3299 if (media & TI_LNK_10MB)
3300 ifmr->ifm_active |= IFM_10_FL;
3301 }
3302 if (media & TI_LNK_FULL_DUPLEX)
3303 ifmr->ifm_active |= IFM_FDX;
3304 if (media & TI_LNK_HALF_DUPLEX)
3305 ifmr->ifm_active |= IFM_HDX;
3306 }
3307}
3308
3309static int
3310ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3311{
3312 struct ti_softc *sc = ifp->if_softc;
3313 struct ifreq *ifr = (struct ifreq *) data;
3314 struct ti_cmd_desc cmd;
3315 int mask, error = 0;
3316
3317 switch (command) {
3318 case SIOCSIFMTU:
3319 TI_LOCK(sc);
3320 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3321 error = EINVAL;
3322 else {
3323 ifp->if_mtu = ifr->ifr_mtu;
3324 ti_init_locked(sc);
3325 }
3326 TI_UNLOCK(sc);
3327 break;
3328 case SIOCSIFFLAGS:
3329 TI_LOCK(sc);
3330 if (ifp->if_flags & IFF_UP) {
3331 /*
3332 * If only the state of the PROMISC flag changed,
3333 * then just use the 'set promisc mode' command
3334 * instead of reinitializing the entire NIC. Doing
3335 * a full re-init means reloading the firmware and
3336 * waiting for it to start up, which may take a
3337 * second or two.
3338 */
3339 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3340 ifp->if_flags & IFF_PROMISC &&
3341 !(sc->ti_if_flags & IFF_PROMISC)) {
3342 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3343 TI_CMD_CODE_PROMISC_ENB, 0);
3344 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3345 !(ifp->if_flags & IFF_PROMISC) &&
3346 sc->ti_if_flags & IFF_PROMISC) {
3347 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3348 TI_CMD_CODE_PROMISC_DIS, 0);
3349 } else
3350 ti_init_locked(sc);
3351 } else {
3352 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3353 ti_stop(sc);
3354 }
3355 }
3356 sc->ti_if_flags = ifp->if_flags;
3357 TI_UNLOCK(sc);
3358 break;
3359 case SIOCADDMULTI:
3360 case SIOCDELMULTI:
3361 TI_LOCK(sc);
3362 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3363 ti_setmulti(sc);
3364 TI_UNLOCK(sc);
3365 break;
3366 case SIOCSIFMEDIA:
3367 case SIOCGIFMEDIA:
3368 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3369 break;
3370 case SIOCSIFCAP:
3371 TI_LOCK(sc);
3372 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3373 if (mask & IFCAP_HWCSUM) {
3374 if (IFCAP_HWCSUM & ifp->if_capenable)
3375 ifp->if_capenable &= ~IFCAP_HWCSUM;
3376 else
3377 ifp->if_capenable |= IFCAP_HWCSUM;
3378 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3379 ti_init_locked(sc);
3380 }
3381 TI_UNLOCK(sc);
3382 break;
3383 default:
3384 error = ether_ioctl(ifp, command, data);
3385 break;
3386 }
3387
3388 return (error);
3389}
3390
3391static int
3392ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3393{
3394 struct ti_softc *sc;
3395
3396 sc = dev->si_drv1;
3397 if (sc == NULL)
3398 return (ENODEV);
3399
3400 TI_LOCK(sc);
3401 sc->ti_flags |= TI_FLAG_DEBUGING;
3402 TI_UNLOCK(sc);
3403
3404 return (0);
3405}
3406
3407static int
3408ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3409{
3410 struct ti_softc *sc;
3411
3412 sc = dev->si_drv1;
3413 if (sc == NULL)
3414 return (ENODEV);
3415
3416 TI_LOCK(sc);
3417 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3418 TI_UNLOCK(sc);
3419
3420 return (0);
3421}
3422
3423/*
3424 * This ioctl routine goes along with the Tigon character device.
3425 */
3426static int
3427ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3428 struct thread *td)
3429{
3430 struct ti_softc *sc;
3431 int error;
3432
3433 sc = dev->si_drv1;
3434 if (sc == NULL)
3435 return (ENODEV);
3436
3437 error = 0;
3438
3439 switch (cmd) {
3440 case TIIOCGETSTATS:
3441 {
3442 struct ti_stats *outstats;
3443
3444 outstats = (struct ti_stats *)addr;
3445
3446 TI_LOCK(sc);
3447 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3448 sizeof(struct ti_stats));
3449 TI_UNLOCK(sc);
3450 break;
3451 }
3452 case TIIOCGETPARAMS:
3453 {
3454 struct ti_params *params;
3455
3456 params = (struct ti_params *)addr;
3457
3458 TI_LOCK(sc);
3459 params->ti_stat_ticks = sc->ti_stat_ticks;
3460 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3461 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3462 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3463 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3464 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3465 params->param_mask = TI_PARAM_ALL;
3466 TI_UNLOCK(sc);
3467
3468 error = 0;
3469
3470 break;
3471 }
3472 case TIIOCSETPARAMS:
3473 {
3474 struct ti_params *params;
3475
3476 params = (struct ti_params *)addr;
3477
3478 TI_LOCK(sc);
3479 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3480 sc->ti_stat_ticks = params->ti_stat_ticks;
3481 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3482 }
3483
3484 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3485 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3486 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3487 sc->ti_rx_coal_ticks);
3488 }
3489
3490 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3491 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3492 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3493 sc->ti_tx_coal_ticks);
3494 }
3495
3496 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3497 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3498 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3499 sc->ti_rx_max_coal_bds);
3500 }
3501
3502 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3503 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3504 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3505 sc->ti_tx_max_coal_bds);
3506 }
3507
3508 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3509 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3510 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3511 sc->ti_tx_buf_ratio);
3512 }
3513 TI_UNLOCK(sc);
3514
3515 error = 0;
3516
3517 break;
3518 }
3519 case TIIOCSETTRACE: {
3520 ti_trace_type trace_type;
3521
3522 trace_type = *(ti_trace_type *)addr;
3523
3524 /*
3525 * Set tracing to whatever the user asked for. Setting
3526 * this register to 0 should have the effect of disabling
3527 * tracing.
3528 */
3529 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3530
3531 error = 0;
3532
3533 break;
3534 }
3535 case TIIOCGETTRACE: {
3536 struct ti_trace_buf *trace_buf;
3537 uint32_t trace_start, cur_trace_ptr, trace_len;
3538
3539 trace_buf = (struct ti_trace_buf *)addr;
3540
3541 TI_LOCK(sc);
3542 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3543 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3544 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3545
3546#if 0
3547 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3548 "trace_len = %d\n", trace_start,
3549 cur_trace_ptr, trace_len);
3550 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3551 trace_buf->buf_len);
3552#endif
3553
3554 error = ti_copy_mem(sc, trace_start, min(trace_len,
3555 trace_buf->buf_len),
3556 (caddr_t)trace_buf->buf, 1, 1);
3557
3558 if (error == 0) {
3559 trace_buf->fill_len = min(trace_len,
3560 trace_buf->buf_len);
3561 if (cur_trace_ptr < trace_start)
3562 trace_buf->cur_trace_ptr =
3563 trace_start - cur_trace_ptr;
3564 else
3565 trace_buf->cur_trace_ptr =
3566 cur_trace_ptr - trace_start;
3567 } else
3568 trace_buf->fill_len = 0;
3569 TI_UNLOCK(sc);
3570
3571 break;
3572 }
3573
3574 /*
3575 * For debugging, five ioctls are needed:
3576 * ALT_ATTACH
3577 * ALT_READ_TG_REG
3578 * ALT_WRITE_TG_REG
3579 * ALT_READ_TG_MEM
3580 * ALT_WRITE_TG_MEM
3581 */
3582 case ALT_ATTACH:
3583 /*
3584 * From what I can tell, Alteon's Solaris Tigon driver
3585 * only has one character device, so you have to attach
3586 * to the Tigon board you're interested in. This seems
3587 * like a not-so-good way to do things, since unless you
3588 * subsequently specify the unit number of the device
3589 * you're interested in every ioctl, you'll only be
3590 * able to debug one board at a time.
3591 */
3592 error = 0;
3593 break;
3594 case ALT_READ_TG_MEM:
3595 case ALT_WRITE_TG_MEM:
3596 {
3597 struct tg_mem *mem_param;
3598 uint32_t sram_end, scratch_end;
3599
3600 mem_param = (struct tg_mem *)addr;
3601
3602 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3603 sram_end = TI_END_SRAM_I;
3604 scratch_end = TI_END_SCRATCH_I;
3605 } else {
3606 sram_end = TI_END_SRAM_II;
3607 scratch_end = TI_END_SCRATCH_II;
3608 }
3609
3610 /*
3611 * For now, we'll only handle accessing regular SRAM,
3612 * nothing else.
3613 */
3614 TI_LOCK(sc);
3615 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3616 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3617 /*
3618 * In this instance, we always copy to/from user
3619 * space, so the user space argument is set to 1.
3620 */
3621 error = ti_copy_mem(sc, mem_param->tgAddr,
3622 mem_param->len,
3623 mem_param->userAddr, 1,
3624 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3625 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3626 && (mem_param->tgAddr <= scratch_end)) {
3627 error = ti_copy_scratch(sc, mem_param->tgAddr,
3628 mem_param->len,
3629 mem_param->userAddr, 1,
3630 (cmd == ALT_READ_TG_MEM) ?
3631 1 : 0, TI_PROCESSOR_A);
3632 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3633 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3634 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3635 if_printf(sc->ti_ifp,
3636 "invalid memory range for Tigon I\n");
3637 error = EINVAL;
3638 break;
3639 }
3640 error = ti_copy_scratch(sc, mem_param->tgAddr -
3641 TI_SCRATCH_DEBUG_OFF,
3642 mem_param->len,
3643 mem_param->userAddr, 1,
3644 (cmd == ALT_READ_TG_MEM) ?
3645 1 : 0, TI_PROCESSOR_B);
3646 } else {
3647 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3648 "out of supported range\n",
3649 mem_param->tgAddr, mem_param->len);
3650 error = EINVAL;
3651 }
3652 TI_UNLOCK(sc);
3653
3654 break;
3655 }
3656 case ALT_READ_TG_REG:
3657 case ALT_WRITE_TG_REG:
3658 {
3659 struct tg_reg *regs;
3660 uint32_t tmpval;
3661
3662 regs = (struct tg_reg *)addr;
3663
3664 /*
3665 * Make sure the address in question isn't out of range.
3666 */
3667 if (regs->addr > TI_REG_MAX) {
3668 error = EINVAL;
3669 break;
3670 }
3671 TI_LOCK(sc);
3672 if (cmd == ALT_READ_TG_REG) {
3673 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3674 regs->addr, &tmpval, 1);
3675 regs->data = ntohl(tmpval);
3676#if 0
3677 if ((regs->addr == TI_CPU_STATE)
3678 || (regs->addr == TI_CPU_CTL_B)) {
3679 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3680 regs->addr, tmpval);
3681 }
3682#endif
3683 } else {
3684 tmpval = htonl(regs->data);
3685 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3686 regs->addr, &tmpval, 1);
3687 }
3688 TI_UNLOCK(sc);
3689
3690 break;
3691 }
3692 default:
3693 error = ENOTTY;
3694 break;
3695 }
3696 return (error);
3697}
3698
3699static void
3700ti_watchdog(void *arg)
3701{
3702 struct ti_softc *sc;
3703 struct ifnet *ifp;
3704
3705 sc = arg;
3706 TI_LOCK_ASSERT(sc);
3707 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3708 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3709 return;
3710
3711 /*
3712 * When we're debugging, the chip is often stopped for long periods
3713 * of time, and that would normally cause the watchdog timer to fire.
3714 * Since that impedes debugging, we don't want to do that.
3715 */
3716 if (sc->ti_flags & TI_FLAG_DEBUGING)
3717 return;
3718
3719 ifp = sc->ti_ifp;
3720 if_printf(ifp, "watchdog timeout -- resetting\n");
3721 ti_stop(sc);
3722 ti_init_locked(sc);
3723
3724 ifp->if_oerrors++;
3725}
3726
3727/*
3728 * Stop the adapter and free any mbufs allocated to the
3729 * RX and TX lists.
3730 */
3731static void
3732ti_stop(struct ti_softc *sc)
3733{
3734 struct ifnet *ifp;
3735 struct ti_cmd_desc cmd;
3736
3737 TI_LOCK_ASSERT(sc);
3738
3739 ifp = sc->ti_ifp;
3740
3741 /* Disable host interrupts. */
3742 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3743 /*
3744 * Tell firmware we're shutting down.
3745 */
3746 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3747
3748 /* Halt and reinitialize. */
3749 if (ti_chipinit(sc) != 0)
3750 return;
3751 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3752 if (ti_chipinit(sc) != 0)
3753 return;
3754
3755 /* Free the RX lists. */
3756 ti_free_rx_ring_std(sc);
3757
3758 /* Free jumbo RX list. */
3759 ti_free_rx_ring_jumbo(sc);
3760
3761 /* Free mini RX list. */
3762 ti_free_rx_ring_mini(sc);
3763
3764 /* Free TX buffers. */
3765 ti_free_tx_ring(sc);
3766
3767 sc->ti_ev_prodidx.ti_idx = 0;
3768 sc->ti_return_prodidx.ti_idx = 0;
3769 sc->ti_tx_considx.ti_idx = 0;
3770 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3771
3772 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3773 callout_stop(&sc->ti_watchdog);
3774}
3775
3776/*
3777 * Stop all chip I/O so that the kernel's probe routines don't
3778 * get confused by errant DMAs when rebooting.
3779 */
3780static int
3781ti_shutdown(device_t dev)
3782{
3783 struct ti_softc *sc;
3784
3785 sc = device_get_softc(dev);
3786 TI_LOCK(sc);
3787 ti_chipinit(sc);
3788 TI_UNLOCK(sc);
3789
3790 return (0);
3791}
| 2485 /* Hook interrupt last to avoid having to lock softc */
2486 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2487 NULL, ti_intr, sc, &sc->ti_intrhand);
2488
2489 if (error) {
2490 device_printf(dev, "couldn't set up irq\n");
2491 goto fail;
2492 }
2493
2494fail:
2495 if (error)
2496 ti_detach(dev);
2497
2498 return (error);
2499}
2500
2501/*
2502 * Shutdown hardware and free up resources. This can be called any
2503 * time after the mutex has been initialized. It is called in both
2504 * the error case in attach and the normal detach case so it needs
2505 * to be careful about only freeing resources that have actually been
2506 * allocated.
2507 */
2508static int
2509ti_detach(device_t dev)
2510{
2511 struct ti_softc *sc;
2512 struct ifnet *ifp;
2513
2514 sc = device_get_softc(dev);
2515 if (sc->dev)
2516 destroy_dev(sc->dev);
2517 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2518 ifp = sc->ti_ifp;
2519 if (device_is_attached(dev)) {
2520 ether_ifdetach(ifp);
2521 TI_LOCK(sc);
2522 ti_stop(sc);
2523 TI_UNLOCK(sc);
2524 }
2525
2526 /* These should only be active if attach succeeded */
2527 callout_drain(&sc->ti_watchdog);
2528 bus_generic_detach(dev);
2529 ti_free_dmamaps(sc);
2530 ifmedia_removeall(&sc->ifmedia);
2531
2532#ifdef TI_PRIVATE_JUMBOS
2533 if (sc->ti_cdata.ti_jumbo_buf)
2534 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf,
2535 sc->ti_jumbo_dmamap);
2536#endif
2537 if (sc->ti_jumbo_dmat)
2538 bus_dma_tag_destroy(sc->ti_jumbo_dmat);
2539 if (sc->ti_mbuftx_dmat)
2540 bus_dma_tag_destroy(sc->ti_mbuftx_dmat);
2541 if (sc->ti_mbufrx_dmat)
2542 bus_dma_tag_destroy(sc->ti_mbufrx_dmat);
2543 if (sc->ti_rdata && sc->ti_rdata_dmamap)
2544 bus_dmamap_unload(sc->ti_rdata_dmat, sc->ti_rdata_dmamap);
2545 if (sc->ti_rdata)
2546 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2547 sc->ti_rdata_dmamap);
2548 if (sc->ti_rdata_dmat)
2549 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2550 if (sc->ti_parent_dmat)
2551 bus_dma_tag_destroy(sc->ti_parent_dmat);
2552 if (sc->ti_intrhand)
2553 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2554 if (sc->ti_irq)
2555 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2556 if (sc->ti_res) {
2557 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2558 sc->ti_res);
2559 }
2560 if (ifp)
2561 if_free(ifp);
2562
2563 mtx_destroy(&sc->ti_mtx);
2564
2565 return (0);
2566}
2567
2568#ifdef TI_JUMBO_HDRSPLIT
2569/*
2570 * If hdr_len is 0, that means that header splitting wasn't done on
2571 * this packet for some reason. The two most likely reasons are that
2572 * the protocol isn't a supported protocol for splitting, or this
2573 * packet had a fragment offset that wasn't 0.
2574 *
2575 * The header length, if it is non-zero, will always be the length of
2576 * the headers on the packet, but that length could be longer than the
2577 * first mbuf. So we take the minimum of the two as the actual
2578 * length.
2579 */
2580static __inline void
2581ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2582{
2583 int i = 0;
2584 int lengths[4] = {0, 0, 0, 0};
2585 struct mbuf *m, *mp;
2586
2587 if (hdr_len != 0)
2588 top->m_len = min(hdr_len, top->m_len);
2589 pkt_len -= top->m_len;
2590 lengths[i++] = top->m_len;
2591
2592 mp = top;
2593 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2594 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2595 pkt_len -= m->m_len;
2596 lengths[i++] = m->m_len;
2597 mp = m;
2598 }
2599
2600#if 0
2601 if (hdr_len != 0)
2602 printf("got split packet: ");
2603 else
2604 printf("got non-split packet: ");
2605
2606 printf("%d,%d,%d,%d = %d\n", lengths[0],
2607 lengths[1], lengths[2], lengths[3],
2608 lengths[0] + lengths[1] + lengths[2] +
2609 lengths[3]);
2610#endif
2611
2612 if (pkt_len)
2613 panic("header splitting didn't");
2614
2615 if (m) {
2616 m_freem(m);
2617 mp->m_next = NULL;
2618
2619 }
2620 if (mp->m_next != NULL)
2621 panic("ti_hdr_split: last mbuf in chain should be null");
2622}
2623#endif /* TI_JUMBO_HDRSPLIT */
2624
2625/*
2626 * Frame reception handling. This is called if there's a frame
2627 * on the receive return list.
2628 *
2629 * Note: we have to be able to handle three possibilities here:
2630 * 1) the frame is from the mini receive ring (can only happen)
2631 * on Tigon 2 boards)
2632 * 2) the frame is from the jumbo recieve ring
2633 * 3) the frame is from the standard receive ring
2634 */
2635
2636static void
2637ti_rxeof(struct ti_softc *sc)
2638{
2639 struct ifnet *ifp;
2640 bus_dmamap_t map;
2641 struct ti_cmd_desc cmd;
2642
2643 TI_LOCK_ASSERT(sc);
2644
2645 ifp = sc->ti_ifp;
2646
2647 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2648 struct ti_rx_desc *cur_rx;
2649 struct mbuf *m = NULL;
2650 uint32_t rxidx;
2651 uint16_t vlan_tag = 0;
2652 int have_tag = 0;
2653
2654 cur_rx =
2655 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2656 rxidx = cur_rx->ti_idx;
2657 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2658
2659 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2660 have_tag = 1;
2661 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2662 }
2663
2664 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2665
2666 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2667 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2668 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2669 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2670 bus_dmamap_sync(sc->ti_jumbo_dmat, map,
2671 BUS_DMASYNC_POSTREAD);
2672 bus_dmamap_unload(sc->ti_jumbo_dmat, map);
2673 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2674 ifp->if_ierrors++;
2675 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2676 continue;
2677 }
2678 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2679 ifp->if_ierrors++;
2680 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2681 continue;
2682 }
2683#ifdef TI_PRIVATE_JUMBOS
2684 m->m_len = cur_rx->ti_len;
2685#else /* TI_PRIVATE_JUMBOS */
2686#ifdef TI_JUMBO_HDRSPLIT
2687 if (sc->ti_hdrsplit)
2688 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2689 cur_rx->ti_len, rxidx);
2690 else
2691#endif /* TI_JUMBO_HDRSPLIT */
2692 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2693#endif /* TI_PRIVATE_JUMBOS */
2694 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2695 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2696 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2697 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2698 map = sc->ti_cdata.ti_rx_mini_maps[rxidx];
2699 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2700 BUS_DMASYNC_POSTREAD);
2701 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2702 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2703 ifp->if_ierrors++;
2704 ti_newbuf_mini(sc, sc->ti_mini, m);
2705 continue;
2706 }
2707 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2708 ifp->if_ierrors++;
2709 ti_newbuf_mini(sc, sc->ti_mini, m);
2710 continue;
2711 }
2712 m->m_len = cur_rx->ti_len;
2713 } else {
2714 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2715 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2716 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2717 map = sc->ti_cdata.ti_rx_std_maps[rxidx];
2718 bus_dmamap_sync(sc->ti_mbufrx_dmat, map,
2719 BUS_DMASYNC_POSTREAD);
2720 bus_dmamap_unload(sc->ti_mbufrx_dmat, map);
2721 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2722 ifp->if_ierrors++;
2723 ti_newbuf_std(sc, sc->ti_std, m);
2724 continue;
2725 }
2726 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2727 ifp->if_ierrors++;
2728 ti_newbuf_std(sc, sc->ti_std, m);
2729 continue;
2730 }
2731 m->m_len = cur_rx->ti_len;
2732 }
2733
2734 m->m_pkthdr.len = cur_rx->ti_len;
2735 ifp->if_ipackets++;
2736 m->m_pkthdr.rcvif = ifp;
2737
2738 if (ifp->if_hwassist) {
2739 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2740 CSUM_DATA_VALID;
2741 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2742 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2743 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2744 }
2745
2746 /*
2747 * If we received a packet with a vlan tag,
2748 * tag it before passing the packet upward.
2749 */
2750 if (have_tag) {
2751 m->m_pkthdr.ether_vtag = vlan_tag;
2752 m->m_flags |= M_VLANTAG;
2753 }
2754 TI_UNLOCK(sc);
2755 (*ifp->if_input)(ifp, m);
2756 TI_LOCK(sc);
2757 }
2758
2759 /* Only necessary on the Tigon 1. */
2760 if (sc->ti_hwrev == TI_HWREV_TIGON)
2761 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2762 sc->ti_rx_saved_considx);
2763
2764 TI_UPDATE_STDPROD(sc, sc->ti_std);
2765 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2766 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2767}
2768
2769static void
2770ti_txeof(struct ti_softc *sc)
2771{
2772 struct ti_txdesc *txd;
2773 struct ti_tx_desc txdesc;
2774 struct ti_tx_desc *cur_tx = NULL;
2775 struct ifnet *ifp;
2776 int idx;
2777
2778 ifp = sc->ti_ifp;
2779
2780 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2781 if (txd == NULL)
2782 return;
2783 /*
2784 * Go through our tx ring and free mbufs for those
2785 * frames that have been sent.
2786 */
2787 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2788 TI_INC(idx, TI_TX_RING_CNT)) {
2789 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2790 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2791 sizeof(txdesc), &txdesc);
2792 cur_tx = &txdesc;
2793 } else
2794 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2795 sc->ti_txcnt--;
2796 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2797 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2798 continue;
2799 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2800 BUS_DMASYNC_POSTWRITE);
2801 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2802
2803 ifp->if_opackets++;
2804 m_freem(txd->tx_m);
2805 txd->tx_m = NULL;
2806 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2807 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2808 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2809 }
2810 sc->ti_tx_saved_considx = idx;
2811
2812 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0;
2813}
2814
2815static void
2816ti_intr(void *xsc)
2817{
2818 struct ti_softc *sc;
2819 struct ifnet *ifp;
2820
2821 sc = xsc;
2822 TI_LOCK(sc);
2823 ifp = sc->ti_ifp;
2824
2825/*#ifdef notdef*/
2826 /* Avoid this for now -- checking this register is expensive. */
2827 /* Make sure this is really our interrupt. */
2828 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2829 TI_UNLOCK(sc);
2830 return;
2831 }
2832/*#endif*/
2833
2834 /* Ack interrupt and stop others from occuring. */
2835 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2836
2837 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2838 /* Check RX return ring producer/consumer */
2839 ti_rxeof(sc);
2840
2841 /* Check TX ring producer/consumer */
2842 ti_txeof(sc);
2843 }
2844
2845 ti_handle_events(sc);
2846
2847 /* Re-enable interrupts. */
2848 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2849
2850 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2851 ifp->if_snd.ifq_head != NULL)
2852 ti_start_locked(ifp);
2853
2854 TI_UNLOCK(sc);
2855}
2856
2857static void
2858ti_stats_update(struct ti_softc *sc)
2859{
2860 struct ifnet *ifp;
2861
2862 ifp = sc->ti_ifp;
2863
2864 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2865 BUS_DMASYNC_POSTREAD);
2866
2867 ifp->if_collisions +=
2868 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2869 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2870 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2871 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2872 ifp->if_collisions;
2873
2874 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2875 BUS_DMASYNC_PREREAD);
2876}
2877
2878/*
2879 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2880 * pointers to descriptors.
2881 */
2882static int
2883ti_encap(struct ti_softc *sc, struct mbuf **m_head)
2884{
2885 struct ti_txdesc *txd;
2886 struct ti_tx_desc *f;
2887 struct ti_tx_desc txdesc;
2888 struct mbuf *m;
2889 bus_dma_segment_t txsegs[TI_MAXTXSEGS];
2890 uint16_t csum_flags;
2891 int error, frag, i, nseg;
2892
2893 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
2894 return (ENOBUFS);
2895
2896 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2897 *m_head, txsegs, &nseg, 0);
2898 if (error == EFBIG) {
2899 m = m_defrag(*m_head, M_DONTWAIT);
2900 if (m == NULL) {
2901 m_freem(*m_head);
2902 *m_head = NULL;
2903 return (ENOMEM);
2904 }
2905 *m_head = m;
2906 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat,
2907 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2908 if (error) {
2909 m_freem(*m_head);
2910 *m_head = NULL;
2911 return (error);
2912 }
2913 } else if (error != 0)
2914 return (error);
2915 if (nseg == 0) {
2916 m_freem(*m_head);
2917 *m_head = NULL;
2918 return (EIO);
2919 }
2920
2921 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
2922 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap);
2923 return (ENOBUFS);
2924 }
2925
2926 m = *m_head;
2927 csum_flags = 0;
2928 if (m->m_pkthdr.csum_flags) {
2929 if (m->m_pkthdr.csum_flags & CSUM_IP)
2930 csum_flags |= TI_BDFLAG_IP_CKSUM;
2931 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2932 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2933 if (m->m_flags & M_LASTFRAG)
2934 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2935 else if (m->m_flags & M_FRAG)
2936 csum_flags |= TI_BDFLAG_IP_FRAG;
2937 }
2938
2939 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap,
2940 BUS_DMASYNC_PREWRITE);
2941 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2942 BUS_DMASYNC_PREWRITE);
2943
2944 frag = sc->ti_tx_saved_prodidx;
2945 for (i = 0; i < nseg; i++) {
2946 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2947 bzero(&txdesc, sizeof(txdesc));
2948 f = &txdesc;
2949 } else
2950 f = &sc->ti_rdata->ti_tx_ring[frag];
2951 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
2952 f->ti_len = txsegs[i].ds_len;
2953 f->ti_flags = csum_flags;
2954 if (m->m_flags & M_VLANTAG) {
2955 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2956 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff;
2957 } else {
2958 f->ti_vlan_tag = 0;
2959 }
2960
2961 if (sc->ti_hwrev == TI_HWREV_TIGON)
2962 ti_mem_write(sc, TI_TX_RING_BASE + frag *
2963 sizeof(txdesc), sizeof(txdesc), &txdesc);
2964 TI_INC(frag, TI_TX_RING_CNT);
2965 }
2966
2967 sc->ti_tx_saved_prodidx = frag;
2968 /* set TI_BDFLAG_END on the last descriptor */
2969 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
2970 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2971 txdesc.ti_flags |= TI_BDFLAG_END;
2972 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
2973 sizeof(txdesc), &txdesc);
2974 } else
2975 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
2976
2977 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
2978 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
2979 txd->tx_m = m;
2980 sc->ti_txcnt += nseg;
2981
2982 return (0);
2983}
2984
2985static void
2986ti_start(struct ifnet *ifp)
2987{
2988 struct ti_softc *sc;
2989
2990 sc = ifp->if_softc;
2991 TI_LOCK(sc);
2992 ti_start_locked(ifp);
2993 TI_UNLOCK(sc);
2994}
2995
2996/*
2997 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2998 * to the mbuf data regions directly in the transmit descriptors.
2999 */
3000static void
3001ti_start_locked(struct ifnet *ifp)
3002{
3003 struct ti_softc *sc;
3004 struct mbuf *m_head = NULL;
3005 int enq = 0;
3006
3007 sc = ifp->if_softc;
3008
3009 for (; ifp->if_snd.ifq_head != NULL &&
3010 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3011 IF_DEQUEUE(&ifp->if_snd, m_head);
3012 if (m_head == NULL)
3013 break;
3014
3015 /*
3016 * XXX
3017 * safety overkill. If this is a fragmented packet chain
3018 * with delayed TCP/UDP checksums, then only encapsulate
3019 * it if we have enough descriptors to handle the entire
3020 * chain at once.
3021 * (paranoia -- may not actually be needed)
3022 */
3023 if (m_head->m_flags & M_FIRSTFRAG &&
3024 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3025 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
3026 m_head->m_pkthdr.csum_data + 16) {
3027 IF_PREPEND(&ifp->if_snd, m_head);
3028 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3029 break;
3030 }
3031 }
3032
3033 /*
3034 * Pack the data into the transmit ring. If we
3035 * don't have room, set the OACTIVE flag and wait
3036 * for the NIC to drain the ring.
3037 */
3038 if (ti_encap(sc, &m_head)) {
3039 if (m_head == NULL)
3040 break;
3041 IF_PREPEND(&ifp->if_snd, m_head);
3042 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3043 break;
3044 }
3045
3046 enq++;
3047 /*
3048 * If there's a BPF listener, bounce a copy of this frame
3049 * to him.
3050 */
3051 ETHER_BPF_MTAP(ifp, m_head);
3052 }
3053
3054 if (enq > 0) {
3055 /* Transmit */
3056 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3057
3058 /*
3059 * Set a timeout in case the chip goes out to lunch.
3060 */
3061 sc->ti_timer = 5;
3062 }
3063}
3064
3065static void
3066ti_init(void *xsc)
3067{
3068 struct ti_softc *sc;
3069
3070 sc = xsc;
3071 TI_LOCK(sc);
3072 ti_init_locked(sc);
3073 TI_UNLOCK(sc);
3074}
3075
3076static void
3077ti_init_locked(void *xsc)
3078{
3079 struct ti_softc *sc = xsc;
3080
3081 /* Cancel pending I/O and flush buffers. */
3082 ti_stop(sc);
3083
3084 /* Init the gen info block, ring control blocks and firmware. */
3085 if (ti_gibinit(sc)) {
3086 device_printf(sc->ti_dev, "initialization failure\n");
3087 return;
3088 }
3089}
3090
3091static void ti_init2(struct ti_softc *sc)
3092{
3093 struct ti_cmd_desc cmd;
3094 struct ifnet *ifp;
3095 uint8_t *ea;
3096 struct ifmedia *ifm;
3097 int tmp;
3098
3099 TI_LOCK_ASSERT(sc);
3100
3101 ifp = sc->ti_ifp;
3102
3103 /* Specify MTU and interface index. */
3104 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
3105 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3106 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3107 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3108
3109 /* Load our MAC address. */
3110 ea = IF_LLADDR(sc->ti_ifp);
3111 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3112 CSR_WRITE_4(sc, TI_GCR_PAR1,
3113 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3114 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3115
3116 /* Enable or disable promiscuous mode as needed. */
3117 if (ifp->if_flags & IFF_PROMISC) {
3118 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3119 } else {
3120 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3121 }
3122
3123 /* Program multicast filter. */
3124 ti_setmulti(sc);
3125
3126 /*
3127 * If this is a Tigon 1, we should tell the
3128 * firmware to use software packet filtering.
3129 */
3130 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3131 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3132 }
3133
3134 /* Init RX ring. */
3135 ti_init_rx_ring_std(sc);
3136
3137 /* Init jumbo RX ring. */
3138 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3139 ti_init_rx_ring_jumbo(sc);
3140
3141 /*
3142 * If this is a Tigon 2, we can also configure the
3143 * mini ring.
3144 */
3145 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
3146 ti_init_rx_ring_mini(sc);
3147
3148 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3149 sc->ti_rx_saved_considx = 0;
3150
3151 /* Init TX ring. */
3152 ti_init_tx_ring(sc);
3153
3154 /* Tell firmware we're alive. */
3155 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3156
3157 /* Enable host interrupts. */
3158 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3159
3160 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3161 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3162 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3163
3164 /*
3165 * Make sure to set media properly. We have to do this
3166 * here since we have to issue commands in order to set
3167 * the link negotiation and we can't issue commands until
3168 * the firmware is running.
3169 */
3170 ifm = &sc->ifmedia;
3171 tmp = ifm->ifm_media;
3172 ifm->ifm_media = ifm->ifm_cur->ifm_media;
3173 ti_ifmedia_upd(ifp);
3174 ifm->ifm_media = tmp;
3175}
3176
3177/*
3178 * Set media options.
3179 */
3180static int
3181ti_ifmedia_upd(struct ifnet *ifp)
3182{
3183 struct ti_softc *sc;
3184 struct ifmedia *ifm;
3185 struct ti_cmd_desc cmd;
3186 uint32_t flowctl;
3187
3188 sc = ifp->if_softc;
3189 ifm = &sc->ifmedia;
3190
3191 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3192 return (EINVAL);
3193
3194 flowctl = 0;
3195
3196 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3197 case IFM_AUTO:
3198 /*
3199 * Transmit flow control doesn't work on the Tigon 1.
3200 */
3201 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3202
3203 /*
3204 * Transmit flow control can also cause problems on the
3205 * Tigon 2, apparantly with both the copper and fiber
3206 * boards. The symptom is that the interface will just
3207 * hang. This was reproduced with Alteon 180 switches.
3208 */
3209#if 0
3210 if (sc->ti_hwrev != TI_HWREV_TIGON)
3211 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3212#endif
3213
3214 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3215 TI_GLNK_FULL_DUPLEX| flowctl |
3216 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3217
3218 flowctl = TI_LNK_RX_FLOWCTL_Y;
3219#if 0
3220 if (sc->ti_hwrev != TI_HWREV_TIGON)
3221 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3222#endif
3223
3224 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3225 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3226 TI_LNK_AUTONEGENB|TI_LNK_ENB);
3227 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3228 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3229 break;
3230 case IFM_1000_SX:
3231 case IFM_1000_T:
3232 flowctl = TI_GLNK_RX_FLOWCTL_Y;
3233#if 0
3234 if (sc->ti_hwrev != TI_HWREV_TIGON)
3235 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3236#endif
3237
3238 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3239 flowctl |TI_GLNK_ENB);
3240 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3241 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3242 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3243 }
3244 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3245 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3246 break;
3247 case IFM_100_FX:
3248 case IFM_10_FL:
3249 case IFM_100_TX:
3250 case IFM_10_T:
3251 flowctl = TI_LNK_RX_FLOWCTL_Y;
3252#if 0
3253 if (sc->ti_hwrev != TI_HWREV_TIGON)
3254 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3255#endif
3256
3257 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3258 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3259 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3260 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3261 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3262 } else {
3263 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3264 }
3265 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3266 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3267 } else {
3268 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3269 }
3270 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3271 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3272 break;
3273 }
3274
3275 return (0);
3276}
3277
3278/*
3279 * Report current media status.
3280 */
3281static void
3282ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3283{
3284 struct ti_softc *sc;
3285 uint32_t media = 0;
3286
3287 sc = ifp->if_softc;
3288
3289 ifmr->ifm_status = IFM_AVALID;
3290 ifmr->ifm_active = IFM_ETHER;
3291
3292 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3293 return;
3294
3295 ifmr->ifm_status |= IFM_ACTIVE;
3296
3297 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3298 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3299 if (sc->ti_copper)
3300 ifmr->ifm_active |= IFM_1000_T;
3301 else
3302 ifmr->ifm_active |= IFM_1000_SX;
3303 if (media & TI_GLNK_FULL_DUPLEX)
3304 ifmr->ifm_active |= IFM_FDX;
3305 else
3306 ifmr->ifm_active |= IFM_HDX;
3307 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3308 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3309 if (sc->ti_copper) {
3310 if (media & TI_LNK_100MB)
3311 ifmr->ifm_active |= IFM_100_TX;
3312 if (media & TI_LNK_10MB)
3313 ifmr->ifm_active |= IFM_10_T;
3314 } else {
3315 if (media & TI_LNK_100MB)
3316 ifmr->ifm_active |= IFM_100_FX;
3317 if (media & TI_LNK_10MB)
3318 ifmr->ifm_active |= IFM_10_FL;
3319 }
3320 if (media & TI_LNK_FULL_DUPLEX)
3321 ifmr->ifm_active |= IFM_FDX;
3322 if (media & TI_LNK_HALF_DUPLEX)
3323 ifmr->ifm_active |= IFM_HDX;
3324 }
3325}
3326
3327static int
3328ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3329{
3330 struct ti_softc *sc = ifp->if_softc;
3331 struct ifreq *ifr = (struct ifreq *) data;
3332 struct ti_cmd_desc cmd;
3333 int mask, error = 0;
3334
3335 switch (command) {
3336 case SIOCSIFMTU:
3337 TI_LOCK(sc);
3338 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3339 error = EINVAL;
3340 else {
3341 ifp->if_mtu = ifr->ifr_mtu;
3342 ti_init_locked(sc);
3343 }
3344 TI_UNLOCK(sc);
3345 break;
3346 case SIOCSIFFLAGS:
3347 TI_LOCK(sc);
3348 if (ifp->if_flags & IFF_UP) {
3349 /*
3350 * If only the state of the PROMISC flag changed,
3351 * then just use the 'set promisc mode' command
3352 * instead of reinitializing the entire NIC. Doing
3353 * a full re-init means reloading the firmware and
3354 * waiting for it to start up, which may take a
3355 * second or two.
3356 */
3357 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3358 ifp->if_flags & IFF_PROMISC &&
3359 !(sc->ti_if_flags & IFF_PROMISC)) {
3360 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3361 TI_CMD_CODE_PROMISC_ENB, 0);
3362 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3363 !(ifp->if_flags & IFF_PROMISC) &&
3364 sc->ti_if_flags & IFF_PROMISC) {
3365 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3366 TI_CMD_CODE_PROMISC_DIS, 0);
3367 } else
3368 ti_init_locked(sc);
3369 } else {
3370 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3371 ti_stop(sc);
3372 }
3373 }
3374 sc->ti_if_flags = ifp->if_flags;
3375 TI_UNLOCK(sc);
3376 break;
3377 case SIOCADDMULTI:
3378 case SIOCDELMULTI:
3379 TI_LOCK(sc);
3380 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3381 ti_setmulti(sc);
3382 TI_UNLOCK(sc);
3383 break;
3384 case SIOCSIFMEDIA:
3385 case SIOCGIFMEDIA:
3386 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3387 break;
3388 case SIOCSIFCAP:
3389 TI_LOCK(sc);
3390 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3391 if (mask & IFCAP_HWCSUM) {
3392 if (IFCAP_HWCSUM & ifp->if_capenable)
3393 ifp->if_capenable &= ~IFCAP_HWCSUM;
3394 else
3395 ifp->if_capenable |= IFCAP_HWCSUM;
3396 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3397 ti_init_locked(sc);
3398 }
3399 TI_UNLOCK(sc);
3400 break;
3401 default:
3402 error = ether_ioctl(ifp, command, data);
3403 break;
3404 }
3405
3406 return (error);
3407}
3408
3409static int
3410ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3411{
3412 struct ti_softc *sc;
3413
3414 sc = dev->si_drv1;
3415 if (sc == NULL)
3416 return (ENODEV);
3417
3418 TI_LOCK(sc);
3419 sc->ti_flags |= TI_FLAG_DEBUGING;
3420 TI_UNLOCK(sc);
3421
3422 return (0);
3423}
3424
3425static int
3426ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3427{
3428 struct ti_softc *sc;
3429
3430 sc = dev->si_drv1;
3431 if (sc == NULL)
3432 return (ENODEV);
3433
3434 TI_LOCK(sc);
3435 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3436 TI_UNLOCK(sc);
3437
3438 return (0);
3439}
3440
3441/*
3442 * This ioctl routine goes along with the Tigon character device.
3443 */
3444static int
3445ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3446 struct thread *td)
3447{
3448 struct ti_softc *sc;
3449 int error;
3450
3451 sc = dev->si_drv1;
3452 if (sc == NULL)
3453 return (ENODEV);
3454
3455 error = 0;
3456
3457 switch (cmd) {
3458 case TIIOCGETSTATS:
3459 {
3460 struct ti_stats *outstats;
3461
3462 outstats = (struct ti_stats *)addr;
3463
3464 TI_LOCK(sc);
3465 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3466 sizeof(struct ti_stats));
3467 TI_UNLOCK(sc);
3468 break;
3469 }
3470 case TIIOCGETPARAMS:
3471 {
3472 struct ti_params *params;
3473
3474 params = (struct ti_params *)addr;
3475
3476 TI_LOCK(sc);
3477 params->ti_stat_ticks = sc->ti_stat_ticks;
3478 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3479 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3480 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3481 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3482 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3483 params->param_mask = TI_PARAM_ALL;
3484 TI_UNLOCK(sc);
3485
3486 error = 0;
3487
3488 break;
3489 }
3490 case TIIOCSETPARAMS:
3491 {
3492 struct ti_params *params;
3493
3494 params = (struct ti_params *)addr;
3495
3496 TI_LOCK(sc);
3497 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3498 sc->ti_stat_ticks = params->ti_stat_ticks;
3499 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3500 }
3501
3502 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3503 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3504 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3505 sc->ti_rx_coal_ticks);
3506 }
3507
3508 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3509 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3510 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3511 sc->ti_tx_coal_ticks);
3512 }
3513
3514 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3515 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3516 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3517 sc->ti_rx_max_coal_bds);
3518 }
3519
3520 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3521 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3522 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3523 sc->ti_tx_max_coal_bds);
3524 }
3525
3526 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3527 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3528 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3529 sc->ti_tx_buf_ratio);
3530 }
3531 TI_UNLOCK(sc);
3532
3533 error = 0;
3534
3535 break;
3536 }
3537 case TIIOCSETTRACE: {
3538 ti_trace_type trace_type;
3539
3540 trace_type = *(ti_trace_type *)addr;
3541
3542 /*
3543 * Set tracing to whatever the user asked for. Setting
3544 * this register to 0 should have the effect of disabling
3545 * tracing.
3546 */
3547 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3548
3549 error = 0;
3550
3551 break;
3552 }
3553 case TIIOCGETTRACE: {
3554 struct ti_trace_buf *trace_buf;
3555 uint32_t trace_start, cur_trace_ptr, trace_len;
3556
3557 trace_buf = (struct ti_trace_buf *)addr;
3558
3559 TI_LOCK(sc);
3560 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3561 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3562 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3563
3564#if 0
3565 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3566 "trace_len = %d\n", trace_start,
3567 cur_trace_ptr, trace_len);
3568 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3569 trace_buf->buf_len);
3570#endif
3571
3572 error = ti_copy_mem(sc, trace_start, min(trace_len,
3573 trace_buf->buf_len),
3574 (caddr_t)trace_buf->buf, 1, 1);
3575
3576 if (error == 0) {
3577 trace_buf->fill_len = min(trace_len,
3578 trace_buf->buf_len);
3579 if (cur_trace_ptr < trace_start)
3580 trace_buf->cur_trace_ptr =
3581 trace_start - cur_trace_ptr;
3582 else
3583 trace_buf->cur_trace_ptr =
3584 cur_trace_ptr - trace_start;
3585 } else
3586 trace_buf->fill_len = 0;
3587 TI_UNLOCK(sc);
3588
3589 break;
3590 }
3591
3592 /*
3593 * For debugging, five ioctls are needed:
3594 * ALT_ATTACH
3595 * ALT_READ_TG_REG
3596 * ALT_WRITE_TG_REG
3597 * ALT_READ_TG_MEM
3598 * ALT_WRITE_TG_MEM
3599 */
3600 case ALT_ATTACH:
3601 /*
3602 * From what I can tell, Alteon's Solaris Tigon driver
3603 * only has one character device, so you have to attach
3604 * to the Tigon board you're interested in. This seems
3605 * like a not-so-good way to do things, since unless you
3606 * subsequently specify the unit number of the device
3607 * you're interested in every ioctl, you'll only be
3608 * able to debug one board at a time.
3609 */
3610 error = 0;
3611 break;
3612 case ALT_READ_TG_MEM:
3613 case ALT_WRITE_TG_MEM:
3614 {
3615 struct tg_mem *mem_param;
3616 uint32_t sram_end, scratch_end;
3617
3618 mem_param = (struct tg_mem *)addr;
3619
3620 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3621 sram_end = TI_END_SRAM_I;
3622 scratch_end = TI_END_SCRATCH_I;
3623 } else {
3624 sram_end = TI_END_SRAM_II;
3625 scratch_end = TI_END_SCRATCH_II;
3626 }
3627
3628 /*
3629 * For now, we'll only handle accessing regular SRAM,
3630 * nothing else.
3631 */
3632 TI_LOCK(sc);
3633 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3634 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3635 /*
3636 * In this instance, we always copy to/from user
3637 * space, so the user space argument is set to 1.
3638 */
3639 error = ti_copy_mem(sc, mem_param->tgAddr,
3640 mem_param->len,
3641 mem_param->userAddr, 1,
3642 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3643 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3644 && (mem_param->tgAddr <= scratch_end)) {
3645 error = ti_copy_scratch(sc, mem_param->tgAddr,
3646 mem_param->len,
3647 mem_param->userAddr, 1,
3648 (cmd == ALT_READ_TG_MEM) ?
3649 1 : 0, TI_PROCESSOR_A);
3650 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3651 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3652 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3653 if_printf(sc->ti_ifp,
3654 "invalid memory range for Tigon I\n");
3655 error = EINVAL;
3656 break;
3657 }
3658 error = ti_copy_scratch(sc, mem_param->tgAddr -
3659 TI_SCRATCH_DEBUG_OFF,
3660 mem_param->len,
3661 mem_param->userAddr, 1,
3662 (cmd == ALT_READ_TG_MEM) ?
3663 1 : 0, TI_PROCESSOR_B);
3664 } else {
3665 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3666 "out of supported range\n",
3667 mem_param->tgAddr, mem_param->len);
3668 error = EINVAL;
3669 }
3670 TI_UNLOCK(sc);
3671
3672 break;
3673 }
3674 case ALT_READ_TG_REG:
3675 case ALT_WRITE_TG_REG:
3676 {
3677 struct tg_reg *regs;
3678 uint32_t tmpval;
3679
3680 regs = (struct tg_reg *)addr;
3681
3682 /*
3683 * Make sure the address in question isn't out of range.
3684 */
3685 if (regs->addr > TI_REG_MAX) {
3686 error = EINVAL;
3687 break;
3688 }
3689 TI_LOCK(sc);
3690 if (cmd == ALT_READ_TG_REG) {
3691 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3692 regs->addr, &tmpval, 1);
3693 regs->data = ntohl(tmpval);
3694#if 0
3695 if ((regs->addr == TI_CPU_STATE)
3696 || (regs->addr == TI_CPU_CTL_B)) {
3697 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3698 regs->addr, tmpval);
3699 }
3700#endif
3701 } else {
3702 tmpval = htonl(regs->data);
3703 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3704 regs->addr, &tmpval, 1);
3705 }
3706 TI_UNLOCK(sc);
3707
3708 break;
3709 }
3710 default:
3711 error = ENOTTY;
3712 break;
3713 }
3714 return (error);
3715}
3716
3717static void
3718ti_watchdog(void *arg)
3719{
3720 struct ti_softc *sc;
3721 struct ifnet *ifp;
3722
3723 sc = arg;
3724 TI_LOCK_ASSERT(sc);
3725 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3726 if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3727 return;
3728
3729 /*
3730 * When we're debugging, the chip is often stopped for long periods
3731 * of time, and that would normally cause the watchdog timer to fire.
3732 * Since that impedes debugging, we don't want to do that.
3733 */
3734 if (sc->ti_flags & TI_FLAG_DEBUGING)
3735 return;
3736
3737 ifp = sc->ti_ifp;
3738 if_printf(ifp, "watchdog timeout -- resetting\n");
3739 ti_stop(sc);
3740 ti_init_locked(sc);
3741
3742 ifp->if_oerrors++;
3743}
3744
3745/*
3746 * Stop the adapter and free any mbufs allocated to the
3747 * RX and TX lists.
3748 */
3749static void
3750ti_stop(struct ti_softc *sc)
3751{
3752 struct ifnet *ifp;
3753 struct ti_cmd_desc cmd;
3754
3755 TI_LOCK_ASSERT(sc);
3756
3757 ifp = sc->ti_ifp;
3758
3759 /* Disable host interrupts. */
3760 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3761 /*
3762 * Tell firmware we're shutting down.
3763 */
3764 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3765
3766 /* Halt and reinitialize. */
3767 if (ti_chipinit(sc) != 0)
3768 return;
3769 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3770 if (ti_chipinit(sc) != 0)
3771 return;
3772
3773 /* Free the RX lists. */
3774 ti_free_rx_ring_std(sc);
3775
3776 /* Free jumbo RX list. */
3777 ti_free_rx_ring_jumbo(sc);
3778
3779 /* Free mini RX list. */
3780 ti_free_rx_ring_mini(sc);
3781
3782 /* Free TX buffers. */
3783 ti_free_tx_ring(sc);
3784
3785 sc->ti_ev_prodidx.ti_idx = 0;
3786 sc->ti_return_prodidx.ti_idx = 0;
3787 sc->ti_tx_considx.ti_idx = 0;
3788 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3789
3790 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3791 callout_stop(&sc->ti_watchdog);
3792}
3793
3794/*
3795 * Stop all chip I/O so that the kernel's probe routines don't
3796 * get confused by errant DMAs when rebooting.
3797 */
3798static int
3799ti_shutdown(device_t dev)
3800{
3801 struct ti_softc *sc;
3802
3803 sc = device_get_softc(dev);
3804 TI_LOCK(sc);
3805 ti_chipinit(sc);
3806 TI_UNLOCK(sc);
3807
3808 return (0);
3809}
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