81
82#include "opt_ti.h"
83
84#include <sys/param.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#include <sys/module.h>
91#include <sys/socket.h>
92#include <sys/queue.h>
93#include <sys/conf.h>
94
95#include <net/if.h>
96#include <net/if_arp.h>
97#include <net/ethernet.h>
98#include <net/if_dl.h>
99#include <net/if_media.h>
100#include <net/if_types.h>
101#include <net/if_vlan_var.h>
102
103#include <net/bpf.h>
104
105#include <netinet/in_systm.h>
106#include <netinet/in.h>
107#include <netinet/ip.h>
108
109#include <vm/vm.h> /* for vtophys */
110#include <vm/pmap.h> /* for vtophys */
111#include <machine/bus_memio.h>
112#include <machine/bus.h>
113#include <machine/resource.h>
114#include <sys/bus.h>
115#include <sys/rman.h>
116
117/* #define TI_PRIVATE_JUMBOS */
118
119#if !defined(TI_PRIVATE_JUMBOS)
120#include <sys/sockio.h>
121#include <sys/uio.h>
122#include <sys/lock.h>
123#include <sys/sf_buf.h>
124#include <vm/vm_extern.h>
125#include <vm/pmap.h>
126#include <vm/vm_map.h>
127#include <vm/vm_map.h>
128#include <vm/vm_param.h>
129#include <vm/vm_pageout.h>
130#include <sys/vmmeter.h>
131#include <vm/vm_page.h>
132#include <vm/vm_object.h>
133#include <vm/vm_kern.h>
134#include <sys/proc.h>
135#endif /* !TI_PRIVATE_JUMBOS */
136
137#include <dev/pci/pcireg.h>
138#include <dev/pci/pcivar.h>
139
140#include <sys/tiio.h>
141#include <pci/if_tireg.h>
142#include <pci/ti_fw.h>
143#include <pci/ti_fw2.h>
144
145#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
146/*
147 * We can only turn on header splitting if we're using extended receive
148 * BDs.
149 */
150#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
151#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
152#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
153
154struct ti_softc *tis[8];
155
156typedef enum {
157 TI_SWAP_HTON,
158 TI_SWAP_NTOH
159} ti_swap_type;
160
161
162/*
163 * Various supported device vendors/types and their names.
164 */
165
166static struct ti_type ti_devs[] = {
167 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
170 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
171 { TC_VENDORID, TC_DEVICEID_3C985,
172 "3Com 3c985-SX Gigabit Ethernet" },
173 { NG_VENDORID, NG_DEVICEID_GA620,
174 "Netgear GA620 1000baseSX Gigabit Ethernet" },
175 { NG_VENDORID, NG_DEVICEID_GA620T,
176 "Netgear GA620 1000baseT Gigabit Ethernet" },
177 { SGI_VENDORID, SGI_DEVICEID_TIGON,
178 "Silicon Graphics Gigabit Ethernet" },
179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
180 "Farallon PN9000SX Gigabit Ethernet" },
181 { 0, 0, NULL }
182};
183
184
185static d_open_t ti_open;
186static d_close_t ti_close;
187static d_ioctl_t ti_ioctl2;
188
189static struct cdevsw ti_cdevsw = {
190 .d_version = D_VERSION,
191 .d_flags = D_NEEDGIANT,
192 .d_open = ti_open,
193 .d_close = ti_close,
194 .d_ioctl = ti_ioctl2,
195 .d_name = "ti",
196};
197
198static int ti_probe(device_t);
199static int ti_attach(device_t);
200static int ti_detach(device_t);
201static void ti_txeof(struct ti_softc *);
202static void ti_rxeof(struct ti_softc *);
203
204static void ti_stats_update(struct ti_softc *);
205static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
206
207static void ti_intr(void *);
208static void ti_start(struct ifnet *);
209static int ti_ioctl(struct ifnet *, u_long, caddr_t);
210static void ti_init(void *);
211static void ti_init2(struct ti_softc *);
212static void ti_stop(struct ti_softc *);
213static void ti_watchdog(struct ifnet *);
214static void ti_shutdown(device_t);
215static int ti_ifmedia_upd(struct ifnet *);
216static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
217
218static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
219static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
220static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
221
222static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
223static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
224static void ti_setmulti(struct ti_softc *);
225
226static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
227static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
228static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
229 int, int, int);
230static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
231static void ti_loadfw(struct ti_softc *);
232static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
233static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
234static void ti_handle_events(struct ti_softc *);
235#ifdef TI_PRIVATE_JUMBOS
236static int ti_alloc_jumbo_mem(struct ti_softc *);
237static void *ti_jalloc(struct ti_softc *);
238static void ti_jfree(void *, void *);
239#endif /* TI_PRIVATE_JUMBOS */
240static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
241static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
242static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
243static int ti_init_rx_ring_std(struct ti_softc *);
244static void ti_free_rx_ring_std(struct ti_softc *);
245static int ti_init_rx_ring_jumbo(struct ti_softc *);
246static void ti_free_rx_ring_jumbo(struct ti_softc *);
247static int ti_init_rx_ring_mini(struct ti_softc *);
248static void ti_free_rx_ring_mini(struct ti_softc *);
249static void ti_free_tx_ring(struct ti_softc *);
250static int ti_init_tx_ring(struct ti_softc *);
251
252static int ti_64bitslot_war(struct ti_softc *);
253static int ti_chipinit(struct ti_softc *);
254static int ti_gibinit(struct ti_softc *);
255
256#ifdef TI_JUMBO_HDRSPLIT
257static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
258 int pkt_len, int idx);
259#endif /* TI_JUMBO_HDRSPLIT */
260
261static device_method_t ti_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, ti_probe),
264 DEVMETHOD(device_attach, ti_attach),
265 DEVMETHOD(device_detach, ti_detach),
266 DEVMETHOD(device_shutdown, ti_shutdown),
267 { 0, 0 }
268};
269
270static driver_t ti_driver = {
271 "ti",
272 ti_methods,
273 sizeof(struct ti_softc)
274};
275
276static devclass_t ti_devclass;
277
278DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
279MODULE_DEPEND(ti, pci, 1, 1, 1);
280MODULE_DEPEND(ti, ether, 1, 1, 1);
281
282/*
283 * Send an instruction or address to the EEPROM, check for ACK.
284 */
285static u_int32_t ti_eeprom_putbyte(sc, byte)
286 struct ti_softc *sc;
287 int byte;
288{
289 register int i, ack = 0;
290
291 /*
292 * Make sure we're in TX mode.
293 */
294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
295
296 /*
297 * Feed in each bit and stobe the clock.
298 */
299 for (i = 0x80; i; i >>= 1) {
300 if (byte & i) {
301 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 } else {
303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
304 }
305 DELAY(1);
306 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 DELAY(1);
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
309 }
310
311 /*
312 * Turn off TX mode.
313 */
314 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
315
316 /*
317 * Check for ack.
318 */
319 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
320 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
321 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
322
323 return (ack);
324}
325
326/*
327 * Read a byte of data stored in the EEPROM at address 'addr.'
328 * We have to send two address bytes since the EEPROM can hold
329 * more than 256 bytes of data.
330 */
331static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
332 struct ti_softc *sc;
333 int addr;
334 u_int8_t *dest;
335{
336 register int i;
337 u_int8_t byte = 0;
338
339 EEPROM_START;
340
341 /*
342 * Send write control code to EEPROM.
343 */
344 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
345 printf("ti%d: failed to send write command, status: %x\n",
346 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
347 return (1);
348 }
349
350 /*
351 * Send first byte of address of byte we want to read.
352 */
353 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
354 printf("ti%d: failed to send address, status: %x\n",
355 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
356 return (1);
357 }
358 /*
359 * Send second byte address of byte we want to read.
360 */
361 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
362 printf("ti%d: failed to send address, status: %x\n",
363 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
364 return (1);
365 }
366
367 EEPROM_STOP;
368 EEPROM_START;
369 /*
370 * Send read control code to EEPROM.
371 */
372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
373 printf("ti%d: failed to send read command, status: %x\n",
374 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
375 return (1);
376 }
377
378 /*
379 * Start reading bits from EEPROM.
380 */
381 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
382 for (i = 0x80; i; i >>= 1) {
383 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
384 DELAY(1);
385 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
386 byte |= i;
387 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
388 DELAY(1);
389 }
390
391 EEPROM_STOP;
392
393 /*
394 * No ACK generated for read, so just return byte.
395 */
396
397 *dest = byte;
398
399 return (0);
400}
401
402/*
403 * Read a sequence of bytes from the EEPROM.
404 */
405static int
406ti_read_eeprom(sc, dest, off, cnt)
407 struct ti_softc *sc;
408 caddr_t dest;
409 int off;
410 int cnt;
411{
412 int err = 0, i;
413 u_int8_t byte = 0;
414
415 for (i = 0; i < cnt; i++) {
416 err = ti_eeprom_getbyte(sc, off + i, &byte);
417 if (err)
418 break;
419 *(dest + i) = byte;
420 }
421
422 return (err ? 1 : 0);
423}
424
425/*
426 * NIC memory access function. Can be used to either clear a section
427 * of NIC local memory or (if buf is non-NULL) copy data into it.
428 */
429static void
430ti_mem(sc, addr, len, buf)
431 struct ti_softc *sc;
432 u_int32_t addr, len;
433 caddr_t buf;
434{
435 int segptr, segsize, cnt;
436 caddr_t ti_winbase, ptr;
437
438 segptr = addr;
439 cnt = len;
440 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
441 ptr = buf;
442
443 while (cnt) {
444 if (cnt < TI_WINLEN)
445 segsize = cnt;
446 else
447 segsize = TI_WINLEN - (segptr % TI_WINLEN);
448 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
449 if (buf == NULL)
450 bzero((char *)ti_winbase + (segptr &
451 (TI_WINLEN - 1)), segsize);
452 else {
453 bcopy((char *)ptr, (char *)ti_winbase +
454 (segptr & (TI_WINLEN - 1)), segsize);
455 ptr += segsize;
456 }
457 segptr += segsize;
458 cnt -= segsize;
459 }
460}
461
462static int
463ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
464 struct ti_softc *sc;
465 u_int32_t tigon_addr, len;
466 caddr_t buf;
467 int useraddr, readdata;
468{
469 int segptr, segsize, cnt;
470 caddr_t ptr;
471 u_int32_t origwin;
472 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
473 int resid, segresid;
474 int first_pass;
475
476 /*
477 * At the moment, we don't handle non-aligned cases, we just bail.
478 * If this proves to be a problem, it will be fixed.
479 */
480 if ((readdata == 0)
481 && (tigon_addr & 0x3)) {
482 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
483 "word-aligned\n", sc->ti_unit, tigon_addr);
484 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
485 "supported\n", sc->ti_unit);
486 return (EINVAL);
487 }
488
489 segptr = tigon_addr & ~0x3;
490 segresid = tigon_addr - segptr;
491
492 /*
493 * This is the non-aligned amount left over that we'll need to
494 * copy.
495 */
496 resid = len & 0x3;
497
498 /* Add in the left over amount at the front of the buffer */
499 resid += segresid;
500
501 cnt = len & ~0x3;
502 /*
503 * If resid + segresid is >= 4, add multiples of 4 to the count and
504 * decrease the residual by that much.
505 */
506 cnt += resid & ~0x3;
507 resid -= resid & ~0x3;
508
509 ptr = buf;
510
511 first_pass = 1;
512
513 /*
514 * Make sure we aren't interrupted while we're changing the window
515 * pointer.
516 */
517 TI_LOCK(sc);
518
519 /*
520 * Save the old window base value.
521 */
522 origwin = CSR_READ_4(sc, TI_WINBASE);
523
524 while (cnt) {
525 bus_size_t ti_offset;
526
527 if (cnt < TI_WINLEN)
528 segsize = cnt;
529 else
530 segsize = TI_WINLEN - (segptr % TI_WINLEN);
531 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
532
533 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
534
535 if (readdata) {
536
537 bus_space_read_region_4(sc->ti_btag,
538 sc->ti_bhandle, ti_offset,
539 (u_int32_t *)tmparray,
540 segsize >> 2);
541 if (useraddr) {
542 /*
543 * Yeah, this is a little on the kludgy
544 * side, but at least this code is only
545 * used for debugging.
546 */
547 ti_bcopy_swap(tmparray, tmparray2, segsize,
548 TI_SWAP_NTOH);
549
550 if (first_pass) {
551 copyout(&tmparray2[segresid], ptr,
552 segsize - segresid);
553 first_pass = 0;
554 } else
555 copyout(tmparray2, ptr, segsize);
556 } else {
557 if (first_pass) {
558
559 ti_bcopy_swap(tmparray, tmparray2,
560 segsize, TI_SWAP_NTOH);
561 bcopy(&tmparray2[segresid], ptr,
562 segsize - segresid);
563 first_pass = 0;
564 } else
565 ti_bcopy_swap(tmparray, ptr, segsize,
566 TI_SWAP_NTOH);
567 }
568
569 } else {
570 if (useraddr) {
571 copyin(ptr, tmparray2, segsize);
572 ti_bcopy_swap(tmparray2, tmparray, segsize,
573 TI_SWAP_HTON);
574 } else
575 ti_bcopy_swap(ptr, tmparray, segsize,
576 TI_SWAP_HTON);
577
578 bus_space_write_region_4(sc->ti_btag,
579 sc->ti_bhandle, ti_offset,
580 (u_int32_t *)tmparray,
581 segsize >> 2);
582 }
583 segptr += segsize;
584 ptr += segsize;
585 cnt -= segsize;
586 }
587
588 /*
589 * Handle leftover, non-word-aligned bytes.
590 */
591 if (resid != 0) {
592 u_int32_t tmpval, tmpval2;
593 bus_size_t ti_offset;
594
595 /*
596 * Set the segment pointer.
597 */
598 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
599
600 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
601
602 /*
603 * First, grab whatever is in our source/destination.
604 * We'll obviously need this for reads, but also for
605 * writes, since we'll be doing read/modify/write.
606 */
607 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
608 ti_offset, &tmpval, 1);
609
610 /*
611 * Next, translate this from little-endian to big-endian
612 * (at least on i386 boxes).
613 */
614 tmpval2 = ntohl(tmpval);
615
616 if (readdata) {
617 /*
618 * If we're reading, just copy the leftover number
619 * of bytes from the host byte order buffer to
620 * the user's buffer.
621 */
622 if (useraddr)
623 copyout(&tmpval2, ptr, resid);
624 else
625 bcopy(&tmpval2, ptr, resid);
626 } else {
627 /*
628 * If we're writing, first copy the bytes to be
629 * written into the network byte order buffer,
630 * leaving the rest of the buffer with whatever was
631 * originally in there. Then, swap the bytes
632 * around into host order and write them out.
633 *
634 * XXX KDM the read side of this has been verified
635 * to work, but the write side of it has not been
636 * verified. So user beware.
637 */
638 if (useraddr)
639 copyin(ptr, &tmpval2, resid);
640 else
641 bcopy(ptr, &tmpval2, resid);
642
643 tmpval = htonl(tmpval2);
644
645 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
646 ti_offset, &tmpval, 1);
647 }
648 }
649
650 CSR_WRITE_4(sc, TI_WINBASE, origwin);
651
652 TI_UNLOCK(sc);
653
654 return (0);
655}
656
657static int
658ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
659 struct ti_softc *sc;
660 u_int32_t tigon_addr, len;
661 caddr_t buf;
662 int useraddr, readdata;
663 int cpu;
664{
665 u_int32_t segptr;
666 int cnt;
667 u_int32_t tmpval, tmpval2;
668 caddr_t ptr;
669
670 /*
671 * At the moment, we don't handle non-aligned cases, we just bail.
672 * If this proves to be a problem, it will be fixed.
673 */
674 if (tigon_addr & 0x3) {
675 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
676 "word-aligned\n", sc->ti_unit, tigon_addr);
677 return (EINVAL);
678 }
679
680 if (len & 0x3) {
681 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
682 "word-aligned\n", sc->ti_unit, len);
683 return (EINVAL);
684 }
685
686 segptr = tigon_addr;
687 cnt = len;
688 ptr = buf;
689
690 TI_LOCK(sc);
691
692 while (cnt) {
693 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
694
695 if (readdata) {
696 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
697
698 tmpval = ntohl(tmpval2);
699
700 /*
701 * Note: I've used this debugging interface
702 * extensively with Alteon's 12.3.15 firmware,
703 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
704 *
705 * When you compile the firmware without
706 * optimization, which is necessary sometimes in
707 * order to properly step through it, you sometimes
708 * read out a bogus value of 0xc0017c instead of
709 * whatever was supposed to be in that scratchpad
710 * location. That value is on the stack somewhere,
711 * but I've never been able to figure out what was
712 * causing the problem.
713 *
714 * The address seems to pop up in random places,
715 * often not in the same place on two subsequent
716 * reads.
717 *
718 * In any case, the underlying data doesn't seem
719 * to be affected, just the value read out.
720 *
721 * KDM, 3/7/2000
722 */
723
724 if (tmpval2 == 0xc0017c)
725 printf("ti%d: found 0xc0017c at %#x "
726 "(tmpval2)\n", sc->ti_unit, segptr);
727
728 if (tmpval == 0xc0017c)
729 printf("ti%d: found 0xc0017c at %#x "
730 "(tmpval)\n", sc->ti_unit, segptr);
731
732 if (useraddr)
733 copyout(&tmpval, ptr, 4);
734 else
735 bcopy(&tmpval, ptr, 4);
736 } else {
737 if (useraddr)
738 copyin(ptr, &tmpval2, 4);
739 else
740 bcopy(ptr, &tmpval2, 4);
741
742 tmpval = htonl(tmpval2);
743
744 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
745 }
746
747 cnt -= 4;
748 segptr += 4;
749 ptr += 4;
750 }
751
752 TI_UNLOCK(sc);
753
754 return (0);
755}
756
757static int
758ti_bcopy_swap(src, dst, len, swap_type)
759 const void *src;
760 void *dst;
761 size_t len;
762 ti_swap_type swap_type;
763{
764 const u_int8_t *tmpsrc;
765 u_int8_t *tmpdst;
766 size_t tmplen;
767
768 if (len & 0x3) {
769 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
770 len);
771 return (-1);
772 }
773
774 tmpsrc = src;
775 tmpdst = dst;
776 tmplen = len;
777
778 while (tmplen) {
779 if (swap_type == TI_SWAP_NTOH)
780 *(u_int32_t *)tmpdst =
781 ntohl(*(const u_int32_t *)tmpsrc);
782 else
783 *(u_int32_t *)tmpdst =
784 htonl(*(const u_int32_t *)tmpsrc);
785
786 tmpsrc += 4;
787 tmpdst += 4;
788 tmplen -= 4;
789 }
790
791 return (0);
792}
793
794/*
795 * Load firmware image into the NIC. Check that the firmware revision
796 * is acceptable and see if we want the firmware for the Tigon 1 or
797 * Tigon 2.
798 */
799static void
800ti_loadfw(sc)
801 struct ti_softc *sc;
802{
803 switch (sc->ti_hwrev) {
804 case TI_HWREV_TIGON:
805 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
806 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
807 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
808 printf("ti%d: firmware revision mismatch; want "
809 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
810 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
811 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
812 tigonFwReleaseMinor, tigonFwReleaseFix);
813 return;
814 }
815 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
816 (caddr_t)tigonFwText);
817 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
818 (caddr_t)tigonFwData);
819 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
820 (caddr_t)tigonFwRodata);
821 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
822 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
823 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
824 break;
825 case TI_HWREV_TIGON_II:
826 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
827 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
828 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
829 printf("ti%d: firmware revision mismatch; want "
830 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
831 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
832 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
833 tigon2FwReleaseMinor, tigon2FwReleaseFix);
834 return;
835 }
836 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
837 (caddr_t)tigon2FwText);
838 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
839 (caddr_t)tigon2FwData);
840 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
841 (caddr_t)tigon2FwRodata);
842 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
843 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
845 break;
846 default:
847 printf("ti%d: can't load firmware: unknown hardware rev\n",
848 sc->ti_unit);
849 break;
850 }
851}
852
853/*
854 * Send the NIC a command via the command ring.
855 */
856static void
857ti_cmd(sc, cmd)
858 struct ti_softc *sc;
859 struct ti_cmd_desc *cmd;
860{
861 u_int32_t index;
862
863 if (sc->ti_rdata->ti_cmd_ring == NULL)
864 return;
865
866 index = sc->ti_cmd_saved_prodidx;
867 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
868 TI_INC(index, TI_CMD_RING_CNT);
869 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
870 sc->ti_cmd_saved_prodidx = index;
871}
872
873/*
874 * Send the NIC an extended command. The 'len' parameter specifies the
875 * number of command slots to include after the initial command.
876 */
877static void
878ti_cmd_ext(sc, cmd, arg, len)
879 struct ti_softc *sc;
880 struct ti_cmd_desc *cmd;
881 caddr_t arg;
882 int len;
883{
884 u_int32_t index;
885 register int i;
886
887 if (sc->ti_rdata->ti_cmd_ring == NULL)
888 return;
889
890 index = sc->ti_cmd_saved_prodidx;
891 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
892 TI_INC(index, TI_CMD_RING_CNT);
893 for (i = 0; i < len; i++) {
894 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
895 *(u_int32_t *)(&arg[i * 4]));
896 TI_INC(index, TI_CMD_RING_CNT);
897 }
898 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
899 sc->ti_cmd_saved_prodidx = index;
900}
901
902/*
903 * Handle events that have triggered interrupts.
904 */
905static void
906ti_handle_events(sc)
907 struct ti_softc *sc;
908{
909 struct ti_event_desc *e;
910
911 if (sc->ti_rdata->ti_event_ring == NULL)
912 return;
913
914 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
915 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
916 switch (e->ti_event) {
917 case TI_EV_LINKSTAT_CHANGED:
918 sc->ti_linkstat = e->ti_code;
919 if (e->ti_code == TI_EV_CODE_LINK_UP)
920 printf("ti%d: 10/100 link up\n", sc->ti_unit);
921 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
922 printf("ti%d: gigabit link up\n", sc->ti_unit);
923 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
924 printf("ti%d: link down\n", sc->ti_unit);
925 break;
926 case TI_EV_ERROR:
927 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
928 printf("ti%d: invalid command\n", sc->ti_unit);
929 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
930 printf("ti%d: unknown command\n", sc->ti_unit);
931 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
932 printf("ti%d: bad config data\n", sc->ti_unit);
933 break;
934 case TI_EV_FIRMWARE_UP:
935 ti_init2(sc);
936 break;
937 case TI_EV_STATS_UPDATED:
938 ti_stats_update(sc);
939 break;
940 case TI_EV_RESET_JUMBO_RING:
941 case TI_EV_MCAST_UPDATED:
942 /* Who cares. */
943 break;
944 default:
945 printf("ti%d: unknown event: %d\n",
946 sc->ti_unit, e->ti_event);
947 break;
948 }
949 /* Advance the consumer index. */
950 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
951 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
952 }
953}
954
955#ifdef TI_PRIVATE_JUMBOS
956
957/*
958 * Memory management for the jumbo receive ring is a pain in the
959 * butt. We need to allocate at least 9018 bytes of space per frame,
960 * _and_ it has to be contiguous (unless you use the extended
961 * jumbo descriptor format). Using malloc() all the time won't
962 * work: malloc() allocates memory in powers of two, which means we
963 * would end up wasting a considerable amount of space by allocating
964 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
965 * to do our own memory management.
966 *
967 * The driver needs to allocate a contiguous chunk of memory at boot
968 * time. We then chop this up ourselves into 9K pieces and use them
969 * as external mbuf storage.
970 *
971 * One issue here is how much memory to allocate. The jumbo ring has
972 * 256 slots in it, but at 9K per slot than can consume over 2MB of
973 * RAM. This is a bit much, especially considering we also need
974 * RAM for the standard ring and mini ring (on the Tigon 2). To
975 * save space, we only actually allocate enough memory for 64 slots
976 * by default, which works out to between 500 and 600K. This can
977 * be tuned by changing a #define in if_tireg.h.
978 */
979
980static int
981ti_alloc_jumbo_mem(sc)
982 struct ti_softc *sc;
983{
984 caddr_t ptr;
985 register int i;
986 struct ti_jpool_entry *entry;
987
988 /* Grab a big chunk o' storage. */
989 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
990 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
991
992 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
993 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
994 return (ENOBUFS);
995 }
996
997 SLIST_INIT(&sc->ti_jfree_listhead);
998 SLIST_INIT(&sc->ti_jinuse_listhead);
999
1000 /*
1001 * Now divide it up into 9K pieces and save the addresses
1002 * in an array.
1003 */
1004 ptr = sc->ti_cdata.ti_jumbo_buf;
1005 for (i = 0; i < TI_JSLOTS; i++) {
1006 sc->ti_cdata.ti_jslots[i] = ptr;
1007 ptr += TI_JLEN;
1008 entry = malloc(sizeof(struct ti_jpool_entry),
1009 M_DEVBUF, M_NOWAIT);
1010 if (entry == NULL) {
1011 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
1012 M_DEVBUF);
1013 sc->ti_cdata.ti_jumbo_buf = NULL;
1014 printf("ti%d: no memory for jumbo "
1015 "buffer queue!\n", sc->ti_unit);
1016 return (ENOBUFS);
1017 }
1018 entry->slot = i;
1019 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1020 }
1021
1022 return (0);
1023}
1024
1025/*
1026 * Allocate a jumbo buffer.
1027 */
1028static void *ti_jalloc(sc)
1029 struct ti_softc *sc;
1030{
1031 struct ti_jpool_entry *entry;
1032
1033 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1034
1035 if (entry == NULL) {
1036 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
1037 return (NULL);
1038 }
1039
1040 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1041 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1042 return (sc->ti_cdata.ti_jslots[entry->slot]);
1043}
1044
1045/*
1046 * Release a jumbo buffer.
1047 */
1048static void
1049ti_jfree(buf, args)
1050 void *buf;
1051 void *args;
1052{
1053 struct ti_softc *sc;
1054 int i;
1055 struct ti_jpool_entry *entry;
1056
1057 /* Extract the softc struct pointer. */
1058 sc = (struct ti_softc *)args;
1059
1060 if (sc == NULL)
1061 panic("ti_jfree: didn't get softc pointer!");
1062
1063 /* calculate the slot this buffer belongs to */
1064 i = ((vm_offset_t)buf
1065 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1066
1067 if ((i < 0) || (i >= TI_JSLOTS))
1068 panic("ti_jfree: asked to free buffer that we don't manage!");
1069
1070 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1071 if (entry == NULL)
1072 panic("ti_jfree: buffer not in use!");
1073 entry->slot = i;
1074 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1075 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1076}
1077
1078#endif /* TI_PRIVATE_JUMBOS */
1079
1080/*
1081 * Intialize a standard receive ring descriptor.
1082 */
1083static int
1084ti_newbuf_std(sc, i, m)
1085 struct ti_softc *sc;
1086 int i;
1087 struct mbuf *m;
1088{
1089 struct mbuf *m_new = NULL;
1090 struct ti_rx_desc *r;
1091
1092 if (m == NULL) {
1093 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1094 if (m_new == NULL)
1095 return (ENOBUFS);
1096
1097 MCLGET(m_new, M_DONTWAIT);
1098 if (!(m_new->m_flags & M_EXT)) {
1099 m_freem(m_new);
1100 return (ENOBUFS);
1101 }
1102 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1103 } else {
1104 m_new = m;
1105 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1106 m_new->m_data = m_new->m_ext.ext_buf;
1107 }
1108
1109 m_adj(m_new, ETHER_ALIGN);
1110 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1111 r = &sc->ti_rdata->ti_rx_std_ring[i];
1112 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1113 r->ti_type = TI_BDTYPE_RECV_BD;
1114 r->ti_flags = 0;
1115 if (sc->arpcom.ac_if.if_hwassist)
1116 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1117 r->ti_len = m_new->m_len;
1118 r->ti_idx = i;
1119
1120 return (0);
1121}
1122
1123/*
1124 * Intialize a mini receive ring descriptor. This only applies to
1125 * the Tigon 2.
1126 */
1127static int
1128ti_newbuf_mini(sc, i, m)
1129 struct ti_softc *sc;
1130 int i;
1131 struct mbuf *m;
1132{
1133 struct mbuf *m_new = NULL;
1134 struct ti_rx_desc *r;
1135
1136 if (m == NULL) {
1137 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1138 if (m_new == NULL) {
1139 return (ENOBUFS);
1140 }
1141 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1142 } else {
1143 m_new = m;
1144 m_new->m_data = m_new->m_pktdat;
1145 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1146 }
1147
1148 m_adj(m_new, ETHER_ALIGN);
1149 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1150 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1151 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1152 r->ti_type = TI_BDTYPE_RECV_BD;
1153 r->ti_flags = TI_BDFLAG_MINI_RING;
1154 if (sc->arpcom.ac_if.if_hwassist)
1155 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1156 r->ti_len = m_new->m_len;
1157 r->ti_idx = i;
1158
1159 return (0);
1160}
1161
1162#ifdef TI_PRIVATE_JUMBOS
1163
1164/*
1165 * Initialize a jumbo receive ring descriptor. This allocates
1166 * a jumbo buffer from the pool managed internally by the driver.
1167 */
1168static int
1169ti_newbuf_jumbo(sc, i, m)
1170 struct ti_softc *sc;
1171 int i;
1172 struct mbuf *m;
1173{
1174 struct mbuf *m_new = NULL;
1175 struct ti_rx_desc *r;
1176
1177 if (m == NULL) {
1178 caddr_t *buf = NULL;
1179
1180 /* Allocate the mbuf. */
1181 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1182 if (m_new == NULL) {
1183 return (ENOBUFS);
1184 }
1185
1186 /* Allocate the jumbo buffer */
1187 buf = ti_jalloc(sc);
1188 if (buf == NULL) {
1189 m_freem(m_new);
1190 printf("ti%d: jumbo allocation failed "
1191 "-- packet dropped!\n", sc->ti_unit);
1192 return (ENOBUFS);
1193 }
1194
1195 /* Attach the buffer to the mbuf. */
1196 m_new->m_data = (void *) buf;
1197 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1198 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1199 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1200 } else {
1201 m_new = m;
1202 m_new->m_data = m_new->m_ext.ext_buf;
1203 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1204 }
1205
1206 m_adj(m_new, ETHER_ALIGN);
1207 /* Set up the descriptor. */
1208 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1209 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1210 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1211 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1212 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1213 if (sc->arpcom.ac_if.if_hwassist)
1214 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1215 r->ti_len = m_new->m_len;
1216 r->ti_idx = i;
1217
1218 return (0);
1219}
1220
1221#else
1222#include <vm/vm_page.h>
1223
1224#if (PAGE_SIZE == 4096)
1225#define NPAYLOAD 2
1226#else
1227#define NPAYLOAD 1
1228#endif
1229
1230#define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1231#define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1232#define NFS_HDR_LEN (UDP_HDR_LEN)
1233static int HDR_LEN = TCP_HDR_LEN;
1234
1235
1236/*
1237 * Initialize a jumbo receive ring descriptor. This allocates
1238 * a jumbo buffer from the pool managed internally by the driver.
1239 */
1240static int
1241ti_newbuf_jumbo(sc, idx, m_old)
1242 struct ti_softc *sc;
1243 int idx;
1244 struct mbuf *m_old;
1245{
1246 struct mbuf *cur, *m_new = NULL;
1247 struct mbuf *m[3] = {NULL, NULL, NULL};
1248 struct ti_rx_desc_ext *r;
1249 vm_page_t frame;
1250 static int color;
1251 /* 1 extra buf to make nobufs easy*/
1252 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1253 int i;
1254
1255 if (m_old != NULL) {
1256 m_new = m_old;
1257 cur = m_old->m_next;
1258 for (i = 0; i <= NPAYLOAD; i++){
1259 m[i] = cur;
1260 cur = cur->m_next;
1261 }
1262 } else {
1263 /* Allocate the mbufs. */
1264 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1265 if (m_new == NULL) {
1266 printf("ti%d: mbuf allocation failed "
1267 "-- packet dropped!\n", sc->ti_unit);
1268 goto nobufs;
1269 }
1270 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1271 if (m[NPAYLOAD] == NULL) {
1272 printf("ti%d: cluster mbuf allocation failed "
1273 "-- packet dropped!\n", sc->ti_unit);
1274 goto nobufs;
1275 }
1276 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1277 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1278 printf("ti%d: mbuf allocation failed "
1279 "-- packet dropped!\n", sc->ti_unit);
1280 goto nobufs;
1281 }
1282 m[NPAYLOAD]->m_len = MCLBYTES;
1283
1284 for (i = 0; i < NPAYLOAD; i++){
1285 MGET(m[i], M_DONTWAIT, MT_DATA);
1286 if (m[i] == NULL) {
1287 printf("ti%d: mbuf allocation failed "
1288 "-- packet dropped!\n", sc->ti_unit);
1289 goto nobufs;
1290 }
1291 frame = vm_page_alloc(NULL, color++,
1292 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1293 VM_ALLOC_WIRED);
1294 if (frame == NULL) {
1295 printf("ti%d: buffer allocation failed "
1296 "-- packet dropped!\n", sc->ti_unit);
1297 printf(" index %d page %d\n", idx, i);
1298 goto nobufs;
1299 }
1300 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1301 if (sf[i] == NULL) {
1302 vm_page_lock_queues();
1303 vm_page_unwire(frame, 0);
1304 vm_page_free(frame);
1305 vm_page_unlock_queues();
1306 printf("ti%d: buffer allocation failed "
1307 "-- packet dropped!\n", sc->ti_unit);
1308 printf(" index %d page %d\n", idx, i);
1309 goto nobufs;
1310 }
1311 }
1312 for (i = 0; i < NPAYLOAD; i++){
1313 /* Attach the buffer to the mbuf. */
1314 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1315 m[i]->m_len = PAGE_SIZE;
1316 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1317 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE);
1318 m[i]->m_next = m[i+1];
1319 }
1320 /* link the buffers to the header */
1321 m_new->m_next = m[0];
1322 m_new->m_data += ETHER_ALIGN;
1323 if (sc->ti_hdrsplit)
1324 m_new->m_len = MHLEN - ETHER_ALIGN;
1325 else
1326 m_new->m_len = HDR_LEN;
1327 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1328 }
1329
1330 /* Set up the descriptor. */
1331 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1332 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1333 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
1334 r->ti_len0 = m_new->m_len;
1335
1336 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
1337 r->ti_len1 = PAGE_SIZE;
1338
1339 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
1340 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1341
1342 if (PAGE_SIZE == 4096) {
1343 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
1344 r->ti_len3 = MCLBYTES;
1345 } else {
1346 r->ti_len3 = 0;
1347 }
1348 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1349
1350 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1351
1352 if (sc->arpcom.ac_if.if_hwassist)
1353 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1354
1355 r->ti_idx = idx;
1356
1357 return (0);
1358
1359nobufs:
1360
1361 /*
1362 * Warning! :
1363 * This can only be called before the mbufs are strung together.
1364 * If the mbufs are strung together, m_freem() will free the chain,
1365 * so that the later mbufs will be freed multiple times.
1366 */
1367 if (m_new)
1368 m_freem(m_new);
1369
1370 for (i = 0; i < 3; i++) {
1371 if (m[i])
1372 m_freem(m[i]);
1373 if (sf[i])
1374 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1375 }
1376 return (ENOBUFS);
1377}
1378#endif
1379
1380
1381
1382/*
1383 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1384 * that's 1MB or memory, which is a lot. For now, we fill only the first
1385 * 256 ring entries and hope that our CPU is fast enough to keep up with
1386 * the NIC.
1387 */
1388static int
1389ti_init_rx_ring_std(sc)
1390 struct ti_softc *sc;
1391{
1392 register int i;
1393 struct ti_cmd_desc cmd;
1394
1395 for (i = 0; i < TI_SSLOTS; i++) {
1396 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1397 return (ENOBUFS);
1398 };
1399
1400 TI_UPDATE_STDPROD(sc, i - 1);
1401 sc->ti_std = i - 1;
1402
1403 return (0);
1404}
1405
1406static void
1407ti_free_rx_ring_std(sc)
1408 struct ti_softc *sc;
1409{
1410 register int i;
1411
1412 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1413 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1414 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1415 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1416 }
1417 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1418 sizeof(struct ti_rx_desc));
1419 }
1420}
1421
1422static int
1423ti_init_rx_ring_jumbo(sc)
1424 struct ti_softc *sc;
1425{
1426 register int i;
1427 struct ti_cmd_desc cmd;
1428
1429 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1430 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1431 return (ENOBUFS);
1432 };
1433
1434 TI_UPDATE_JUMBOPROD(sc, i - 1);
1435 sc->ti_jumbo = i - 1;
1436
1437 return (0);
1438}
1439
1440static void
1441ti_free_rx_ring_jumbo(sc)
1442 struct ti_softc *sc;
1443{
1444 register int i;
1445
1446 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1447 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1448 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1449 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1450 }
1451 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1452 sizeof(struct ti_rx_desc));
1453 }
1454}
1455
1456static int
1457ti_init_rx_ring_mini(sc)
1458 struct ti_softc *sc;
1459{
1460 register int i;
1461
1462 for (i = 0; i < TI_MSLOTS; i++) {
1463 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1464 return (ENOBUFS);
1465 };
1466
1467 TI_UPDATE_MINIPROD(sc, i - 1);
1468 sc->ti_mini = i - 1;
1469
1470 return (0);
1471}
1472
1473static void
1474ti_free_rx_ring_mini(sc)
1475 struct ti_softc *sc;
1476{
1477 register int i;
1478
1479 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1480 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1481 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1482 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1483 }
1484 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1485 sizeof(struct ti_rx_desc));
1486 }
1487}
1488
1489static void
1490ti_free_tx_ring(sc)
1491 struct ti_softc *sc;
1492{
1493 register int i;
1494
1495 if (sc->ti_rdata->ti_tx_ring == NULL)
1496 return;
1497
1498 for (i = 0; i < TI_TX_RING_CNT; i++) {
1499 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1500 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1501 sc->ti_cdata.ti_tx_chain[i] = NULL;
1502 }
1503 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1504 sizeof(struct ti_tx_desc));
1505 }
1506}
1507
1508static int
1509ti_init_tx_ring(sc)
1510 struct ti_softc *sc;
1511{
1512 sc->ti_txcnt = 0;
1513 sc->ti_tx_saved_considx = 0;
1514 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1515 return (0);
1516}
1517
1518/*
1519 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1520 * but we have to support the old way too so that Tigon 1 cards will
1521 * work.
1522 */
1523static void
1524ti_add_mcast(sc, addr)
1525 struct ti_softc *sc;
1526 struct ether_addr *addr;
1527{
1528 struct ti_cmd_desc cmd;
1529 u_int16_t *m;
1530 u_int32_t ext[2] = {0, 0};
1531
1532 m = (u_int16_t *)&addr->octet[0];
1533
1534 switch (sc->ti_hwrev) {
1535 case TI_HWREV_TIGON:
1536 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1537 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1538 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1539 break;
1540 case TI_HWREV_TIGON_II:
1541 ext[0] = htons(m[0]);
1542 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1543 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1544 break;
1545 default:
1546 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1547 break;
1548 }
1549}
1550
1551static void
1552ti_del_mcast(sc, addr)
1553 struct ti_softc *sc;
1554 struct ether_addr *addr;
1555{
1556 struct ti_cmd_desc cmd;
1557 u_int16_t *m;
1558 u_int32_t ext[2] = {0, 0};
1559
1560 m = (u_int16_t *)&addr->octet[0];
1561
1562 switch (sc->ti_hwrev) {
1563 case TI_HWREV_TIGON:
1564 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1565 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1566 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1567 break;
1568 case TI_HWREV_TIGON_II:
1569 ext[0] = htons(m[0]);
1570 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1571 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1572 break;
1573 default:
1574 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1575 break;
1576 }
1577}
1578
1579/*
1580 * Configure the Tigon's multicast address filter.
1581 *
1582 * The actual multicast table management is a bit of a pain, thanks to
1583 * slight brain damage on the part of both Alteon and us. With our
1584 * multicast code, we are only alerted when the multicast address table
1585 * changes and at that point we only have the current list of addresses:
1586 * we only know the current state, not the previous state, so we don't
1587 * actually know what addresses were removed or added. The firmware has
1588 * state, but we can't get our grubby mits on it, and there is no 'delete
1589 * all multicast addresses' command. Hence, we have to maintain our own
1590 * state so we know what addresses have been programmed into the NIC at
1591 * any given time.
1592 */
1593static void
1594ti_setmulti(sc)
1595 struct ti_softc *sc;
1596{
1597 struct ifnet *ifp;
1598 struct ifmultiaddr *ifma;
1599 struct ti_cmd_desc cmd;
1600 struct ti_mc_entry *mc;
1601 u_int32_t intrs;
1602
1603 ifp = &sc->arpcom.ac_if;
1604
1605 if (ifp->if_flags & IFF_ALLMULTI) {
1606 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1607 return;
1608 } else {
1609 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1610 }
1611
1612 /* Disable interrupts. */
1613 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1614 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1615
1616 /* First, zot all the existing filters. */
1617 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1618 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1619 ti_del_mcast(sc, &mc->mc_addr);
1620 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1621 free(mc, M_DEVBUF);
1622 }
1623
1624 /* Now program new ones. */
1625 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1626 if (ifma->ifma_addr->sa_family != AF_LINK)
1627 continue;
1628 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1629 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1630 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1631 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1632 ti_add_mcast(sc, &mc->mc_addr);
1633 }
1634
1635 /* Re-enable interrupts. */
1636 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1637}
1638
1639/*
1640 * Check to see if the BIOS has configured us for a 64 bit slot when
1641 * we aren't actually in one. If we detect this condition, we can work
1642 * around it on the Tigon 2 by setting a bit in the PCI state register,
1643 * but for the Tigon 1 we must give up and abort the interface attach.
1644 */
1645static int ti_64bitslot_war(sc)
1646 struct ti_softc *sc;
1647{
1648 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1649 CSR_WRITE_4(sc, 0x600, 0);
1650 CSR_WRITE_4(sc, 0x604, 0);
1651 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1652 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1653 if (sc->ti_hwrev == TI_HWREV_TIGON)
1654 return (EINVAL);
1655 else {
1656 TI_SETBIT(sc, TI_PCI_STATE,
1657 TI_PCISTATE_32BIT_BUS);
1658 return (0);
1659 }
1660 }
1661 }
1662
1663 return (0);
1664}
1665
1666/*
1667 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1668 * self-test results.
1669 */
1670static int
1671ti_chipinit(sc)
1672 struct ti_softc *sc;
1673{
1674 u_int32_t cacheline;
1675 u_int32_t pci_writemax = 0;
1676 u_int32_t hdrsplit;
1677
1678 /* Initialize link to down state. */
1679 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1680
1681 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1682 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1683 else
1684 sc->arpcom.ac_if.if_hwassist = 0;
1685
1686 /* Set endianness before we access any non-PCI registers. */
1687#if BYTE_ORDER == BIG_ENDIAN
1688 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1689 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1690#else
1691 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1692 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1693#endif
1694
1695 /* Check the ROM failed bit to see if self-tests passed. */
1696 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1697 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1698 return (ENODEV);
1699 }
1700
1701 /* Halt the CPU. */
1702 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1703
1704 /* Figure out the hardware revision. */
1705 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1706 case TI_REV_TIGON_I:
1707 sc->ti_hwrev = TI_HWREV_TIGON;
1708 break;
1709 case TI_REV_TIGON_II:
1710 sc->ti_hwrev = TI_HWREV_TIGON_II;
1711 break;
1712 default:
1713 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1714 return (ENODEV);
1715 }
1716
1717 /* Do special setup for Tigon 2. */
1718 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1719 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1720 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1721 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1722 }
1723
1724 /*
1725 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1726 * can't do header splitting.
1727 */
1728#ifdef TI_JUMBO_HDRSPLIT
1729 if (sc->ti_hwrev != TI_HWREV_TIGON)
1730 sc->ti_hdrsplit = 1;
1731 else
1732 printf("ti%d: can't do header splitting on a Tigon I board\n",
1733 sc->ti_unit);
1734#endif /* TI_JUMBO_HDRSPLIT */
1735
1736 /* Set up the PCI state register. */
1737 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1738 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1739 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1740 }
1741
1742 /* Clear the read/write max DMA parameters. */
1743 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1744 TI_PCISTATE_READ_MAXDMA));
1745
1746 /* Get cache line size. */
1747 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1748
1749 /*
1750 * If the system has set enabled the PCI memory write
1751 * and invalidate command in the command register, set
1752 * the write max parameter accordingly. This is necessary
1753 * to use MWI with the Tigon 2.
1754 */
1755 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1756 switch (cacheline) {
1757 case 1:
1758 case 4:
1759 case 8:
1760 case 16:
1761 case 32:
1762 case 64:
1763 break;
1764 default:
1765 /* Disable PCI memory write and invalidate. */
1766 if (bootverbose)
1767 printf("ti%d: cache line size %d not "
1768 "supported; disabling PCI MWI\n",
1769 sc->ti_unit, cacheline);
1770 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1771 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1772 break;
1773 }
1774 }
1775
1776#ifdef __brokenalpha__
1777 /*
1778 * From the Alteon sample driver:
1779 * Must insure that we do not cross an 8K (bytes) boundary
1780 * for DMA reads. Our highest limit is 1K bytes. This is a
1781 * restriction on some ALPHA platforms with early revision
1782 * 21174 PCI chipsets, such as the AlphaPC 164lx
1783 */
1784 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1785#else
1786 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1787#endif
1788
1789 /* This sets the min dma param all the way up (0xff). */
1790 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1791
1792 if (sc->ti_hdrsplit)
1793 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1794 else
1795 hdrsplit = 0;
1796
1797 /* Configure DMA variables. */
1798#if BYTE_ORDER == BIG_ENDIAN
1799 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1800 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1801 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1802 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1803#else /* BYTE_ORDER */
1804 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1805 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1806 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1807#endif /* BYTE_ORDER */
1808
1809 /*
1810 * Only allow 1 DMA channel to be active at a time.
1811 * I don't think this is a good idea, but without it
1812 * the firmware racks up lots of nicDmaReadRingFull
1813 * errors. This is not compatible with hardware checksums.
1814 */
1815 if (sc->arpcom.ac_if.if_hwassist == 0)
1816 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1817
1818 /* Recommended settings from Tigon manual. */
1819 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1820 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1821
1822 if (ti_64bitslot_war(sc)) {
1823 printf("ti%d: bios thinks we're in a 64 bit slot, "
1824 "but we aren't", sc->ti_unit);
1825 return (EINVAL);
1826 }
1827
1828 return (0);
1829}
1830
| 81
82#include "opt_ti.h"
83
84#include <sys/param.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/kernel.h>
90#include <sys/module.h>
91#include <sys/socket.h>
92#include <sys/queue.h>
93#include <sys/conf.h>
94
95#include <net/if.h>
96#include <net/if_arp.h>
97#include <net/ethernet.h>
98#include <net/if_dl.h>
99#include <net/if_media.h>
100#include <net/if_types.h>
101#include <net/if_vlan_var.h>
102
103#include <net/bpf.h>
104
105#include <netinet/in_systm.h>
106#include <netinet/in.h>
107#include <netinet/ip.h>
108
109#include <vm/vm.h> /* for vtophys */
110#include <vm/pmap.h> /* for vtophys */
111#include <machine/bus_memio.h>
112#include <machine/bus.h>
113#include <machine/resource.h>
114#include <sys/bus.h>
115#include <sys/rman.h>
116
117/* #define TI_PRIVATE_JUMBOS */
118
119#if !defined(TI_PRIVATE_JUMBOS)
120#include <sys/sockio.h>
121#include <sys/uio.h>
122#include <sys/lock.h>
123#include <sys/sf_buf.h>
124#include <vm/vm_extern.h>
125#include <vm/pmap.h>
126#include <vm/vm_map.h>
127#include <vm/vm_map.h>
128#include <vm/vm_param.h>
129#include <vm/vm_pageout.h>
130#include <sys/vmmeter.h>
131#include <vm/vm_page.h>
132#include <vm/vm_object.h>
133#include <vm/vm_kern.h>
134#include <sys/proc.h>
135#endif /* !TI_PRIVATE_JUMBOS */
136
137#include <dev/pci/pcireg.h>
138#include <dev/pci/pcivar.h>
139
140#include <sys/tiio.h>
141#include <pci/if_tireg.h>
142#include <pci/ti_fw.h>
143#include <pci/ti_fw2.h>
144
145#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
146/*
147 * We can only turn on header splitting if we're using extended receive
148 * BDs.
149 */
150#if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
151#error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
152#endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
153
154struct ti_softc *tis[8];
155
156typedef enum {
157 TI_SWAP_HTON,
158 TI_SWAP_NTOH
159} ti_swap_type;
160
161
162/*
163 * Various supported device vendors/types and their names.
164 */
165
166static struct ti_type ti_devs[] = {
167 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
170 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
171 { TC_VENDORID, TC_DEVICEID_3C985,
172 "3Com 3c985-SX Gigabit Ethernet" },
173 { NG_VENDORID, NG_DEVICEID_GA620,
174 "Netgear GA620 1000baseSX Gigabit Ethernet" },
175 { NG_VENDORID, NG_DEVICEID_GA620T,
176 "Netgear GA620 1000baseT Gigabit Ethernet" },
177 { SGI_VENDORID, SGI_DEVICEID_TIGON,
178 "Silicon Graphics Gigabit Ethernet" },
179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
180 "Farallon PN9000SX Gigabit Ethernet" },
181 { 0, 0, NULL }
182};
183
184
185static d_open_t ti_open;
186static d_close_t ti_close;
187static d_ioctl_t ti_ioctl2;
188
189static struct cdevsw ti_cdevsw = {
190 .d_version = D_VERSION,
191 .d_flags = D_NEEDGIANT,
192 .d_open = ti_open,
193 .d_close = ti_close,
194 .d_ioctl = ti_ioctl2,
195 .d_name = "ti",
196};
197
198static int ti_probe(device_t);
199static int ti_attach(device_t);
200static int ti_detach(device_t);
201static void ti_txeof(struct ti_softc *);
202static void ti_rxeof(struct ti_softc *);
203
204static void ti_stats_update(struct ti_softc *);
205static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
206
207static void ti_intr(void *);
208static void ti_start(struct ifnet *);
209static int ti_ioctl(struct ifnet *, u_long, caddr_t);
210static void ti_init(void *);
211static void ti_init2(struct ti_softc *);
212static void ti_stop(struct ti_softc *);
213static void ti_watchdog(struct ifnet *);
214static void ti_shutdown(device_t);
215static int ti_ifmedia_upd(struct ifnet *);
216static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
217
218static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
219static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
220static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
221
222static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
223static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
224static void ti_setmulti(struct ti_softc *);
225
226static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
227static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
228static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
229 int, int, int);
230static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
231static void ti_loadfw(struct ti_softc *);
232static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
233static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
234static void ti_handle_events(struct ti_softc *);
235#ifdef TI_PRIVATE_JUMBOS
236static int ti_alloc_jumbo_mem(struct ti_softc *);
237static void *ti_jalloc(struct ti_softc *);
238static void ti_jfree(void *, void *);
239#endif /* TI_PRIVATE_JUMBOS */
240static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
241static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
242static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
243static int ti_init_rx_ring_std(struct ti_softc *);
244static void ti_free_rx_ring_std(struct ti_softc *);
245static int ti_init_rx_ring_jumbo(struct ti_softc *);
246static void ti_free_rx_ring_jumbo(struct ti_softc *);
247static int ti_init_rx_ring_mini(struct ti_softc *);
248static void ti_free_rx_ring_mini(struct ti_softc *);
249static void ti_free_tx_ring(struct ti_softc *);
250static int ti_init_tx_ring(struct ti_softc *);
251
252static int ti_64bitslot_war(struct ti_softc *);
253static int ti_chipinit(struct ti_softc *);
254static int ti_gibinit(struct ti_softc *);
255
256#ifdef TI_JUMBO_HDRSPLIT
257static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
258 int pkt_len, int idx);
259#endif /* TI_JUMBO_HDRSPLIT */
260
261static device_method_t ti_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, ti_probe),
264 DEVMETHOD(device_attach, ti_attach),
265 DEVMETHOD(device_detach, ti_detach),
266 DEVMETHOD(device_shutdown, ti_shutdown),
267 { 0, 0 }
268};
269
270static driver_t ti_driver = {
271 "ti",
272 ti_methods,
273 sizeof(struct ti_softc)
274};
275
276static devclass_t ti_devclass;
277
278DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
279MODULE_DEPEND(ti, pci, 1, 1, 1);
280MODULE_DEPEND(ti, ether, 1, 1, 1);
281
282/*
283 * Send an instruction or address to the EEPROM, check for ACK.
284 */
285static u_int32_t ti_eeprom_putbyte(sc, byte)
286 struct ti_softc *sc;
287 int byte;
288{
289 register int i, ack = 0;
290
291 /*
292 * Make sure we're in TX mode.
293 */
294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
295
296 /*
297 * Feed in each bit and stobe the clock.
298 */
299 for (i = 0x80; i; i >>= 1) {
300 if (byte & i) {
301 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 } else {
303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
304 }
305 DELAY(1);
306 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 DELAY(1);
308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
309 }
310
311 /*
312 * Turn off TX mode.
313 */
314 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
315
316 /*
317 * Check for ack.
318 */
319 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
320 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
321 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
322
323 return (ack);
324}
325
326/*
327 * Read a byte of data stored in the EEPROM at address 'addr.'
328 * We have to send two address bytes since the EEPROM can hold
329 * more than 256 bytes of data.
330 */
331static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
332 struct ti_softc *sc;
333 int addr;
334 u_int8_t *dest;
335{
336 register int i;
337 u_int8_t byte = 0;
338
339 EEPROM_START;
340
341 /*
342 * Send write control code to EEPROM.
343 */
344 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
345 printf("ti%d: failed to send write command, status: %x\n",
346 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
347 return (1);
348 }
349
350 /*
351 * Send first byte of address of byte we want to read.
352 */
353 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
354 printf("ti%d: failed to send address, status: %x\n",
355 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
356 return (1);
357 }
358 /*
359 * Send second byte address of byte we want to read.
360 */
361 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
362 printf("ti%d: failed to send address, status: %x\n",
363 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
364 return (1);
365 }
366
367 EEPROM_STOP;
368 EEPROM_START;
369 /*
370 * Send read control code to EEPROM.
371 */
372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
373 printf("ti%d: failed to send read command, status: %x\n",
374 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
375 return (1);
376 }
377
378 /*
379 * Start reading bits from EEPROM.
380 */
381 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
382 for (i = 0x80; i; i >>= 1) {
383 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
384 DELAY(1);
385 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
386 byte |= i;
387 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
388 DELAY(1);
389 }
390
391 EEPROM_STOP;
392
393 /*
394 * No ACK generated for read, so just return byte.
395 */
396
397 *dest = byte;
398
399 return (0);
400}
401
402/*
403 * Read a sequence of bytes from the EEPROM.
404 */
405static int
406ti_read_eeprom(sc, dest, off, cnt)
407 struct ti_softc *sc;
408 caddr_t dest;
409 int off;
410 int cnt;
411{
412 int err = 0, i;
413 u_int8_t byte = 0;
414
415 for (i = 0; i < cnt; i++) {
416 err = ti_eeprom_getbyte(sc, off + i, &byte);
417 if (err)
418 break;
419 *(dest + i) = byte;
420 }
421
422 return (err ? 1 : 0);
423}
424
425/*
426 * NIC memory access function. Can be used to either clear a section
427 * of NIC local memory or (if buf is non-NULL) copy data into it.
428 */
429static void
430ti_mem(sc, addr, len, buf)
431 struct ti_softc *sc;
432 u_int32_t addr, len;
433 caddr_t buf;
434{
435 int segptr, segsize, cnt;
436 caddr_t ti_winbase, ptr;
437
438 segptr = addr;
439 cnt = len;
440 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
441 ptr = buf;
442
443 while (cnt) {
444 if (cnt < TI_WINLEN)
445 segsize = cnt;
446 else
447 segsize = TI_WINLEN - (segptr % TI_WINLEN);
448 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
449 if (buf == NULL)
450 bzero((char *)ti_winbase + (segptr &
451 (TI_WINLEN - 1)), segsize);
452 else {
453 bcopy((char *)ptr, (char *)ti_winbase +
454 (segptr & (TI_WINLEN - 1)), segsize);
455 ptr += segsize;
456 }
457 segptr += segsize;
458 cnt -= segsize;
459 }
460}
461
462static int
463ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
464 struct ti_softc *sc;
465 u_int32_t tigon_addr, len;
466 caddr_t buf;
467 int useraddr, readdata;
468{
469 int segptr, segsize, cnt;
470 caddr_t ptr;
471 u_int32_t origwin;
472 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
473 int resid, segresid;
474 int first_pass;
475
476 /*
477 * At the moment, we don't handle non-aligned cases, we just bail.
478 * If this proves to be a problem, it will be fixed.
479 */
480 if ((readdata == 0)
481 && (tigon_addr & 0x3)) {
482 printf("ti%d: ti_copy_mem: tigon address %#x isn't "
483 "word-aligned\n", sc->ti_unit, tigon_addr);
484 printf("ti%d: ti_copy_mem: unaligned writes aren't yet "
485 "supported\n", sc->ti_unit);
486 return (EINVAL);
487 }
488
489 segptr = tigon_addr & ~0x3;
490 segresid = tigon_addr - segptr;
491
492 /*
493 * This is the non-aligned amount left over that we'll need to
494 * copy.
495 */
496 resid = len & 0x3;
497
498 /* Add in the left over amount at the front of the buffer */
499 resid += segresid;
500
501 cnt = len & ~0x3;
502 /*
503 * If resid + segresid is >= 4, add multiples of 4 to the count and
504 * decrease the residual by that much.
505 */
506 cnt += resid & ~0x3;
507 resid -= resid & ~0x3;
508
509 ptr = buf;
510
511 first_pass = 1;
512
513 /*
514 * Make sure we aren't interrupted while we're changing the window
515 * pointer.
516 */
517 TI_LOCK(sc);
518
519 /*
520 * Save the old window base value.
521 */
522 origwin = CSR_READ_4(sc, TI_WINBASE);
523
524 while (cnt) {
525 bus_size_t ti_offset;
526
527 if (cnt < TI_WINLEN)
528 segsize = cnt;
529 else
530 segsize = TI_WINLEN - (segptr % TI_WINLEN);
531 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
532
533 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
534
535 if (readdata) {
536
537 bus_space_read_region_4(sc->ti_btag,
538 sc->ti_bhandle, ti_offset,
539 (u_int32_t *)tmparray,
540 segsize >> 2);
541 if (useraddr) {
542 /*
543 * Yeah, this is a little on the kludgy
544 * side, but at least this code is only
545 * used for debugging.
546 */
547 ti_bcopy_swap(tmparray, tmparray2, segsize,
548 TI_SWAP_NTOH);
549
550 if (first_pass) {
551 copyout(&tmparray2[segresid], ptr,
552 segsize - segresid);
553 first_pass = 0;
554 } else
555 copyout(tmparray2, ptr, segsize);
556 } else {
557 if (first_pass) {
558
559 ti_bcopy_swap(tmparray, tmparray2,
560 segsize, TI_SWAP_NTOH);
561 bcopy(&tmparray2[segresid], ptr,
562 segsize - segresid);
563 first_pass = 0;
564 } else
565 ti_bcopy_swap(tmparray, ptr, segsize,
566 TI_SWAP_NTOH);
567 }
568
569 } else {
570 if (useraddr) {
571 copyin(ptr, tmparray2, segsize);
572 ti_bcopy_swap(tmparray2, tmparray, segsize,
573 TI_SWAP_HTON);
574 } else
575 ti_bcopy_swap(ptr, tmparray, segsize,
576 TI_SWAP_HTON);
577
578 bus_space_write_region_4(sc->ti_btag,
579 sc->ti_bhandle, ti_offset,
580 (u_int32_t *)tmparray,
581 segsize >> 2);
582 }
583 segptr += segsize;
584 ptr += segsize;
585 cnt -= segsize;
586 }
587
588 /*
589 * Handle leftover, non-word-aligned bytes.
590 */
591 if (resid != 0) {
592 u_int32_t tmpval, tmpval2;
593 bus_size_t ti_offset;
594
595 /*
596 * Set the segment pointer.
597 */
598 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
599
600 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
601
602 /*
603 * First, grab whatever is in our source/destination.
604 * We'll obviously need this for reads, but also for
605 * writes, since we'll be doing read/modify/write.
606 */
607 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
608 ti_offset, &tmpval, 1);
609
610 /*
611 * Next, translate this from little-endian to big-endian
612 * (at least on i386 boxes).
613 */
614 tmpval2 = ntohl(tmpval);
615
616 if (readdata) {
617 /*
618 * If we're reading, just copy the leftover number
619 * of bytes from the host byte order buffer to
620 * the user's buffer.
621 */
622 if (useraddr)
623 copyout(&tmpval2, ptr, resid);
624 else
625 bcopy(&tmpval2, ptr, resid);
626 } else {
627 /*
628 * If we're writing, first copy the bytes to be
629 * written into the network byte order buffer,
630 * leaving the rest of the buffer with whatever was
631 * originally in there. Then, swap the bytes
632 * around into host order and write them out.
633 *
634 * XXX KDM the read side of this has been verified
635 * to work, but the write side of it has not been
636 * verified. So user beware.
637 */
638 if (useraddr)
639 copyin(ptr, &tmpval2, resid);
640 else
641 bcopy(ptr, &tmpval2, resid);
642
643 tmpval = htonl(tmpval2);
644
645 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
646 ti_offset, &tmpval, 1);
647 }
648 }
649
650 CSR_WRITE_4(sc, TI_WINBASE, origwin);
651
652 TI_UNLOCK(sc);
653
654 return (0);
655}
656
657static int
658ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
659 struct ti_softc *sc;
660 u_int32_t tigon_addr, len;
661 caddr_t buf;
662 int useraddr, readdata;
663 int cpu;
664{
665 u_int32_t segptr;
666 int cnt;
667 u_int32_t tmpval, tmpval2;
668 caddr_t ptr;
669
670 /*
671 * At the moment, we don't handle non-aligned cases, we just bail.
672 * If this proves to be a problem, it will be fixed.
673 */
674 if (tigon_addr & 0x3) {
675 printf("ti%d: ti_copy_scratch: tigon address %#x isn't "
676 "word-aligned\n", sc->ti_unit, tigon_addr);
677 return (EINVAL);
678 }
679
680 if (len & 0x3) {
681 printf("ti%d: ti_copy_scratch: transfer length %d isn't "
682 "word-aligned\n", sc->ti_unit, len);
683 return (EINVAL);
684 }
685
686 segptr = tigon_addr;
687 cnt = len;
688 ptr = buf;
689
690 TI_LOCK(sc);
691
692 while (cnt) {
693 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
694
695 if (readdata) {
696 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
697
698 tmpval = ntohl(tmpval2);
699
700 /*
701 * Note: I've used this debugging interface
702 * extensively with Alteon's 12.3.15 firmware,
703 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
704 *
705 * When you compile the firmware without
706 * optimization, which is necessary sometimes in
707 * order to properly step through it, you sometimes
708 * read out a bogus value of 0xc0017c instead of
709 * whatever was supposed to be in that scratchpad
710 * location. That value is on the stack somewhere,
711 * but I've never been able to figure out what was
712 * causing the problem.
713 *
714 * The address seems to pop up in random places,
715 * often not in the same place on two subsequent
716 * reads.
717 *
718 * In any case, the underlying data doesn't seem
719 * to be affected, just the value read out.
720 *
721 * KDM, 3/7/2000
722 */
723
724 if (tmpval2 == 0xc0017c)
725 printf("ti%d: found 0xc0017c at %#x "
726 "(tmpval2)\n", sc->ti_unit, segptr);
727
728 if (tmpval == 0xc0017c)
729 printf("ti%d: found 0xc0017c at %#x "
730 "(tmpval)\n", sc->ti_unit, segptr);
731
732 if (useraddr)
733 copyout(&tmpval, ptr, 4);
734 else
735 bcopy(&tmpval, ptr, 4);
736 } else {
737 if (useraddr)
738 copyin(ptr, &tmpval2, 4);
739 else
740 bcopy(ptr, &tmpval2, 4);
741
742 tmpval = htonl(tmpval2);
743
744 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
745 }
746
747 cnt -= 4;
748 segptr += 4;
749 ptr += 4;
750 }
751
752 TI_UNLOCK(sc);
753
754 return (0);
755}
756
757static int
758ti_bcopy_swap(src, dst, len, swap_type)
759 const void *src;
760 void *dst;
761 size_t len;
762 ti_swap_type swap_type;
763{
764 const u_int8_t *tmpsrc;
765 u_int8_t *tmpdst;
766 size_t tmplen;
767
768 if (len & 0x3) {
769 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
770 len);
771 return (-1);
772 }
773
774 tmpsrc = src;
775 tmpdst = dst;
776 tmplen = len;
777
778 while (tmplen) {
779 if (swap_type == TI_SWAP_NTOH)
780 *(u_int32_t *)tmpdst =
781 ntohl(*(const u_int32_t *)tmpsrc);
782 else
783 *(u_int32_t *)tmpdst =
784 htonl(*(const u_int32_t *)tmpsrc);
785
786 tmpsrc += 4;
787 tmpdst += 4;
788 tmplen -= 4;
789 }
790
791 return (0);
792}
793
794/*
795 * Load firmware image into the NIC. Check that the firmware revision
796 * is acceptable and see if we want the firmware for the Tigon 1 or
797 * Tigon 2.
798 */
799static void
800ti_loadfw(sc)
801 struct ti_softc *sc;
802{
803 switch (sc->ti_hwrev) {
804 case TI_HWREV_TIGON:
805 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
806 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
807 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
808 printf("ti%d: firmware revision mismatch; want "
809 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
810 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
811 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
812 tigonFwReleaseMinor, tigonFwReleaseFix);
813 return;
814 }
815 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
816 (caddr_t)tigonFwText);
817 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
818 (caddr_t)tigonFwData);
819 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
820 (caddr_t)tigonFwRodata);
821 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
822 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
823 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
824 break;
825 case TI_HWREV_TIGON_II:
826 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
827 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
828 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
829 printf("ti%d: firmware revision mismatch; want "
830 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
831 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
832 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
833 tigon2FwReleaseMinor, tigon2FwReleaseFix);
834 return;
835 }
836 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
837 (caddr_t)tigon2FwText);
838 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
839 (caddr_t)tigon2FwData);
840 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
841 (caddr_t)tigon2FwRodata);
842 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
843 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
845 break;
846 default:
847 printf("ti%d: can't load firmware: unknown hardware rev\n",
848 sc->ti_unit);
849 break;
850 }
851}
852
853/*
854 * Send the NIC a command via the command ring.
855 */
856static void
857ti_cmd(sc, cmd)
858 struct ti_softc *sc;
859 struct ti_cmd_desc *cmd;
860{
861 u_int32_t index;
862
863 if (sc->ti_rdata->ti_cmd_ring == NULL)
864 return;
865
866 index = sc->ti_cmd_saved_prodidx;
867 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
868 TI_INC(index, TI_CMD_RING_CNT);
869 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
870 sc->ti_cmd_saved_prodidx = index;
871}
872
873/*
874 * Send the NIC an extended command. The 'len' parameter specifies the
875 * number of command slots to include after the initial command.
876 */
877static void
878ti_cmd_ext(sc, cmd, arg, len)
879 struct ti_softc *sc;
880 struct ti_cmd_desc *cmd;
881 caddr_t arg;
882 int len;
883{
884 u_int32_t index;
885 register int i;
886
887 if (sc->ti_rdata->ti_cmd_ring == NULL)
888 return;
889
890 index = sc->ti_cmd_saved_prodidx;
891 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
892 TI_INC(index, TI_CMD_RING_CNT);
893 for (i = 0; i < len; i++) {
894 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
895 *(u_int32_t *)(&arg[i * 4]));
896 TI_INC(index, TI_CMD_RING_CNT);
897 }
898 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
899 sc->ti_cmd_saved_prodidx = index;
900}
901
902/*
903 * Handle events that have triggered interrupts.
904 */
905static void
906ti_handle_events(sc)
907 struct ti_softc *sc;
908{
909 struct ti_event_desc *e;
910
911 if (sc->ti_rdata->ti_event_ring == NULL)
912 return;
913
914 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
915 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
916 switch (e->ti_event) {
917 case TI_EV_LINKSTAT_CHANGED:
918 sc->ti_linkstat = e->ti_code;
919 if (e->ti_code == TI_EV_CODE_LINK_UP)
920 printf("ti%d: 10/100 link up\n", sc->ti_unit);
921 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
922 printf("ti%d: gigabit link up\n", sc->ti_unit);
923 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
924 printf("ti%d: link down\n", sc->ti_unit);
925 break;
926 case TI_EV_ERROR:
927 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
928 printf("ti%d: invalid command\n", sc->ti_unit);
929 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
930 printf("ti%d: unknown command\n", sc->ti_unit);
931 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
932 printf("ti%d: bad config data\n", sc->ti_unit);
933 break;
934 case TI_EV_FIRMWARE_UP:
935 ti_init2(sc);
936 break;
937 case TI_EV_STATS_UPDATED:
938 ti_stats_update(sc);
939 break;
940 case TI_EV_RESET_JUMBO_RING:
941 case TI_EV_MCAST_UPDATED:
942 /* Who cares. */
943 break;
944 default:
945 printf("ti%d: unknown event: %d\n",
946 sc->ti_unit, e->ti_event);
947 break;
948 }
949 /* Advance the consumer index. */
950 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
951 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
952 }
953}
954
955#ifdef TI_PRIVATE_JUMBOS
956
957/*
958 * Memory management for the jumbo receive ring is a pain in the
959 * butt. We need to allocate at least 9018 bytes of space per frame,
960 * _and_ it has to be contiguous (unless you use the extended
961 * jumbo descriptor format). Using malloc() all the time won't
962 * work: malloc() allocates memory in powers of two, which means we
963 * would end up wasting a considerable amount of space by allocating
964 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
965 * to do our own memory management.
966 *
967 * The driver needs to allocate a contiguous chunk of memory at boot
968 * time. We then chop this up ourselves into 9K pieces and use them
969 * as external mbuf storage.
970 *
971 * One issue here is how much memory to allocate. The jumbo ring has
972 * 256 slots in it, but at 9K per slot than can consume over 2MB of
973 * RAM. This is a bit much, especially considering we also need
974 * RAM for the standard ring and mini ring (on the Tigon 2). To
975 * save space, we only actually allocate enough memory for 64 slots
976 * by default, which works out to between 500 and 600K. This can
977 * be tuned by changing a #define in if_tireg.h.
978 */
979
980static int
981ti_alloc_jumbo_mem(sc)
982 struct ti_softc *sc;
983{
984 caddr_t ptr;
985 register int i;
986 struct ti_jpool_entry *entry;
987
988 /* Grab a big chunk o' storage. */
989 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
990 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
991
992 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
993 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
994 return (ENOBUFS);
995 }
996
997 SLIST_INIT(&sc->ti_jfree_listhead);
998 SLIST_INIT(&sc->ti_jinuse_listhead);
999
1000 /*
1001 * Now divide it up into 9K pieces and save the addresses
1002 * in an array.
1003 */
1004 ptr = sc->ti_cdata.ti_jumbo_buf;
1005 for (i = 0; i < TI_JSLOTS; i++) {
1006 sc->ti_cdata.ti_jslots[i] = ptr;
1007 ptr += TI_JLEN;
1008 entry = malloc(sizeof(struct ti_jpool_entry),
1009 M_DEVBUF, M_NOWAIT);
1010 if (entry == NULL) {
1011 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
1012 M_DEVBUF);
1013 sc->ti_cdata.ti_jumbo_buf = NULL;
1014 printf("ti%d: no memory for jumbo "
1015 "buffer queue!\n", sc->ti_unit);
1016 return (ENOBUFS);
1017 }
1018 entry->slot = i;
1019 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1020 }
1021
1022 return (0);
1023}
1024
1025/*
1026 * Allocate a jumbo buffer.
1027 */
1028static void *ti_jalloc(sc)
1029 struct ti_softc *sc;
1030{
1031 struct ti_jpool_entry *entry;
1032
1033 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1034
1035 if (entry == NULL) {
1036 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
1037 return (NULL);
1038 }
1039
1040 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1041 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1042 return (sc->ti_cdata.ti_jslots[entry->slot]);
1043}
1044
1045/*
1046 * Release a jumbo buffer.
1047 */
1048static void
1049ti_jfree(buf, args)
1050 void *buf;
1051 void *args;
1052{
1053 struct ti_softc *sc;
1054 int i;
1055 struct ti_jpool_entry *entry;
1056
1057 /* Extract the softc struct pointer. */
1058 sc = (struct ti_softc *)args;
1059
1060 if (sc == NULL)
1061 panic("ti_jfree: didn't get softc pointer!");
1062
1063 /* calculate the slot this buffer belongs to */
1064 i = ((vm_offset_t)buf
1065 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1066
1067 if ((i < 0) || (i >= TI_JSLOTS))
1068 panic("ti_jfree: asked to free buffer that we don't manage!");
1069
1070 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1071 if (entry == NULL)
1072 panic("ti_jfree: buffer not in use!");
1073 entry->slot = i;
1074 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1075 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1076}
1077
1078#endif /* TI_PRIVATE_JUMBOS */
1079
1080/*
1081 * Intialize a standard receive ring descriptor.
1082 */
1083static int
1084ti_newbuf_std(sc, i, m)
1085 struct ti_softc *sc;
1086 int i;
1087 struct mbuf *m;
1088{
1089 struct mbuf *m_new = NULL;
1090 struct ti_rx_desc *r;
1091
1092 if (m == NULL) {
1093 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1094 if (m_new == NULL)
1095 return (ENOBUFS);
1096
1097 MCLGET(m_new, M_DONTWAIT);
1098 if (!(m_new->m_flags & M_EXT)) {
1099 m_freem(m_new);
1100 return (ENOBUFS);
1101 }
1102 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1103 } else {
1104 m_new = m;
1105 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1106 m_new->m_data = m_new->m_ext.ext_buf;
1107 }
1108
1109 m_adj(m_new, ETHER_ALIGN);
1110 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1111 r = &sc->ti_rdata->ti_rx_std_ring[i];
1112 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1113 r->ti_type = TI_BDTYPE_RECV_BD;
1114 r->ti_flags = 0;
1115 if (sc->arpcom.ac_if.if_hwassist)
1116 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1117 r->ti_len = m_new->m_len;
1118 r->ti_idx = i;
1119
1120 return (0);
1121}
1122
1123/*
1124 * Intialize a mini receive ring descriptor. This only applies to
1125 * the Tigon 2.
1126 */
1127static int
1128ti_newbuf_mini(sc, i, m)
1129 struct ti_softc *sc;
1130 int i;
1131 struct mbuf *m;
1132{
1133 struct mbuf *m_new = NULL;
1134 struct ti_rx_desc *r;
1135
1136 if (m == NULL) {
1137 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1138 if (m_new == NULL) {
1139 return (ENOBUFS);
1140 }
1141 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1142 } else {
1143 m_new = m;
1144 m_new->m_data = m_new->m_pktdat;
1145 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1146 }
1147
1148 m_adj(m_new, ETHER_ALIGN);
1149 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1150 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1151 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1152 r->ti_type = TI_BDTYPE_RECV_BD;
1153 r->ti_flags = TI_BDFLAG_MINI_RING;
1154 if (sc->arpcom.ac_if.if_hwassist)
1155 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1156 r->ti_len = m_new->m_len;
1157 r->ti_idx = i;
1158
1159 return (0);
1160}
1161
1162#ifdef TI_PRIVATE_JUMBOS
1163
1164/*
1165 * Initialize a jumbo receive ring descriptor. This allocates
1166 * a jumbo buffer from the pool managed internally by the driver.
1167 */
1168static int
1169ti_newbuf_jumbo(sc, i, m)
1170 struct ti_softc *sc;
1171 int i;
1172 struct mbuf *m;
1173{
1174 struct mbuf *m_new = NULL;
1175 struct ti_rx_desc *r;
1176
1177 if (m == NULL) {
1178 caddr_t *buf = NULL;
1179
1180 /* Allocate the mbuf. */
1181 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1182 if (m_new == NULL) {
1183 return (ENOBUFS);
1184 }
1185
1186 /* Allocate the jumbo buffer */
1187 buf = ti_jalloc(sc);
1188 if (buf == NULL) {
1189 m_freem(m_new);
1190 printf("ti%d: jumbo allocation failed "
1191 "-- packet dropped!\n", sc->ti_unit);
1192 return (ENOBUFS);
1193 }
1194
1195 /* Attach the buffer to the mbuf. */
1196 m_new->m_data = (void *) buf;
1197 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1198 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1199 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1200 } else {
1201 m_new = m;
1202 m_new->m_data = m_new->m_ext.ext_buf;
1203 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1204 }
1205
1206 m_adj(m_new, ETHER_ALIGN);
1207 /* Set up the descriptor. */
1208 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1209 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1210 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1211 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1212 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1213 if (sc->arpcom.ac_if.if_hwassist)
1214 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1215 r->ti_len = m_new->m_len;
1216 r->ti_idx = i;
1217
1218 return (0);
1219}
1220
1221#else
1222#include <vm/vm_page.h>
1223
1224#if (PAGE_SIZE == 4096)
1225#define NPAYLOAD 2
1226#else
1227#define NPAYLOAD 1
1228#endif
1229
1230#define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1231#define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1232#define NFS_HDR_LEN (UDP_HDR_LEN)
1233static int HDR_LEN = TCP_HDR_LEN;
1234
1235
1236/*
1237 * Initialize a jumbo receive ring descriptor. This allocates
1238 * a jumbo buffer from the pool managed internally by the driver.
1239 */
1240static int
1241ti_newbuf_jumbo(sc, idx, m_old)
1242 struct ti_softc *sc;
1243 int idx;
1244 struct mbuf *m_old;
1245{
1246 struct mbuf *cur, *m_new = NULL;
1247 struct mbuf *m[3] = {NULL, NULL, NULL};
1248 struct ti_rx_desc_ext *r;
1249 vm_page_t frame;
1250 static int color;
1251 /* 1 extra buf to make nobufs easy*/
1252 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1253 int i;
1254
1255 if (m_old != NULL) {
1256 m_new = m_old;
1257 cur = m_old->m_next;
1258 for (i = 0; i <= NPAYLOAD; i++){
1259 m[i] = cur;
1260 cur = cur->m_next;
1261 }
1262 } else {
1263 /* Allocate the mbufs. */
1264 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1265 if (m_new == NULL) {
1266 printf("ti%d: mbuf allocation failed "
1267 "-- packet dropped!\n", sc->ti_unit);
1268 goto nobufs;
1269 }
1270 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1271 if (m[NPAYLOAD] == NULL) {
1272 printf("ti%d: cluster mbuf allocation failed "
1273 "-- packet dropped!\n", sc->ti_unit);
1274 goto nobufs;
1275 }
1276 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1277 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1278 printf("ti%d: mbuf allocation failed "
1279 "-- packet dropped!\n", sc->ti_unit);
1280 goto nobufs;
1281 }
1282 m[NPAYLOAD]->m_len = MCLBYTES;
1283
1284 for (i = 0; i < NPAYLOAD; i++){
1285 MGET(m[i], M_DONTWAIT, MT_DATA);
1286 if (m[i] == NULL) {
1287 printf("ti%d: mbuf allocation failed "
1288 "-- packet dropped!\n", sc->ti_unit);
1289 goto nobufs;
1290 }
1291 frame = vm_page_alloc(NULL, color++,
1292 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1293 VM_ALLOC_WIRED);
1294 if (frame == NULL) {
1295 printf("ti%d: buffer allocation failed "
1296 "-- packet dropped!\n", sc->ti_unit);
1297 printf(" index %d page %d\n", idx, i);
1298 goto nobufs;
1299 }
1300 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1301 if (sf[i] == NULL) {
1302 vm_page_lock_queues();
1303 vm_page_unwire(frame, 0);
1304 vm_page_free(frame);
1305 vm_page_unlock_queues();
1306 printf("ti%d: buffer allocation failed "
1307 "-- packet dropped!\n", sc->ti_unit);
1308 printf(" index %d page %d\n", idx, i);
1309 goto nobufs;
1310 }
1311 }
1312 for (i = 0; i < NPAYLOAD; i++){
1313 /* Attach the buffer to the mbuf. */
1314 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1315 m[i]->m_len = PAGE_SIZE;
1316 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1317 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE);
1318 m[i]->m_next = m[i+1];
1319 }
1320 /* link the buffers to the header */
1321 m_new->m_next = m[0];
1322 m_new->m_data += ETHER_ALIGN;
1323 if (sc->ti_hdrsplit)
1324 m_new->m_len = MHLEN - ETHER_ALIGN;
1325 else
1326 m_new->m_len = HDR_LEN;
1327 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1328 }
1329
1330 /* Set up the descriptor. */
1331 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1332 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1333 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
1334 r->ti_len0 = m_new->m_len;
1335
1336 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
1337 r->ti_len1 = PAGE_SIZE;
1338
1339 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
1340 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1341
1342 if (PAGE_SIZE == 4096) {
1343 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
1344 r->ti_len3 = MCLBYTES;
1345 } else {
1346 r->ti_len3 = 0;
1347 }
1348 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1349
1350 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1351
1352 if (sc->arpcom.ac_if.if_hwassist)
1353 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1354
1355 r->ti_idx = idx;
1356
1357 return (0);
1358
1359nobufs:
1360
1361 /*
1362 * Warning! :
1363 * This can only be called before the mbufs are strung together.
1364 * If the mbufs are strung together, m_freem() will free the chain,
1365 * so that the later mbufs will be freed multiple times.
1366 */
1367 if (m_new)
1368 m_freem(m_new);
1369
1370 for (i = 0; i < 3; i++) {
1371 if (m[i])
1372 m_freem(m[i]);
1373 if (sf[i])
1374 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1375 }
1376 return (ENOBUFS);
1377}
1378#endif
1379
1380
1381
1382/*
1383 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1384 * that's 1MB or memory, which is a lot. For now, we fill only the first
1385 * 256 ring entries and hope that our CPU is fast enough to keep up with
1386 * the NIC.
1387 */
1388static int
1389ti_init_rx_ring_std(sc)
1390 struct ti_softc *sc;
1391{
1392 register int i;
1393 struct ti_cmd_desc cmd;
1394
1395 for (i = 0; i < TI_SSLOTS; i++) {
1396 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1397 return (ENOBUFS);
1398 };
1399
1400 TI_UPDATE_STDPROD(sc, i - 1);
1401 sc->ti_std = i - 1;
1402
1403 return (0);
1404}
1405
1406static void
1407ti_free_rx_ring_std(sc)
1408 struct ti_softc *sc;
1409{
1410 register int i;
1411
1412 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1413 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1414 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1415 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1416 }
1417 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1418 sizeof(struct ti_rx_desc));
1419 }
1420}
1421
1422static int
1423ti_init_rx_ring_jumbo(sc)
1424 struct ti_softc *sc;
1425{
1426 register int i;
1427 struct ti_cmd_desc cmd;
1428
1429 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1430 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1431 return (ENOBUFS);
1432 };
1433
1434 TI_UPDATE_JUMBOPROD(sc, i - 1);
1435 sc->ti_jumbo = i - 1;
1436
1437 return (0);
1438}
1439
1440static void
1441ti_free_rx_ring_jumbo(sc)
1442 struct ti_softc *sc;
1443{
1444 register int i;
1445
1446 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1447 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1448 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1449 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1450 }
1451 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1452 sizeof(struct ti_rx_desc));
1453 }
1454}
1455
1456static int
1457ti_init_rx_ring_mini(sc)
1458 struct ti_softc *sc;
1459{
1460 register int i;
1461
1462 for (i = 0; i < TI_MSLOTS; i++) {
1463 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1464 return (ENOBUFS);
1465 };
1466
1467 TI_UPDATE_MINIPROD(sc, i - 1);
1468 sc->ti_mini = i - 1;
1469
1470 return (0);
1471}
1472
1473static void
1474ti_free_rx_ring_mini(sc)
1475 struct ti_softc *sc;
1476{
1477 register int i;
1478
1479 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1480 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1481 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1482 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1483 }
1484 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1485 sizeof(struct ti_rx_desc));
1486 }
1487}
1488
1489static void
1490ti_free_tx_ring(sc)
1491 struct ti_softc *sc;
1492{
1493 register int i;
1494
1495 if (sc->ti_rdata->ti_tx_ring == NULL)
1496 return;
1497
1498 for (i = 0; i < TI_TX_RING_CNT; i++) {
1499 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1500 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1501 sc->ti_cdata.ti_tx_chain[i] = NULL;
1502 }
1503 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1504 sizeof(struct ti_tx_desc));
1505 }
1506}
1507
1508static int
1509ti_init_tx_ring(sc)
1510 struct ti_softc *sc;
1511{
1512 sc->ti_txcnt = 0;
1513 sc->ti_tx_saved_considx = 0;
1514 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1515 return (0);
1516}
1517
1518/*
1519 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1520 * but we have to support the old way too so that Tigon 1 cards will
1521 * work.
1522 */
1523static void
1524ti_add_mcast(sc, addr)
1525 struct ti_softc *sc;
1526 struct ether_addr *addr;
1527{
1528 struct ti_cmd_desc cmd;
1529 u_int16_t *m;
1530 u_int32_t ext[2] = {0, 0};
1531
1532 m = (u_int16_t *)&addr->octet[0];
1533
1534 switch (sc->ti_hwrev) {
1535 case TI_HWREV_TIGON:
1536 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1537 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1538 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1539 break;
1540 case TI_HWREV_TIGON_II:
1541 ext[0] = htons(m[0]);
1542 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1543 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1544 break;
1545 default:
1546 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1547 break;
1548 }
1549}
1550
1551static void
1552ti_del_mcast(sc, addr)
1553 struct ti_softc *sc;
1554 struct ether_addr *addr;
1555{
1556 struct ti_cmd_desc cmd;
1557 u_int16_t *m;
1558 u_int32_t ext[2] = {0, 0};
1559
1560 m = (u_int16_t *)&addr->octet[0];
1561
1562 switch (sc->ti_hwrev) {
1563 case TI_HWREV_TIGON:
1564 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1565 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1566 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1567 break;
1568 case TI_HWREV_TIGON_II:
1569 ext[0] = htons(m[0]);
1570 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1571 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1572 break;
1573 default:
1574 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1575 break;
1576 }
1577}
1578
1579/*
1580 * Configure the Tigon's multicast address filter.
1581 *
1582 * The actual multicast table management is a bit of a pain, thanks to
1583 * slight brain damage on the part of both Alteon and us. With our
1584 * multicast code, we are only alerted when the multicast address table
1585 * changes and at that point we only have the current list of addresses:
1586 * we only know the current state, not the previous state, so we don't
1587 * actually know what addresses were removed or added. The firmware has
1588 * state, but we can't get our grubby mits on it, and there is no 'delete
1589 * all multicast addresses' command. Hence, we have to maintain our own
1590 * state so we know what addresses have been programmed into the NIC at
1591 * any given time.
1592 */
1593static void
1594ti_setmulti(sc)
1595 struct ti_softc *sc;
1596{
1597 struct ifnet *ifp;
1598 struct ifmultiaddr *ifma;
1599 struct ti_cmd_desc cmd;
1600 struct ti_mc_entry *mc;
1601 u_int32_t intrs;
1602
1603 ifp = &sc->arpcom.ac_if;
1604
1605 if (ifp->if_flags & IFF_ALLMULTI) {
1606 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1607 return;
1608 } else {
1609 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1610 }
1611
1612 /* Disable interrupts. */
1613 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1614 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1615
1616 /* First, zot all the existing filters. */
1617 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1618 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1619 ti_del_mcast(sc, &mc->mc_addr);
1620 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1621 free(mc, M_DEVBUF);
1622 }
1623
1624 /* Now program new ones. */
1625 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1626 if (ifma->ifma_addr->sa_family != AF_LINK)
1627 continue;
1628 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1629 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1630 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1631 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1632 ti_add_mcast(sc, &mc->mc_addr);
1633 }
1634
1635 /* Re-enable interrupts. */
1636 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1637}
1638
1639/*
1640 * Check to see if the BIOS has configured us for a 64 bit slot when
1641 * we aren't actually in one. If we detect this condition, we can work
1642 * around it on the Tigon 2 by setting a bit in the PCI state register,
1643 * but for the Tigon 1 we must give up and abort the interface attach.
1644 */
1645static int ti_64bitslot_war(sc)
1646 struct ti_softc *sc;
1647{
1648 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1649 CSR_WRITE_4(sc, 0x600, 0);
1650 CSR_WRITE_4(sc, 0x604, 0);
1651 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1652 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1653 if (sc->ti_hwrev == TI_HWREV_TIGON)
1654 return (EINVAL);
1655 else {
1656 TI_SETBIT(sc, TI_PCI_STATE,
1657 TI_PCISTATE_32BIT_BUS);
1658 return (0);
1659 }
1660 }
1661 }
1662
1663 return (0);
1664}
1665
1666/*
1667 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1668 * self-test results.
1669 */
1670static int
1671ti_chipinit(sc)
1672 struct ti_softc *sc;
1673{
1674 u_int32_t cacheline;
1675 u_int32_t pci_writemax = 0;
1676 u_int32_t hdrsplit;
1677
1678 /* Initialize link to down state. */
1679 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1680
1681 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1682 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1683 else
1684 sc->arpcom.ac_if.if_hwassist = 0;
1685
1686 /* Set endianness before we access any non-PCI registers. */
1687#if BYTE_ORDER == BIG_ENDIAN
1688 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1689 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1690#else
1691 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1692 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1693#endif
1694
1695 /* Check the ROM failed bit to see if self-tests passed. */
1696 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1697 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1698 return (ENODEV);
1699 }
1700
1701 /* Halt the CPU. */
1702 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1703
1704 /* Figure out the hardware revision. */
1705 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1706 case TI_REV_TIGON_I:
1707 sc->ti_hwrev = TI_HWREV_TIGON;
1708 break;
1709 case TI_REV_TIGON_II:
1710 sc->ti_hwrev = TI_HWREV_TIGON_II;
1711 break;
1712 default:
1713 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1714 return (ENODEV);
1715 }
1716
1717 /* Do special setup for Tigon 2. */
1718 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1719 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1720 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1721 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1722 }
1723
1724 /*
1725 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1726 * can't do header splitting.
1727 */
1728#ifdef TI_JUMBO_HDRSPLIT
1729 if (sc->ti_hwrev != TI_HWREV_TIGON)
1730 sc->ti_hdrsplit = 1;
1731 else
1732 printf("ti%d: can't do header splitting on a Tigon I board\n",
1733 sc->ti_unit);
1734#endif /* TI_JUMBO_HDRSPLIT */
1735
1736 /* Set up the PCI state register. */
1737 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1738 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1739 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1740 }
1741
1742 /* Clear the read/write max DMA parameters. */
1743 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1744 TI_PCISTATE_READ_MAXDMA));
1745
1746 /* Get cache line size. */
1747 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1748
1749 /*
1750 * If the system has set enabled the PCI memory write
1751 * and invalidate command in the command register, set
1752 * the write max parameter accordingly. This is necessary
1753 * to use MWI with the Tigon 2.
1754 */
1755 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1756 switch (cacheline) {
1757 case 1:
1758 case 4:
1759 case 8:
1760 case 16:
1761 case 32:
1762 case 64:
1763 break;
1764 default:
1765 /* Disable PCI memory write and invalidate. */
1766 if (bootverbose)
1767 printf("ti%d: cache line size %d not "
1768 "supported; disabling PCI MWI\n",
1769 sc->ti_unit, cacheline);
1770 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1771 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1772 break;
1773 }
1774 }
1775
1776#ifdef __brokenalpha__
1777 /*
1778 * From the Alteon sample driver:
1779 * Must insure that we do not cross an 8K (bytes) boundary
1780 * for DMA reads. Our highest limit is 1K bytes. This is a
1781 * restriction on some ALPHA platforms with early revision
1782 * 21174 PCI chipsets, such as the AlphaPC 164lx
1783 */
1784 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1785#else
1786 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1787#endif
1788
1789 /* This sets the min dma param all the way up (0xff). */
1790 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1791
1792 if (sc->ti_hdrsplit)
1793 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1794 else
1795 hdrsplit = 0;
1796
1797 /* Configure DMA variables. */
1798#if BYTE_ORDER == BIG_ENDIAN
1799 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1800 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1801 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1802 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1803#else /* BYTE_ORDER */
1804 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1805 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1806 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1807#endif /* BYTE_ORDER */
1808
1809 /*
1810 * Only allow 1 DMA channel to be active at a time.
1811 * I don't think this is a good idea, but without it
1812 * the firmware racks up lots of nicDmaReadRingFull
1813 * errors. This is not compatible with hardware checksums.
1814 */
1815 if (sc->arpcom.ac_if.if_hwassist == 0)
1816 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1817
1818 /* Recommended settings from Tigon manual. */
1819 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1820 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1821
1822 if (ti_64bitslot_war(sc)) {
1823 printf("ti%d: bios thinks we're in a 64 bit slot, "
1824 "but we aren't", sc->ti_unit);
1825 return (EINVAL);
1826 }
1827
1828 return (0);
1829}
1830
|
2263 if (sc->ti_intrhand)
2264 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2265 if (sc->ti_irq)
2266 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2267 if (sc->ti_res) {
2268 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2269 sc->ti_res);
2270 }
2271
2272#ifdef TI_PRIVATE_JUMBOS
2273 if (sc->ti_cdata.ti_jumbo_buf)
2274 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
2275#endif
2276 if (sc->ti_rdata)
2277 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
2278
2279 TI_UNLOCK(sc);
2280 mtx_destroy(&sc->ti_mtx);
2281
2282 return (0);
2283}
2284
2285#ifdef TI_JUMBO_HDRSPLIT
2286/*
2287 * If hdr_len is 0, that means that header splitting wasn't done on
2288 * this packet for some reason. The two most likely reasons are that
2289 * the protocol isn't a supported protocol for splitting, or this
2290 * packet had a fragment offset that wasn't 0.
2291 *
2292 * The header length, if it is non-zero, will always be the length of
2293 * the headers on the packet, but that length could be longer than the
2294 * first mbuf. So we take the minimum of the two as the actual
2295 * length.
2296 */
2297static __inline void
2298ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2299{
2300 int i = 0;
2301 int lengths[4] = {0, 0, 0, 0};
2302 struct mbuf *m, *mp;
2303
2304 if (hdr_len != 0)
2305 top->m_len = min(hdr_len, top->m_len);
2306 pkt_len -= top->m_len;
2307 lengths[i++] = top->m_len;
2308
2309 mp = top;
2310 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2311 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2312 pkt_len -= m->m_len;
2313 lengths[i++] = m->m_len;
2314 mp = m;
2315 }
2316
2317#if 0
2318 if (hdr_len != 0)
2319 printf("got split packet: ");
2320 else
2321 printf("got non-split packet: ");
2322
2323 printf("%d,%d,%d,%d = %d\n", lengths[0],
2324 lengths[1], lengths[2], lengths[3],
2325 lengths[0] + lengths[1] + lengths[2] +
2326 lengths[3]);
2327#endif
2328
2329 if (pkt_len)
2330 panic("header splitting didn't");
2331
2332 if (m) {
2333 m_freem(m);
2334 mp->m_next = NULL;
2335
2336 }
2337 if (mp->m_next != NULL)
2338 panic("ti_hdr_split: last mbuf in chain should be null");
2339}
2340#endif /* TI_JUMBO_HDRSPLIT */
2341
2342/*
2343 * Frame reception handling. This is called if there's a frame
2344 * on the receive return list.
2345 *
2346 * Note: we have to be able to handle three possibilities here:
2347 * 1) the frame is from the mini receive ring (can only happen)
2348 * on Tigon 2 boards)
2349 * 2) the frame is from the jumbo recieve ring
2350 * 3) the frame is from the standard receive ring
2351 */
2352
2353static void
2354ti_rxeof(sc)
2355 struct ti_softc *sc;
2356{
2357 struct ifnet *ifp;
2358 struct ti_cmd_desc cmd;
2359
2360 TI_LOCK_ASSERT(sc);
2361
2362 ifp = &sc->arpcom.ac_if;
2363
2364 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2365 struct ti_rx_desc *cur_rx;
2366 u_int32_t rxidx;
2367 struct mbuf *m = NULL;
2368 u_int16_t vlan_tag = 0;
2369 int have_tag = 0;
2370
2371 cur_rx =
2372 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2373 rxidx = cur_rx->ti_idx;
2374 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2375
2376 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2377 have_tag = 1;
2378 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2379 }
2380
2381 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2382
2383 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2384 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2385 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2386 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2387 ifp->if_ierrors++;
2388 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2389 continue;
2390 }
2391 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2392 ifp->if_ierrors++;
2393 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2394 continue;
2395 }
2396#ifdef TI_PRIVATE_JUMBOS
2397 m->m_len = cur_rx->ti_len;
2398#else /* TI_PRIVATE_JUMBOS */
2399#ifdef TI_JUMBO_HDRSPLIT
2400 if (sc->ti_hdrsplit)
2401 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2402 cur_rx->ti_len, rxidx);
2403 else
2404#endif /* TI_JUMBO_HDRSPLIT */
2405 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2406#endif /* TI_PRIVATE_JUMBOS */
2407 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2408 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2409 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2410 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2411 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2412 ifp->if_ierrors++;
2413 ti_newbuf_mini(sc, sc->ti_mini, m);
2414 continue;
2415 }
2416 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2417 ifp->if_ierrors++;
2418 ti_newbuf_mini(sc, sc->ti_mini, m);
2419 continue;
2420 }
2421 m->m_len = cur_rx->ti_len;
2422 } else {
2423 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2424 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2425 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2426 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2427 ifp->if_ierrors++;
2428 ti_newbuf_std(sc, sc->ti_std, m);
2429 continue;
2430 }
2431 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2432 ifp->if_ierrors++;
2433 ti_newbuf_std(sc, sc->ti_std, m);
2434 continue;
2435 }
2436 m->m_len = cur_rx->ti_len;
2437 }
2438
2439 m->m_pkthdr.len = cur_rx->ti_len;
2440 ifp->if_ipackets++;
2441 m->m_pkthdr.rcvif = ifp;
2442
2443 if (ifp->if_hwassist) {
2444 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2445 CSUM_DATA_VALID;
2446 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2447 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2448 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2449 }
2450
2451 /*
2452 * If we received a packet with a vlan tag,
2453 * tag it before passing the packet upward.
2454 */
2455 if (have_tag)
2456 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
2457 TI_UNLOCK(sc);
2458 (*ifp->if_input)(ifp, m);
2459 TI_LOCK(sc);
2460 }
2461
2462 /* Only necessary on the Tigon 1. */
2463 if (sc->ti_hwrev == TI_HWREV_TIGON)
2464 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2465 sc->ti_rx_saved_considx);
2466
2467 TI_UPDATE_STDPROD(sc, sc->ti_std);
2468 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2469 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2470}
2471
2472static void
2473ti_txeof(sc)
2474 struct ti_softc *sc;
2475{
2476 struct ti_tx_desc *cur_tx = NULL;
2477 struct ifnet *ifp;
2478
2479 ifp = &sc->arpcom.ac_if;
2480
2481 /*
2482 * Go through our tx ring and free mbufs for those
2483 * frames that have been sent.
2484 */
2485 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2486 u_int32_t idx = 0;
2487
2488 idx = sc->ti_tx_saved_considx;
2489 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2490 if (idx > 383)
2491 CSR_WRITE_4(sc, TI_WINBASE,
2492 TI_TX_RING_BASE + 6144);
2493 else if (idx > 255)
2494 CSR_WRITE_4(sc, TI_WINBASE,
2495 TI_TX_RING_BASE + 4096);
2496 else if (idx > 127)
2497 CSR_WRITE_4(sc, TI_WINBASE,
2498 TI_TX_RING_BASE + 2048);
2499 else
2500 CSR_WRITE_4(sc, TI_WINBASE,
2501 TI_TX_RING_BASE);
2502 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
2503 } else
2504 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2505 if (cur_tx->ti_flags & TI_BDFLAG_END)
2506 ifp->if_opackets++;
2507 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2508 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2509 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2510 }
2511 sc->ti_txcnt--;
2512 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2513 ifp->if_timer = 0;
2514 }
2515
2516 if (cur_tx != NULL)
2517 ifp->if_flags &= ~IFF_OACTIVE;
2518}
2519
2520static void
2521ti_intr(xsc)
2522 void *xsc;
2523{
2524 struct ti_softc *sc;
2525 struct ifnet *ifp;
2526
2527 sc = xsc;
2528 TI_LOCK(sc);
2529 ifp = &sc->arpcom.ac_if;
2530
2531/*#ifdef notdef*/
2532 /* Avoid this for now -- checking this register is expensive. */
2533 /* Make sure this is really our interrupt. */
2534 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2535 TI_UNLOCK(sc);
2536 return;
2537 }
2538/*#endif*/
2539
2540 /* Ack interrupt and stop others from occuring. */
2541 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2542
2543 if (ifp->if_flags & IFF_RUNNING) {
2544 /* Check RX return ring producer/consumer */
2545 ti_rxeof(sc);
2546
2547 /* Check TX ring producer/consumer */
2548 ti_txeof(sc);
2549 }
2550
2551 ti_handle_events(sc);
2552
2553 /* Re-enable interrupts. */
2554 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2555
2556 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2557 ti_start(ifp);
2558
2559 TI_UNLOCK(sc);
2560}
2561
2562static void
2563ti_stats_update(sc)
2564 struct ti_softc *sc;
2565{
2566 struct ifnet *ifp;
2567
2568 ifp = &sc->arpcom.ac_if;
2569
2570 ifp->if_collisions +=
2571 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2572 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2573 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2574 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2575 ifp->if_collisions;
2576}
2577
2578/*
2579 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2580 * pointers to descriptors.
2581 */
2582static int
2583ti_encap(sc, m_head, txidx)
2584 struct ti_softc *sc;
2585 struct mbuf *m_head;
2586 u_int32_t *txidx;
2587{
2588 struct ti_tx_desc *f = NULL;
2589 struct mbuf *m;
2590 u_int32_t frag, cur, cnt = 0;
2591 u_int16_t csum_flags = 0;
2592 struct m_tag *mtag;
2593
2594 m = m_head;
2595 cur = frag = *txidx;
2596
2597 if (m_head->m_pkthdr.csum_flags) {
2598 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2599 csum_flags |= TI_BDFLAG_IP_CKSUM;
2600 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2601 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2602 if (m_head->m_flags & M_LASTFRAG)
2603 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2604 else if (m_head->m_flags & M_FRAG)
2605 csum_flags |= TI_BDFLAG_IP_FRAG;
2606 }
2607
2608 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m);
2609
2610 /*
2611 * Start packing the mbufs in this chain into
2612 * the fragment pointers. Stop when we run out
2613 * of fragments or hit the end of the mbuf chain.
2614 */
2615 for (m = m_head; m != NULL; m = m->m_next) {
2616 if (m->m_len != 0) {
2617 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2618 if (frag > 383)
2619 CSR_WRITE_4(sc, TI_WINBASE,
2620 TI_TX_RING_BASE + 6144);
2621 else if (frag > 255)
2622 CSR_WRITE_4(sc, TI_WINBASE,
2623 TI_TX_RING_BASE + 4096);
2624 else if (frag > 127)
2625 CSR_WRITE_4(sc, TI_WINBASE,
2626 TI_TX_RING_BASE + 2048);
2627 else
2628 CSR_WRITE_4(sc, TI_WINBASE,
2629 TI_TX_RING_BASE);
2630 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2631 } else
2632 f = &sc->ti_rdata->ti_tx_ring[frag];
2633 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2634 break;
2635 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2636 f->ti_len = m->m_len;
2637 f->ti_flags = csum_flags;
2638
2639 if (mtag != NULL) {
2640 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2641 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
2642 } else {
2643 f->ti_vlan_tag = 0;
2644 }
2645
2646 /*
2647 * Sanity check: avoid coming within 16 descriptors
2648 * of the end of the ring.
2649 */
2650 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2651 return (ENOBUFS);
2652 cur = frag;
2653 TI_INC(frag, TI_TX_RING_CNT);
2654 cnt++;
2655 }
2656 }
2657
2658 if (m != NULL)
2659 return (ENOBUFS);
2660
2661 if (frag == sc->ti_tx_saved_considx)
2662 return (ENOBUFS);
2663
2664 if (sc->ti_hwrev == TI_HWREV_TIGON)
2665 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2666 TI_BDFLAG_END;
2667 else
2668 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2669 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2670 sc->ti_txcnt += cnt;
2671
2672 *txidx = frag;
2673
2674 return (0);
2675}
2676
2677/*
2678 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2679 * to the mbuf data regions directly in the transmit descriptors.
2680 */
2681static void
2682ti_start(ifp)
2683 struct ifnet *ifp;
2684{
2685 struct ti_softc *sc;
2686 struct mbuf *m_head = NULL;
2687 u_int32_t prodidx = 0;
2688
2689 sc = ifp->if_softc;
2690 TI_LOCK(sc);
2691
2692 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2693
2694 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2695 IF_DEQUEUE(&ifp->if_snd, m_head);
2696 if (m_head == NULL)
2697 break;
2698
2699 /*
2700 * XXX
2701 * safety overkill. If this is a fragmented packet chain
2702 * with delayed TCP/UDP checksums, then only encapsulate
2703 * it if we have enough descriptors to handle the entire
2704 * chain at once.
2705 * (paranoia -- may not actually be needed)
2706 */
2707 if (m_head->m_flags & M_FIRSTFRAG &&
2708 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2709 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2710 m_head->m_pkthdr.csum_data + 16) {
2711 IF_PREPEND(&ifp->if_snd, m_head);
2712 ifp->if_flags |= IFF_OACTIVE;
2713 break;
2714 }
2715 }
2716
2717 /*
2718 * Pack the data into the transmit ring. If we
2719 * don't have room, set the OACTIVE flag and wait
2720 * for the NIC to drain the ring.
2721 */
2722 if (ti_encap(sc, m_head, &prodidx)) {
2723 IF_PREPEND(&ifp->if_snd, m_head);
2724 ifp->if_flags |= IFF_OACTIVE;
2725 break;
2726 }
2727
2728 /*
2729 * If there's a BPF listener, bounce a copy of this frame
2730 * to him.
2731 */
2732 BPF_MTAP(ifp, m_head);
2733 }
2734
2735 /* Transmit */
2736 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2737
2738 /*
2739 * Set a timeout in case the chip goes out to lunch.
2740 */
2741 ifp->if_timer = 5;
2742 TI_UNLOCK(sc);
2743}
2744
2745static void
2746ti_init(xsc)
2747 void *xsc;
2748{
2749 struct ti_softc *sc = xsc;
2750
2751 /* Cancel pending I/O and flush buffers. */
2752 ti_stop(sc);
2753
2754 TI_LOCK(sc);
2755 /* Init the gen info block, ring control blocks and firmware. */
2756 if (ti_gibinit(sc)) {
2757 printf("ti%d: initialization failure\n", sc->ti_unit);
2758 TI_UNLOCK(sc);
2759 return;
2760 }
2761
2762 TI_UNLOCK(sc);
2763}
2764
2765static void ti_init2(sc)
2766 struct ti_softc *sc;
2767{
2768 struct ti_cmd_desc cmd;
2769 struct ifnet *ifp;
2770 u_int16_t *m;
2771 struct ifmedia *ifm;
2772 int tmp;
2773
2774 ifp = &sc->arpcom.ac_if;
2775
2776 /* Specify MTU and interface index. */
2777 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
2778 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2779 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
2780 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2781
2782 /* Load our MAC address. */
2783 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2784 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2785 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2786 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2787
2788 /* Enable or disable promiscuous mode as needed. */
2789 if (ifp->if_flags & IFF_PROMISC) {
2790 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2791 } else {
2792 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2793 }
2794
2795 /* Program multicast filter. */
2796 ti_setmulti(sc);
2797
2798 /*
2799 * If this is a Tigon 1, we should tell the
2800 * firmware to use software packet filtering.
2801 */
2802 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2803 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2804 }
2805
2806 /* Init RX ring. */
2807 ti_init_rx_ring_std(sc);
2808
2809 /* Init jumbo RX ring. */
2810 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2811 ti_init_rx_ring_jumbo(sc);
2812
2813 /*
2814 * If this is a Tigon 2, we can also configure the
2815 * mini ring.
2816 */
2817 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2818 ti_init_rx_ring_mini(sc);
2819
2820 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2821 sc->ti_rx_saved_considx = 0;
2822
2823 /* Init TX ring. */
2824 ti_init_tx_ring(sc);
2825
2826 /* Tell firmware we're alive. */
2827 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2828
2829 /* Enable host interrupts. */
2830 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2831
2832 ifp->if_flags |= IFF_RUNNING;
2833 ifp->if_flags &= ~IFF_OACTIVE;
2834
2835 /*
2836 * Make sure to set media properly. We have to do this
2837 * here since we have to issue commands in order to set
2838 * the link negotiation and we can't issue commands until
2839 * the firmware is running.
2840 */
2841 ifm = &sc->ifmedia;
2842 tmp = ifm->ifm_media;
2843 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2844 ti_ifmedia_upd(ifp);
2845 ifm->ifm_media = tmp;
2846}
2847
2848/*
2849 * Set media options.
2850 */
2851static int
2852ti_ifmedia_upd(ifp)
2853 struct ifnet *ifp;
2854{
2855 struct ti_softc *sc;
2856 struct ifmedia *ifm;
2857 struct ti_cmd_desc cmd;
2858 u_int32_t flowctl;
2859
2860 sc = ifp->if_softc;
2861 ifm = &sc->ifmedia;
2862
2863 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2864 return (EINVAL);
2865
2866 flowctl = 0;
2867
2868 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2869 case IFM_AUTO:
2870 /*
2871 * Transmit flow control doesn't work on the Tigon 1.
2872 */
2873 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2874
2875 /*
2876 * Transmit flow control can also cause problems on the
2877 * Tigon 2, apparantly with both the copper and fiber
2878 * boards. The symptom is that the interface will just
2879 * hang. This was reproduced with Alteon 180 switches.
2880 */
2881#if 0
2882 if (sc->ti_hwrev != TI_HWREV_TIGON)
2883 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2884#endif
2885
2886 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2887 TI_GLNK_FULL_DUPLEX| flowctl |
2888 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2889
2890 flowctl = TI_LNK_RX_FLOWCTL_Y;
2891#if 0
2892 if (sc->ti_hwrev != TI_HWREV_TIGON)
2893 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2894#endif
2895
2896 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2897 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
2898 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2899 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2900 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2901 break;
2902 case IFM_1000_SX:
2903 case IFM_1000_T:
2904 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2905#if 0
2906 if (sc->ti_hwrev != TI_HWREV_TIGON)
2907 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2908#endif
2909
2910 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2911 flowctl |TI_GLNK_ENB);
2912 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2913 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2914 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2915 }
2916 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2917 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2918 break;
2919 case IFM_100_FX:
2920 case IFM_10_FL:
2921 case IFM_100_TX:
2922 case IFM_10_T:
2923 flowctl = TI_LNK_RX_FLOWCTL_Y;
2924#if 0
2925 if (sc->ti_hwrev != TI_HWREV_TIGON)
2926 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2927#endif
2928
2929 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2930 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
2931 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2932 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2933 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2934 } else {
2935 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2936 }
2937 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2938 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2939 } else {
2940 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2941 }
2942 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2943 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2944 break;
2945 }
2946
2947 return (0);
2948}
2949
2950/*
2951 * Report current media status.
2952 */
2953static void
2954ti_ifmedia_sts(ifp, ifmr)
2955 struct ifnet *ifp;
2956 struct ifmediareq *ifmr;
2957{
2958 struct ti_softc *sc;
2959 u_int32_t media = 0;
2960
2961 sc = ifp->if_softc;
2962
2963 ifmr->ifm_status = IFM_AVALID;
2964 ifmr->ifm_active = IFM_ETHER;
2965
2966 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2967 return;
2968
2969 ifmr->ifm_status |= IFM_ACTIVE;
2970
2971 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2972 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2973 if (sc->ti_copper)
2974 ifmr->ifm_active |= IFM_1000_T;
2975 else
2976 ifmr->ifm_active |= IFM_1000_SX;
2977 if (media & TI_GLNK_FULL_DUPLEX)
2978 ifmr->ifm_active |= IFM_FDX;
2979 else
2980 ifmr->ifm_active |= IFM_HDX;
2981 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2982 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2983 if (sc->ti_copper) {
2984 if (media & TI_LNK_100MB)
2985 ifmr->ifm_active |= IFM_100_TX;
2986 if (media & TI_LNK_10MB)
2987 ifmr->ifm_active |= IFM_10_T;
2988 } else {
2989 if (media & TI_LNK_100MB)
2990 ifmr->ifm_active |= IFM_100_FX;
2991 if (media & TI_LNK_10MB)
2992 ifmr->ifm_active |= IFM_10_FL;
2993 }
2994 if (media & TI_LNK_FULL_DUPLEX)
2995 ifmr->ifm_active |= IFM_FDX;
2996 if (media & TI_LNK_HALF_DUPLEX)
2997 ifmr->ifm_active |= IFM_HDX;
2998 }
2999}
3000
3001static int
3002ti_ioctl(ifp, command, data)
3003 struct ifnet *ifp;
3004 u_long command;
3005 caddr_t data;
3006{
3007 struct ti_softc *sc = ifp->if_softc;
3008 struct ifreq *ifr = (struct ifreq *) data;
3009 int mask, error = 0;
3010 struct ti_cmd_desc cmd;
3011
3012 TI_LOCK(sc);
3013
3014 switch (command) {
3015 case SIOCSIFMTU:
3016 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3017 error = EINVAL;
3018 else {
3019 ifp->if_mtu = ifr->ifr_mtu;
3020 ti_init(sc);
3021 }
3022 break;
3023 case SIOCSIFFLAGS:
3024 if (ifp->if_flags & IFF_UP) {
3025 /*
3026 * If only the state of the PROMISC flag changed,
3027 * then just use the 'set promisc mode' command
3028 * instead of reinitializing the entire NIC. Doing
3029 * a full re-init means reloading the firmware and
3030 * waiting for it to start up, which may take a
3031 * second or two.
3032 */
3033 if (ifp->if_flags & IFF_RUNNING &&
3034 ifp->if_flags & IFF_PROMISC &&
3035 !(sc->ti_if_flags & IFF_PROMISC)) {
3036 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3037 TI_CMD_CODE_PROMISC_ENB, 0);
3038 } else if (ifp->if_flags & IFF_RUNNING &&
3039 !(ifp->if_flags & IFF_PROMISC) &&
3040 sc->ti_if_flags & IFF_PROMISC) {
3041 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3042 TI_CMD_CODE_PROMISC_DIS, 0);
3043 } else
3044 ti_init(sc);
3045 } else {
3046 if (ifp->if_flags & IFF_RUNNING) {
3047 ti_stop(sc);
3048 }
3049 }
3050 sc->ti_if_flags = ifp->if_flags;
3051 error = 0;
3052 break;
3053 case SIOCADDMULTI:
3054 case SIOCDELMULTI:
3055 if (ifp->if_flags & IFF_RUNNING) {
3056 ti_setmulti(sc);
3057 error = 0;
3058 }
3059 break;
3060 case SIOCSIFMEDIA:
3061 case SIOCGIFMEDIA:
3062 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3063 break;
3064 case SIOCSIFCAP:
3065 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3066 if (mask & IFCAP_HWCSUM) {
3067 if (IFCAP_HWCSUM & ifp->if_capenable)
3068 ifp->if_capenable &= ~IFCAP_HWCSUM;
3069 else
3070 ifp->if_capenable |= IFCAP_HWCSUM;
3071 if (ifp->if_flags & IFF_RUNNING)
3072 ti_init(sc);
3073 }
3074 error = 0;
3075 break;
3076 default:
3077 error = ether_ioctl(ifp, command, data);
3078 break;
3079 }
3080
3081 TI_UNLOCK(sc);
3082
3083 return (error);
3084}
3085
3086static int
3087ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3088{
3089 struct ti_softc *sc;
3090
3091 sc = dev->si_drv1;
3092 if (sc == NULL)
3093 return (ENODEV);
3094
3095 TI_LOCK(sc);
3096 sc->ti_flags |= TI_FLAG_DEBUGING;
3097 TI_UNLOCK(sc);
3098
3099 return (0);
3100}
3101
3102static int
3103ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3104{
3105 struct ti_softc *sc;
3106
3107 sc = dev->si_drv1;
3108 if (sc == NULL)
3109 return (ENODEV);
3110
3111 TI_LOCK(sc);
3112 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3113 TI_UNLOCK(sc);
3114
3115 return (0);
3116}
3117
3118/*
3119 * This ioctl routine goes along with the Tigon character device.
3120 */
3121static int
3122ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
3123{
3124 int error;
3125 struct ti_softc *sc;
3126
3127 sc = dev->si_drv1;
3128 if (sc == NULL)
3129 return (ENODEV);
3130
3131 error = 0;
3132
3133 switch (cmd) {
3134 case TIIOCGETSTATS:
3135 {
3136 struct ti_stats *outstats;
3137
3138 outstats = (struct ti_stats *)addr;
3139
3140 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3141 sizeof(struct ti_stats));
3142 break;
3143 }
3144 case TIIOCGETPARAMS:
3145 {
3146 struct ti_params *params;
3147
3148 params = (struct ti_params *)addr;
3149
3150 params->ti_stat_ticks = sc->ti_stat_ticks;
3151 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3152 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3153 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3154 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3155 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3156 params->param_mask = TI_PARAM_ALL;
3157
3158 error = 0;
3159
3160 break;
3161 }
3162 case TIIOCSETPARAMS:
3163 {
3164 struct ti_params *params;
3165
3166 params = (struct ti_params *)addr;
3167
3168 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3169 sc->ti_stat_ticks = params->ti_stat_ticks;
3170 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3171 }
3172
3173 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3174 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3175 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3176 sc->ti_rx_coal_ticks);
3177 }
3178
3179 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3180 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3181 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3182 sc->ti_tx_coal_ticks);
3183 }
3184
3185 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3186 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3187 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3188 sc->ti_rx_max_coal_bds);
3189 }
3190
3191 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3192 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3193 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3194 sc->ti_tx_max_coal_bds);
3195 }
3196
3197 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3198 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3199 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3200 sc->ti_tx_buf_ratio);
3201 }
3202
3203 error = 0;
3204
3205 break;
3206 }
3207 case TIIOCSETTRACE: {
3208 ti_trace_type trace_type;
3209
3210 trace_type = *(ti_trace_type *)addr;
3211
3212 /*
3213 * Set tracing to whatever the user asked for. Setting
3214 * this register to 0 should have the effect of disabling
3215 * tracing.
3216 */
3217 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3218
3219 error = 0;
3220
3221 break;
3222 }
3223 case TIIOCGETTRACE: {
3224 struct ti_trace_buf *trace_buf;
3225 u_int32_t trace_start, cur_trace_ptr, trace_len;
3226
3227 trace_buf = (struct ti_trace_buf *)addr;
3228
3229 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3230 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3231 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3232
3233#if 0
3234 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
3235 "trace_len = %d\n", sc->ti_unit, trace_start,
3236 cur_trace_ptr, trace_len);
3237 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
3238 trace_buf->buf_len);
3239#endif
3240
3241 error = ti_copy_mem(sc, trace_start, min(trace_len,
3242 trace_buf->buf_len),
3243 (caddr_t)trace_buf->buf, 1, 1);
3244
3245 if (error == 0) {
3246 trace_buf->fill_len = min(trace_len,
3247 trace_buf->buf_len);
3248 if (cur_trace_ptr < trace_start)
3249 trace_buf->cur_trace_ptr =
3250 trace_start - cur_trace_ptr;
3251 else
3252 trace_buf->cur_trace_ptr =
3253 cur_trace_ptr - trace_start;
3254 } else
3255 trace_buf->fill_len = 0;
3256
3257 break;
3258 }
3259
3260 /*
3261 * For debugging, five ioctls are needed:
3262 * ALT_ATTACH
3263 * ALT_READ_TG_REG
3264 * ALT_WRITE_TG_REG
3265 * ALT_READ_TG_MEM
3266 * ALT_WRITE_TG_MEM
3267 */
3268 case ALT_ATTACH:
3269 /*
3270 * From what I can tell, Alteon's Solaris Tigon driver
3271 * only has one character device, so you have to attach
3272 * to the Tigon board you're interested in. This seems
3273 * like a not-so-good way to do things, since unless you
3274 * subsequently specify the unit number of the device
3275 * you're interested in in every ioctl, you'll only be
3276 * able to debug one board at a time.
3277 */
3278 error = 0;
3279 break;
3280 case ALT_READ_TG_MEM:
3281 case ALT_WRITE_TG_MEM:
3282 {
3283 struct tg_mem *mem_param;
3284 u_int32_t sram_end, scratch_end;
3285
3286 mem_param = (struct tg_mem *)addr;
3287
3288 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3289 sram_end = TI_END_SRAM_I;
3290 scratch_end = TI_END_SCRATCH_I;
3291 } else {
3292 sram_end = TI_END_SRAM_II;
3293 scratch_end = TI_END_SCRATCH_II;
3294 }
3295
3296 /*
3297 * For now, we'll only handle accessing regular SRAM,
3298 * nothing else.
3299 */
3300 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3301 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3302 /*
3303 * In this instance, we always copy to/from user
3304 * space, so the user space argument is set to 1.
3305 */
3306 error = ti_copy_mem(sc, mem_param->tgAddr,
3307 mem_param->len,
3308 mem_param->userAddr, 1,
3309 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3310 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3311 && (mem_param->tgAddr <= scratch_end)) {
3312 error = ti_copy_scratch(sc, mem_param->tgAddr,
3313 mem_param->len,
3314 mem_param->userAddr, 1,
3315 (cmd == ALT_READ_TG_MEM) ?
3316 1 : 0, TI_PROCESSOR_A);
3317 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3318 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3319 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3320 printf("ti%d: invalid memory range for "
3321 "Tigon I\n", sc->ti_unit);
3322 error = EINVAL;
3323 break;
3324 }
3325 error = ti_copy_scratch(sc, mem_param->tgAddr -
3326 TI_SCRATCH_DEBUG_OFF,
3327 mem_param->len,
3328 mem_param->userAddr, 1,
3329 (cmd == ALT_READ_TG_MEM) ?
3330 1 : 0, TI_PROCESSOR_B);
3331 } else {
3332 printf("ti%d: memory address %#x len %d is out of "
3333 "supported range\n", sc->ti_unit,
3334 mem_param->tgAddr, mem_param->len);
3335 error = EINVAL;
3336 }
3337
3338 break;
3339 }
3340 case ALT_READ_TG_REG:
3341 case ALT_WRITE_TG_REG:
3342 {
3343 struct tg_reg *regs;
3344 u_int32_t tmpval;
3345
3346 regs = (struct tg_reg *)addr;
3347
3348 /*
3349 * Make sure the address in question isn't out of range.
3350 */
3351 if (regs->addr > TI_REG_MAX) {
3352 error = EINVAL;
3353 break;
3354 }
3355 if (cmd == ALT_READ_TG_REG) {
3356 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3357 regs->addr, &tmpval, 1);
3358 regs->data = ntohl(tmpval);
3359#if 0
3360 if ((regs->addr == TI_CPU_STATE)
3361 || (regs->addr == TI_CPU_CTL_B)) {
3362 printf("ti%d: register %#x = %#x\n",
3363 sc->ti_unit, regs->addr, tmpval);
3364 }
3365#endif
3366 } else {
3367 tmpval = htonl(regs->data);
3368 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3369 regs->addr, &tmpval, 1);
3370 }
3371
3372 break;
3373 }
3374 default:
3375 error = ENOTTY;
3376 break;
3377 }
3378 return (error);
3379}
3380
3381static void
3382ti_watchdog(ifp)
3383 struct ifnet *ifp;
3384{
3385 struct ti_softc *sc;
3386
3387 sc = ifp->if_softc;
3388 TI_LOCK(sc);
3389
3390 /*
3391 * When we're debugging, the chip is often stopped for long periods
3392 * of time, and that would normally cause the watchdog timer to fire.
3393 * Since that impedes debugging, we don't want to do that.
3394 */
3395 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3396 TI_UNLOCK(sc);
3397 return;
3398 }
3399
3400 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
3401 ti_stop(sc);
3402 ti_init(sc);
3403
3404 ifp->if_oerrors++;
3405 TI_UNLOCK(sc);
3406}
3407
3408/*
3409 * Stop the adapter and free any mbufs allocated to the
3410 * RX and TX lists.
3411 */
3412static void
3413ti_stop(sc)
3414 struct ti_softc *sc;
3415{
3416 struct ifnet *ifp;
3417 struct ti_cmd_desc cmd;
3418
3419 TI_LOCK(sc);
3420
3421 ifp = &sc->arpcom.ac_if;
3422
3423 /* Disable host interrupts. */
3424 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3425 /*
3426 * Tell firmware we're shutting down.
3427 */
3428 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3429
3430 /* Halt and reinitialize. */
3431 ti_chipinit(sc);
3432 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
3433 ti_chipinit(sc);
3434
3435 /* Free the RX lists. */
3436 ti_free_rx_ring_std(sc);
3437
3438 /* Free jumbo RX list. */
3439 ti_free_rx_ring_jumbo(sc);
3440
3441 /* Free mini RX list. */
3442 ti_free_rx_ring_mini(sc);
3443
3444 /* Free TX buffers. */
3445 ti_free_tx_ring(sc);
3446
3447 sc->ti_ev_prodidx.ti_idx = 0;
3448 sc->ti_return_prodidx.ti_idx = 0;
3449 sc->ti_tx_considx.ti_idx = 0;
3450 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3451
3452 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3453 TI_UNLOCK(sc);
3454}
3455
3456/*
3457 * Stop all chip I/O so that the kernel's probe routines don't
3458 * get confused by errant DMAs when rebooting.
3459 */
3460static void
3461ti_shutdown(dev)
3462 device_t dev;
3463{
3464 struct ti_softc *sc;
3465
3466 sc = device_get_softc(dev);
3467 TI_LOCK(sc);
3468 ti_chipinit(sc);
3469 TI_UNLOCK(sc);
3470}
| 2330 if (sc->ti_intrhand)
2331 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2332 if (sc->ti_irq)
2333 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2334 if (sc->ti_res) {
2335 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2336 sc->ti_res);
2337 }
2338
2339#ifdef TI_PRIVATE_JUMBOS
2340 if (sc->ti_cdata.ti_jumbo_buf)
2341 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
2342#endif
2343 if (sc->ti_rdata)
2344 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
2345
2346 TI_UNLOCK(sc);
2347 mtx_destroy(&sc->ti_mtx);
2348
2349 return (0);
2350}
2351
2352#ifdef TI_JUMBO_HDRSPLIT
2353/*
2354 * If hdr_len is 0, that means that header splitting wasn't done on
2355 * this packet for some reason. The two most likely reasons are that
2356 * the protocol isn't a supported protocol for splitting, or this
2357 * packet had a fragment offset that wasn't 0.
2358 *
2359 * The header length, if it is non-zero, will always be the length of
2360 * the headers on the packet, but that length could be longer than the
2361 * first mbuf. So we take the minimum of the two as the actual
2362 * length.
2363 */
2364static __inline void
2365ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2366{
2367 int i = 0;
2368 int lengths[4] = {0, 0, 0, 0};
2369 struct mbuf *m, *mp;
2370
2371 if (hdr_len != 0)
2372 top->m_len = min(hdr_len, top->m_len);
2373 pkt_len -= top->m_len;
2374 lengths[i++] = top->m_len;
2375
2376 mp = top;
2377 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2378 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2379 pkt_len -= m->m_len;
2380 lengths[i++] = m->m_len;
2381 mp = m;
2382 }
2383
2384#if 0
2385 if (hdr_len != 0)
2386 printf("got split packet: ");
2387 else
2388 printf("got non-split packet: ");
2389
2390 printf("%d,%d,%d,%d = %d\n", lengths[0],
2391 lengths[1], lengths[2], lengths[3],
2392 lengths[0] + lengths[1] + lengths[2] +
2393 lengths[3]);
2394#endif
2395
2396 if (pkt_len)
2397 panic("header splitting didn't");
2398
2399 if (m) {
2400 m_freem(m);
2401 mp->m_next = NULL;
2402
2403 }
2404 if (mp->m_next != NULL)
2405 panic("ti_hdr_split: last mbuf in chain should be null");
2406}
2407#endif /* TI_JUMBO_HDRSPLIT */
2408
2409/*
2410 * Frame reception handling. This is called if there's a frame
2411 * on the receive return list.
2412 *
2413 * Note: we have to be able to handle three possibilities here:
2414 * 1) the frame is from the mini receive ring (can only happen)
2415 * on Tigon 2 boards)
2416 * 2) the frame is from the jumbo recieve ring
2417 * 3) the frame is from the standard receive ring
2418 */
2419
2420static void
2421ti_rxeof(sc)
2422 struct ti_softc *sc;
2423{
2424 struct ifnet *ifp;
2425 struct ti_cmd_desc cmd;
2426
2427 TI_LOCK_ASSERT(sc);
2428
2429 ifp = &sc->arpcom.ac_if;
2430
2431 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2432 struct ti_rx_desc *cur_rx;
2433 u_int32_t rxidx;
2434 struct mbuf *m = NULL;
2435 u_int16_t vlan_tag = 0;
2436 int have_tag = 0;
2437
2438 cur_rx =
2439 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2440 rxidx = cur_rx->ti_idx;
2441 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2442
2443 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2444 have_tag = 1;
2445 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2446 }
2447
2448 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2449
2450 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2451 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2452 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2453 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2454 ifp->if_ierrors++;
2455 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2456 continue;
2457 }
2458 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2459 ifp->if_ierrors++;
2460 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2461 continue;
2462 }
2463#ifdef TI_PRIVATE_JUMBOS
2464 m->m_len = cur_rx->ti_len;
2465#else /* TI_PRIVATE_JUMBOS */
2466#ifdef TI_JUMBO_HDRSPLIT
2467 if (sc->ti_hdrsplit)
2468 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2469 cur_rx->ti_len, rxidx);
2470 else
2471#endif /* TI_JUMBO_HDRSPLIT */
2472 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2473#endif /* TI_PRIVATE_JUMBOS */
2474 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2475 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2476 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2477 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2478 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2479 ifp->if_ierrors++;
2480 ti_newbuf_mini(sc, sc->ti_mini, m);
2481 continue;
2482 }
2483 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2484 ifp->if_ierrors++;
2485 ti_newbuf_mini(sc, sc->ti_mini, m);
2486 continue;
2487 }
2488 m->m_len = cur_rx->ti_len;
2489 } else {
2490 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2491 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2492 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2493 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2494 ifp->if_ierrors++;
2495 ti_newbuf_std(sc, sc->ti_std, m);
2496 continue;
2497 }
2498 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2499 ifp->if_ierrors++;
2500 ti_newbuf_std(sc, sc->ti_std, m);
2501 continue;
2502 }
2503 m->m_len = cur_rx->ti_len;
2504 }
2505
2506 m->m_pkthdr.len = cur_rx->ti_len;
2507 ifp->if_ipackets++;
2508 m->m_pkthdr.rcvif = ifp;
2509
2510 if (ifp->if_hwassist) {
2511 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2512 CSUM_DATA_VALID;
2513 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2514 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2515 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2516 }
2517
2518 /*
2519 * If we received a packet with a vlan tag,
2520 * tag it before passing the packet upward.
2521 */
2522 if (have_tag)
2523 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
2524 TI_UNLOCK(sc);
2525 (*ifp->if_input)(ifp, m);
2526 TI_LOCK(sc);
2527 }
2528
2529 /* Only necessary on the Tigon 1. */
2530 if (sc->ti_hwrev == TI_HWREV_TIGON)
2531 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2532 sc->ti_rx_saved_considx);
2533
2534 TI_UPDATE_STDPROD(sc, sc->ti_std);
2535 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2536 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2537}
2538
2539static void
2540ti_txeof(sc)
2541 struct ti_softc *sc;
2542{
2543 struct ti_tx_desc *cur_tx = NULL;
2544 struct ifnet *ifp;
2545
2546 ifp = &sc->arpcom.ac_if;
2547
2548 /*
2549 * Go through our tx ring and free mbufs for those
2550 * frames that have been sent.
2551 */
2552 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2553 u_int32_t idx = 0;
2554
2555 idx = sc->ti_tx_saved_considx;
2556 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2557 if (idx > 383)
2558 CSR_WRITE_4(sc, TI_WINBASE,
2559 TI_TX_RING_BASE + 6144);
2560 else if (idx > 255)
2561 CSR_WRITE_4(sc, TI_WINBASE,
2562 TI_TX_RING_BASE + 4096);
2563 else if (idx > 127)
2564 CSR_WRITE_4(sc, TI_WINBASE,
2565 TI_TX_RING_BASE + 2048);
2566 else
2567 CSR_WRITE_4(sc, TI_WINBASE,
2568 TI_TX_RING_BASE);
2569 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
2570 } else
2571 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2572 if (cur_tx->ti_flags & TI_BDFLAG_END)
2573 ifp->if_opackets++;
2574 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2575 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2576 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2577 }
2578 sc->ti_txcnt--;
2579 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2580 ifp->if_timer = 0;
2581 }
2582
2583 if (cur_tx != NULL)
2584 ifp->if_flags &= ~IFF_OACTIVE;
2585}
2586
2587static void
2588ti_intr(xsc)
2589 void *xsc;
2590{
2591 struct ti_softc *sc;
2592 struct ifnet *ifp;
2593
2594 sc = xsc;
2595 TI_LOCK(sc);
2596 ifp = &sc->arpcom.ac_if;
2597
2598/*#ifdef notdef*/
2599 /* Avoid this for now -- checking this register is expensive. */
2600 /* Make sure this is really our interrupt. */
2601 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2602 TI_UNLOCK(sc);
2603 return;
2604 }
2605/*#endif*/
2606
2607 /* Ack interrupt and stop others from occuring. */
2608 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2609
2610 if (ifp->if_flags & IFF_RUNNING) {
2611 /* Check RX return ring producer/consumer */
2612 ti_rxeof(sc);
2613
2614 /* Check TX ring producer/consumer */
2615 ti_txeof(sc);
2616 }
2617
2618 ti_handle_events(sc);
2619
2620 /* Re-enable interrupts. */
2621 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2622
2623 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2624 ti_start(ifp);
2625
2626 TI_UNLOCK(sc);
2627}
2628
2629static void
2630ti_stats_update(sc)
2631 struct ti_softc *sc;
2632{
2633 struct ifnet *ifp;
2634
2635 ifp = &sc->arpcom.ac_if;
2636
2637 ifp->if_collisions +=
2638 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2639 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2640 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2641 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2642 ifp->if_collisions;
2643}
2644
2645/*
2646 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2647 * pointers to descriptors.
2648 */
2649static int
2650ti_encap(sc, m_head, txidx)
2651 struct ti_softc *sc;
2652 struct mbuf *m_head;
2653 u_int32_t *txidx;
2654{
2655 struct ti_tx_desc *f = NULL;
2656 struct mbuf *m;
2657 u_int32_t frag, cur, cnt = 0;
2658 u_int16_t csum_flags = 0;
2659 struct m_tag *mtag;
2660
2661 m = m_head;
2662 cur = frag = *txidx;
2663
2664 if (m_head->m_pkthdr.csum_flags) {
2665 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2666 csum_flags |= TI_BDFLAG_IP_CKSUM;
2667 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2668 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2669 if (m_head->m_flags & M_LASTFRAG)
2670 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2671 else if (m_head->m_flags & M_FRAG)
2672 csum_flags |= TI_BDFLAG_IP_FRAG;
2673 }
2674
2675 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m);
2676
2677 /*
2678 * Start packing the mbufs in this chain into
2679 * the fragment pointers. Stop when we run out
2680 * of fragments or hit the end of the mbuf chain.
2681 */
2682 for (m = m_head; m != NULL; m = m->m_next) {
2683 if (m->m_len != 0) {
2684 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2685 if (frag > 383)
2686 CSR_WRITE_4(sc, TI_WINBASE,
2687 TI_TX_RING_BASE + 6144);
2688 else if (frag > 255)
2689 CSR_WRITE_4(sc, TI_WINBASE,
2690 TI_TX_RING_BASE + 4096);
2691 else if (frag > 127)
2692 CSR_WRITE_4(sc, TI_WINBASE,
2693 TI_TX_RING_BASE + 2048);
2694 else
2695 CSR_WRITE_4(sc, TI_WINBASE,
2696 TI_TX_RING_BASE);
2697 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2698 } else
2699 f = &sc->ti_rdata->ti_tx_ring[frag];
2700 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2701 break;
2702 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2703 f->ti_len = m->m_len;
2704 f->ti_flags = csum_flags;
2705
2706 if (mtag != NULL) {
2707 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2708 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
2709 } else {
2710 f->ti_vlan_tag = 0;
2711 }
2712
2713 /*
2714 * Sanity check: avoid coming within 16 descriptors
2715 * of the end of the ring.
2716 */
2717 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2718 return (ENOBUFS);
2719 cur = frag;
2720 TI_INC(frag, TI_TX_RING_CNT);
2721 cnt++;
2722 }
2723 }
2724
2725 if (m != NULL)
2726 return (ENOBUFS);
2727
2728 if (frag == sc->ti_tx_saved_considx)
2729 return (ENOBUFS);
2730
2731 if (sc->ti_hwrev == TI_HWREV_TIGON)
2732 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2733 TI_BDFLAG_END;
2734 else
2735 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2736 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2737 sc->ti_txcnt += cnt;
2738
2739 *txidx = frag;
2740
2741 return (0);
2742}
2743
2744/*
2745 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2746 * to the mbuf data regions directly in the transmit descriptors.
2747 */
2748static void
2749ti_start(ifp)
2750 struct ifnet *ifp;
2751{
2752 struct ti_softc *sc;
2753 struct mbuf *m_head = NULL;
2754 u_int32_t prodidx = 0;
2755
2756 sc = ifp->if_softc;
2757 TI_LOCK(sc);
2758
2759 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2760
2761 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2762 IF_DEQUEUE(&ifp->if_snd, m_head);
2763 if (m_head == NULL)
2764 break;
2765
2766 /*
2767 * XXX
2768 * safety overkill. If this is a fragmented packet chain
2769 * with delayed TCP/UDP checksums, then only encapsulate
2770 * it if we have enough descriptors to handle the entire
2771 * chain at once.
2772 * (paranoia -- may not actually be needed)
2773 */
2774 if (m_head->m_flags & M_FIRSTFRAG &&
2775 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2776 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2777 m_head->m_pkthdr.csum_data + 16) {
2778 IF_PREPEND(&ifp->if_snd, m_head);
2779 ifp->if_flags |= IFF_OACTIVE;
2780 break;
2781 }
2782 }
2783
2784 /*
2785 * Pack the data into the transmit ring. If we
2786 * don't have room, set the OACTIVE flag and wait
2787 * for the NIC to drain the ring.
2788 */
2789 if (ti_encap(sc, m_head, &prodidx)) {
2790 IF_PREPEND(&ifp->if_snd, m_head);
2791 ifp->if_flags |= IFF_OACTIVE;
2792 break;
2793 }
2794
2795 /*
2796 * If there's a BPF listener, bounce a copy of this frame
2797 * to him.
2798 */
2799 BPF_MTAP(ifp, m_head);
2800 }
2801
2802 /* Transmit */
2803 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2804
2805 /*
2806 * Set a timeout in case the chip goes out to lunch.
2807 */
2808 ifp->if_timer = 5;
2809 TI_UNLOCK(sc);
2810}
2811
2812static void
2813ti_init(xsc)
2814 void *xsc;
2815{
2816 struct ti_softc *sc = xsc;
2817
2818 /* Cancel pending I/O and flush buffers. */
2819 ti_stop(sc);
2820
2821 TI_LOCK(sc);
2822 /* Init the gen info block, ring control blocks and firmware. */
2823 if (ti_gibinit(sc)) {
2824 printf("ti%d: initialization failure\n", sc->ti_unit);
2825 TI_UNLOCK(sc);
2826 return;
2827 }
2828
2829 TI_UNLOCK(sc);
2830}
2831
2832static void ti_init2(sc)
2833 struct ti_softc *sc;
2834{
2835 struct ti_cmd_desc cmd;
2836 struct ifnet *ifp;
2837 u_int16_t *m;
2838 struct ifmedia *ifm;
2839 int tmp;
2840
2841 ifp = &sc->arpcom.ac_if;
2842
2843 /* Specify MTU and interface index. */
2844 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
2845 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2846 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
2847 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2848
2849 /* Load our MAC address. */
2850 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2851 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2852 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2853 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2854
2855 /* Enable or disable promiscuous mode as needed. */
2856 if (ifp->if_flags & IFF_PROMISC) {
2857 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2858 } else {
2859 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2860 }
2861
2862 /* Program multicast filter. */
2863 ti_setmulti(sc);
2864
2865 /*
2866 * If this is a Tigon 1, we should tell the
2867 * firmware to use software packet filtering.
2868 */
2869 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2870 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2871 }
2872
2873 /* Init RX ring. */
2874 ti_init_rx_ring_std(sc);
2875
2876 /* Init jumbo RX ring. */
2877 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2878 ti_init_rx_ring_jumbo(sc);
2879
2880 /*
2881 * If this is a Tigon 2, we can also configure the
2882 * mini ring.
2883 */
2884 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2885 ti_init_rx_ring_mini(sc);
2886
2887 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2888 sc->ti_rx_saved_considx = 0;
2889
2890 /* Init TX ring. */
2891 ti_init_tx_ring(sc);
2892
2893 /* Tell firmware we're alive. */
2894 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2895
2896 /* Enable host interrupts. */
2897 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2898
2899 ifp->if_flags |= IFF_RUNNING;
2900 ifp->if_flags &= ~IFF_OACTIVE;
2901
2902 /*
2903 * Make sure to set media properly. We have to do this
2904 * here since we have to issue commands in order to set
2905 * the link negotiation and we can't issue commands until
2906 * the firmware is running.
2907 */
2908 ifm = &sc->ifmedia;
2909 tmp = ifm->ifm_media;
2910 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2911 ti_ifmedia_upd(ifp);
2912 ifm->ifm_media = tmp;
2913}
2914
2915/*
2916 * Set media options.
2917 */
2918static int
2919ti_ifmedia_upd(ifp)
2920 struct ifnet *ifp;
2921{
2922 struct ti_softc *sc;
2923 struct ifmedia *ifm;
2924 struct ti_cmd_desc cmd;
2925 u_int32_t flowctl;
2926
2927 sc = ifp->if_softc;
2928 ifm = &sc->ifmedia;
2929
2930 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2931 return (EINVAL);
2932
2933 flowctl = 0;
2934
2935 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2936 case IFM_AUTO:
2937 /*
2938 * Transmit flow control doesn't work on the Tigon 1.
2939 */
2940 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2941
2942 /*
2943 * Transmit flow control can also cause problems on the
2944 * Tigon 2, apparantly with both the copper and fiber
2945 * boards. The symptom is that the interface will just
2946 * hang. This was reproduced with Alteon 180 switches.
2947 */
2948#if 0
2949 if (sc->ti_hwrev != TI_HWREV_TIGON)
2950 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2951#endif
2952
2953 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2954 TI_GLNK_FULL_DUPLEX| flowctl |
2955 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2956
2957 flowctl = TI_LNK_RX_FLOWCTL_Y;
2958#if 0
2959 if (sc->ti_hwrev != TI_HWREV_TIGON)
2960 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2961#endif
2962
2963 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2964 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
2965 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2966 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2967 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2968 break;
2969 case IFM_1000_SX:
2970 case IFM_1000_T:
2971 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2972#if 0
2973 if (sc->ti_hwrev != TI_HWREV_TIGON)
2974 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2975#endif
2976
2977 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2978 flowctl |TI_GLNK_ENB);
2979 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2980 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2981 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2982 }
2983 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2984 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2985 break;
2986 case IFM_100_FX:
2987 case IFM_10_FL:
2988 case IFM_100_TX:
2989 case IFM_10_T:
2990 flowctl = TI_LNK_RX_FLOWCTL_Y;
2991#if 0
2992 if (sc->ti_hwrev != TI_HWREV_TIGON)
2993 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2994#endif
2995
2996 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2997 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
2998 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2999 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3000 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3001 } else {
3002 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3003 }
3004 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3005 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3006 } else {
3007 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3008 }
3009 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3010 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3011 break;
3012 }
3013
3014 return (0);
3015}
3016
3017/*
3018 * Report current media status.
3019 */
3020static void
3021ti_ifmedia_sts(ifp, ifmr)
3022 struct ifnet *ifp;
3023 struct ifmediareq *ifmr;
3024{
3025 struct ti_softc *sc;
3026 u_int32_t media = 0;
3027
3028 sc = ifp->if_softc;
3029
3030 ifmr->ifm_status = IFM_AVALID;
3031 ifmr->ifm_active = IFM_ETHER;
3032
3033 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3034 return;
3035
3036 ifmr->ifm_status |= IFM_ACTIVE;
3037
3038 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3039 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3040 if (sc->ti_copper)
3041 ifmr->ifm_active |= IFM_1000_T;
3042 else
3043 ifmr->ifm_active |= IFM_1000_SX;
3044 if (media & TI_GLNK_FULL_DUPLEX)
3045 ifmr->ifm_active |= IFM_FDX;
3046 else
3047 ifmr->ifm_active |= IFM_HDX;
3048 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3049 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3050 if (sc->ti_copper) {
3051 if (media & TI_LNK_100MB)
3052 ifmr->ifm_active |= IFM_100_TX;
3053 if (media & TI_LNK_10MB)
3054 ifmr->ifm_active |= IFM_10_T;
3055 } else {
3056 if (media & TI_LNK_100MB)
3057 ifmr->ifm_active |= IFM_100_FX;
3058 if (media & TI_LNK_10MB)
3059 ifmr->ifm_active |= IFM_10_FL;
3060 }
3061 if (media & TI_LNK_FULL_DUPLEX)
3062 ifmr->ifm_active |= IFM_FDX;
3063 if (media & TI_LNK_HALF_DUPLEX)
3064 ifmr->ifm_active |= IFM_HDX;
3065 }
3066}
3067
3068static int
3069ti_ioctl(ifp, command, data)
3070 struct ifnet *ifp;
3071 u_long command;
3072 caddr_t data;
3073{
3074 struct ti_softc *sc = ifp->if_softc;
3075 struct ifreq *ifr = (struct ifreq *) data;
3076 int mask, error = 0;
3077 struct ti_cmd_desc cmd;
3078
3079 TI_LOCK(sc);
3080
3081 switch (command) {
3082 case SIOCSIFMTU:
3083 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3084 error = EINVAL;
3085 else {
3086 ifp->if_mtu = ifr->ifr_mtu;
3087 ti_init(sc);
3088 }
3089 break;
3090 case SIOCSIFFLAGS:
3091 if (ifp->if_flags & IFF_UP) {
3092 /*
3093 * If only the state of the PROMISC flag changed,
3094 * then just use the 'set promisc mode' command
3095 * instead of reinitializing the entire NIC. Doing
3096 * a full re-init means reloading the firmware and
3097 * waiting for it to start up, which may take a
3098 * second or two.
3099 */
3100 if (ifp->if_flags & IFF_RUNNING &&
3101 ifp->if_flags & IFF_PROMISC &&
3102 !(sc->ti_if_flags & IFF_PROMISC)) {
3103 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3104 TI_CMD_CODE_PROMISC_ENB, 0);
3105 } else if (ifp->if_flags & IFF_RUNNING &&
3106 !(ifp->if_flags & IFF_PROMISC) &&
3107 sc->ti_if_flags & IFF_PROMISC) {
3108 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3109 TI_CMD_CODE_PROMISC_DIS, 0);
3110 } else
3111 ti_init(sc);
3112 } else {
3113 if (ifp->if_flags & IFF_RUNNING) {
3114 ti_stop(sc);
3115 }
3116 }
3117 sc->ti_if_flags = ifp->if_flags;
3118 error = 0;
3119 break;
3120 case SIOCADDMULTI:
3121 case SIOCDELMULTI:
3122 if (ifp->if_flags & IFF_RUNNING) {
3123 ti_setmulti(sc);
3124 error = 0;
3125 }
3126 break;
3127 case SIOCSIFMEDIA:
3128 case SIOCGIFMEDIA:
3129 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3130 break;
3131 case SIOCSIFCAP:
3132 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3133 if (mask & IFCAP_HWCSUM) {
3134 if (IFCAP_HWCSUM & ifp->if_capenable)
3135 ifp->if_capenable &= ~IFCAP_HWCSUM;
3136 else
3137 ifp->if_capenable |= IFCAP_HWCSUM;
3138 if (ifp->if_flags & IFF_RUNNING)
3139 ti_init(sc);
3140 }
3141 error = 0;
3142 break;
3143 default:
3144 error = ether_ioctl(ifp, command, data);
3145 break;
3146 }
3147
3148 TI_UNLOCK(sc);
3149
3150 return (error);
3151}
3152
3153static int
3154ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3155{
3156 struct ti_softc *sc;
3157
3158 sc = dev->si_drv1;
3159 if (sc == NULL)
3160 return (ENODEV);
3161
3162 TI_LOCK(sc);
3163 sc->ti_flags |= TI_FLAG_DEBUGING;
3164 TI_UNLOCK(sc);
3165
3166 return (0);
3167}
3168
3169static int
3170ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3171{
3172 struct ti_softc *sc;
3173
3174 sc = dev->si_drv1;
3175 if (sc == NULL)
3176 return (ENODEV);
3177
3178 TI_LOCK(sc);
3179 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3180 TI_UNLOCK(sc);
3181
3182 return (0);
3183}
3184
3185/*
3186 * This ioctl routine goes along with the Tigon character device.
3187 */
3188static int
3189ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
3190{
3191 int error;
3192 struct ti_softc *sc;
3193
3194 sc = dev->si_drv1;
3195 if (sc == NULL)
3196 return (ENODEV);
3197
3198 error = 0;
3199
3200 switch (cmd) {
3201 case TIIOCGETSTATS:
3202 {
3203 struct ti_stats *outstats;
3204
3205 outstats = (struct ti_stats *)addr;
3206
3207 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3208 sizeof(struct ti_stats));
3209 break;
3210 }
3211 case TIIOCGETPARAMS:
3212 {
3213 struct ti_params *params;
3214
3215 params = (struct ti_params *)addr;
3216
3217 params->ti_stat_ticks = sc->ti_stat_ticks;
3218 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3219 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3220 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3221 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3222 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3223 params->param_mask = TI_PARAM_ALL;
3224
3225 error = 0;
3226
3227 break;
3228 }
3229 case TIIOCSETPARAMS:
3230 {
3231 struct ti_params *params;
3232
3233 params = (struct ti_params *)addr;
3234
3235 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3236 sc->ti_stat_ticks = params->ti_stat_ticks;
3237 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3238 }
3239
3240 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3241 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3242 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3243 sc->ti_rx_coal_ticks);
3244 }
3245
3246 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3247 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3248 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3249 sc->ti_tx_coal_ticks);
3250 }
3251
3252 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3253 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3254 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3255 sc->ti_rx_max_coal_bds);
3256 }
3257
3258 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3259 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3260 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3261 sc->ti_tx_max_coal_bds);
3262 }
3263
3264 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3265 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3266 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3267 sc->ti_tx_buf_ratio);
3268 }
3269
3270 error = 0;
3271
3272 break;
3273 }
3274 case TIIOCSETTRACE: {
3275 ti_trace_type trace_type;
3276
3277 trace_type = *(ti_trace_type *)addr;
3278
3279 /*
3280 * Set tracing to whatever the user asked for. Setting
3281 * this register to 0 should have the effect of disabling
3282 * tracing.
3283 */
3284 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3285
3286 error = 0;
3287
3288 break;
3289 }
3290 case TIIOCGETTRACE: {
3291 struct ti_trace_buf *trace_buf;
3292 u_int32_t trace_start, cur_trace_ptr, trace_len;
3293
3294 trace_buf = (struct ti_trace_buf *)addr;
3295
3296 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3297 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3298 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3299
3300#if 0
3301 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, "
3302 "trace_len = %d\n", sc->ti_unit, trace_start,
3303 cur_trace_ptr, trace_len);
3304 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit,
3305 trace_buf->buf_len);
3306#endif
3307
3308 error = ti_copy_mem(sc, trace_start, min(trace_len,
3309 trace_buf->buf_len),
3310 (caddr_t)trace_buf->buf, 1, 1);
3311
3312 if (error == 0) {
3313 trace_buf->fill_len = min(trace_len,
3314 trace_buf->buf_len);
3315 if (cur_trace_ptr < trace_start)
3316 trace_buf->cur_trace_ptr =
3317 trace_start - cur_trace_ptr;
3318 else
3319 trace_buf->cur_trace_ptr =
3320 cur_trace_ptr - trace_start;
3321 } else
3322 trace_buf->fill_len = 0;
3323
3324 break;
3325 }
3326
3327 /*
3328 * For debugging, five ioctls are needed:
3329 * ALT_ATTACH
3330 * ALT_READ_TG_REG
3331 * ALT_WRITE_TG_REG
3332 * ALT_READ_TG_MEM
3333 * ALT_WRITE_TG_MEM
3334 */
3335 case ALT_ATTACH:
3336 /*
3337 * From what I can tell, Alteon's Solaris Tigon driver
3338 * only has one character device, so you have to attach
3339 * to the Tigon board you're interested in. This seems
3340 * like a not-so-good way to do things, since unless you
3341 * subsequently specify the unit number of the device
3342 * you're interested in in every ioctl, you'll only be
3343 * able to debug one board at a time.
3344 */
3345 error = 0;
3346 break;
3347 case ALT_READ_TG_MEM:
3348 case ALT_WRITE_TG_MEM:
3349 {
3350 struct tg_mem *mem_param;
3351 u_int32_t sram_end, scratch_end;
3352
3353 mem_param = (struct tg_mem *)addr;
3354
3355 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3356 sram_end = TI_END_SRAM_I;
3357 scratch_end = TI_END_SCRATCH_I;
3358 } else {
3359 sram_end = TI_END_SRAM_II;
3360 scratch_end = TI_END_SCRATCH_II;
3361 }
3362
3363 /*
3364 * For now, we'll only handle accessing regular SRAM,
3365 * nothing else.
3366 */
3367 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3368 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3369 /*
3370 * In this instance, we always copy to/from user
3371 * space, so the user space argument is set to 1.
3372 */
3373 error = ti_copy_mem(sc, mem_param->tgAddr,
3374 mem_param->len,
3375 mem_param->userAddr, 1,
3376 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3377 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3378 && (mem_param->tgAddr <= scratch_end)) {
3379 error = ti_copy_scratch(sc, mem_param->tgAddr,
3380 mem_param->len,
3381 mem_param->userAddr, 1,
3382 (cmd == ALT_READ_TG_MEM) ?
3383 1 : 0, TI_PROCESSOR_A);
3384 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3385 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3386 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3387 printf("ti%d: invalid memory range for "
3388 "Tigon I\n", sc->ti_unit);
3389 error = EINVAL;
3390 break;
3391 }
3392 error = ti_copy_scratch(sc, mem_param->tgAddr -
3393 TI_SCRATCH_DEBUG_OFF,
3394 mem_param->len,
3395 mem_param->userAddr, 1,
3396 (cmd == ALT_READ_TG_MEM) ?
3397 1 : 0, TI_PROCESSOR_B);
3398 } else {
3399 printf("ti%d: memory address %#x len %d is out of "
3400 "supported range\n", sc->ti_unit,
3401 mem_param->tgAddr, mem_param->len);
3402 error = EINVAL;
3403 }
3404
3405 break;
3406 }
3407 case ALT_READ_TG_REG:
3408 case ALT_WRITE_TG_REG:
3409 {
3410 struct tg_reg *regs;
3411 u_int32_t tmpval;
3412
3413 regs = (struct tg_reg *)addr;
3414
3415 /*
3416 * Make sure the address in question isn't out of range.
3417 */
3418 if (regs->addr > TI_REG_MAX) {
3419 error = EINVAL;
3420 break;
3421 }
3422 if (cmd == ALT_READ_TG_REG) {
3423 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3424 regs->addr, &tmpval, 1);
3425 regs->data = ntohl(tmpval);
3426#if 0
3427 if ((regs->addr == TI_CPU_STATE)
3428 || (regs->addr == TI_CPU_CTL_B)) {
3429 printf("ti%d: register %#x = %#x\n",
3430 sc->ti_unit, regs->addr, tmpval);
3431 }
3432#endif
3433 } else {
3434 tmpval = htonl(regs->data);
3435 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3436 regs->addr, &tmpval, 1);
3437 }
3438
3439 break;
3440 }
3441 default:
3442 error = ENOTTY;
3443 break;
3444 }
3445 return (error);
3446}
3447
3448static void
3449ti_watchdog(ifp)
3450 struct ifnet *ifp;
3451{
3452 struct ti_softc *sc;
3453
3454 sc = ifp->if_softc;
3455 TI_LOCK(sc);
3456
3457 /*
3458 * When we're debugging, the chip is often stopped for long periods
3459 * of time, and that would normally cause the watchdog timer to fire.
3460 * Since that impedes debugging, we don't want to do that.
3461 */
3462 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3463 TI_UNLOCK(sc);
3464 return;
3465 }
3466
3467 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
3468 ti_stop(sc);
3469 ti_init(sc);
3470
3471 ifp->if_oerrors++;
3472 TI_UNLOCK(sc);
3473}
3474
3475/*
3476 * Stop the adapter and free any mbufs allocated to the
3477 * RX and TX lists.
3478 */
3479static void
3480ti_stop(sc)
3481 struct ti_softc *sc;
3482{
3483 struct ifnet *ifp;
3484 struct ti_cmd_desc cmd;
3485
3486 TI_LOCK(sc);
3487
3488 ifp = &sc->arpcom.ac_if;
3489
3490 /* Disable host interrupts. */
3491 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3492 /*
3493 * Tell firmware we're shutting down.
3494 */
3495 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3496
3497 /* Halt and reinitialize. */
3498 ti_chipinit(sc);
3499 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
3500 ti_chipinit(sc);
3501
3502 /* Free the RX lists. */
3503 ti_free_rx_ring_std(sc);
3504
3505 /* Free jumbo RX list. */
3506 ti_free_rx_ring_jumbo(sc);
3507
3508 /* Free mini RX list. */
3509 ti_free_rx_ring_mini(sc);
3510
3511 /* Free TX buffers. */
3512 ti_free_tx_ring(sc);
3513
3514 sc->ti_ev_prodidx.ti_idx = 0;
3515 sc->ti_return_prodidx.ti_idx = 0;
3516 sc->ti_tx_considx.ti_idx = 0;
3517 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3518
3519 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3520 TI_UNLOCK(sc);
3521}
3522
3523/*
3524 * Stop all chip I/O so that the kernel's probe routines don't
3525 * get confused by errant DMAs when rebooting.
3526 */
3527static void
3528ti_shutdown(dev)
3529 device_t dev;
3530{
3531 struct ti_softc *sc;
3532
3533 sc = device_get_softc(dev);
3534 TI_LOCK(sc);
3535 ti_chipinit(sc);
3536 TI_UNLOCK(sc);
3537}
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