1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * ifdtool - Manage Intel Firmware Descriptor information 4 * 5 * Copyright (C) 2011 The ChromiumOS Authors. 6 * 7 * From Coreboot project 8 */ 9 10#include <stdint.h> 11 12#define __packed __attribute__((packed)) 13 14#define IFDTOOL_VERSION "1.1-U-Boot" 15 16#define WRITE_MAX 16 17 18enum spi_frequency { 19 SPI_FREQUENCY_20MHZ = 0, 20 SPI_FREQUENCY_33MHZ = 1, 21 SPI_FREQUENCY_50MHZ = 4, 22}; 23 24enum component_density { 25 COMPONENT_DENSITY_512KB = 0, 26 COMPONENT_DENSITY_1MB = 1, 27 COMPONENT_DENSITY_2MB = 2, 28 COMPONENT_DENSITY_4MB = 3, 29 COMPONENT_DENSITY_8MB = 4, 30 COMPONENT_DENSITY_16MB = 5, 31}; 32 33/* flash descriptor */ 34struct __packed fdbar_t { 35 uint32_t flvalsig; 36 uint32_t flmap0; 37 uint32_t flmap1; 38 uint32_t flmap2; 39 uint8_t reserved[0xefc - 0x20]; 40 uint32_t flumap1; 41}; 42 43#define MAX_REGIONS 5 44 45/* regions */ 46struct __packed frba_t { 47 uint32_t flreg[MAX_REGIONS]; 48}; 49 50/* component section */ 51struct __packed fcba_t { 52 uint32_t flcomp; 53 uint32_t flill; 54 uint32_t flpb; 55}; 56 57#define MAX_STRAPS 18 58 59/* pch strap */ 60struct __packed fpsba_t { 61 uint32_t pchstrp[MAX_STRAPS]; 62}; 63 64/* master */ 65struct __packed fmba_t { 66 uint32_t flmstr1; 67 uint32_t flmstr2; 68 uint32_t flmstr3; 69}; 70 71/* processor strap */ 72struct __packed fmsba_t { 73 uint32_t data[8]; 74}; 75 76/* ME VSCC */ 77struct vscc_t { 78 uint32_t jid; 79 uint32_t vscc; 80}; 81 82struct vtba_t { 83 /* Actual number of entries specified in vtl */ 84 struct vscc_t entry[8]; 85}; 86 87struct region_t { 88 int base, limit, size; 89}; 90