1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware driver
4 *
5 * Copyright (C) 2018-2019 Xilinx, Inc.
6 */
7
8#ifndef _ZYNQMP_FIRMWARE_H_
9#define _ZYNQMP_FIRMWARE_H_
10
11enum pm_api_id {
12	PM_GET_API_VERSION = 1,
13	PM_SET_CONFIGURATION = 2,
14	PM_GET_NODE_STATUS = 3,
15	PM_GET_OPERATING_CHARACTERISTIC = 4,
16	PM_REGISTER_NOTIFIER = 5,
17	/* API for suspending */
18	PM_REQUEST_SUSPEND = 6,
19	PM_SELF_SUSPEND = 7,
20	PM_FORCE_POWERDOWN = 8,
21	PM_ABORT_SUSPEND = 9,
22	PM_REQUEST_WAKEUP = 10,
23	PM_SET_WAKEUP_SOURCE = 11,
24	PM_SYSTEM_SHUTDOWN = 12,
25	PM_REQUEST_NODE = 13,
26	PM_RELEASE_NODE = 14,
27	PM_SET_REQUIREMENT = 15,
28	PM_SET_MAX_LATENCY = 16,
29	/* Direct control API functions: */
30	PM_RESET_ASSERT = 17,
31	PM_RESET_GET_STATUS = 18,
32	PM_MMIO_WRITE = 19,
33	PM_MMIO_READ = 20,
34	PM_PM_INIT_FINALIZE = 21,
35	PM_FPGA_LOAD = 22,
36	PM_FPGA_GET_STATUS = 23,
37	PM_GET_CHIPID = 24,
38	/* ID 25 is been used by U-Boot to process secure boot images */
39	/* Secure library generic API functions */
40	PM_SECURE_SHA = 26,
41	PM_SECURE_RSA = 27,
42	PM_PINCTRL_REQUEST = 28,
43	PM_PINCTRL_RELEASE = 29,
44	PM_PINCTRL_GET_FUNCTION = 30,
45	PM_PINCTRL_SET_FUNCTION = 31,
46	PM_PINCTRL_CONFIG_PARAM_GET = 32,
47	PM_PINCTRL_CONFIG_PARAM_SET = 33,
48	PM_IOCTL = 34,
49	PM_QUERY_DATA = 35,
50	PM_CLOCK_ENABLE = 36,
51	PM_CLOCK_DISABLE = 37,
52	PM_CLOCK_GETSTATE = 38,
53	PM_CLOCK_SETDIVIDER = 39,
54	PM_CLOCK_GETDIVIDER = 40,
55	PM_CLOCK_SETRATE = 41,
56	PM_CLOCK_GETRATE = 42,
57	PM_CLOCK_SETPARENT = 43,
58	PM_CLOCK_GETPARENT = 44,
59	PM_SECURE_IMAGE = 45,
60	PM_FPGA_READ = 46,
61	PM_SECURE_AES = 47,
62	PM_CLOCK_PLL_GETPARAM = 49,
63	/* PM_REGISTER_ACCESS API */
64	PM_REGISTER_ACCESS = 52,
65	PM_EFUSE_ACCESS = 53,
66	PM_FEATURE_CHECK = 63,
67	PM_API_MAX,
68};
69
70enum pm_node_id {
71	NODE_UNKNOWN = 0,
72	NODE_APU = 1,
73	NODE_APU_0 = 2,
74	NODE_APU_1 = 3,
75	NODE_APU_2 = 4,
76	NODE_APU_3 = 5,
77	NODE_RPU = 6,
78	NODE_RPU_0 = 7,
79	NODE_RPU_1 = 8,
80	NODE_PLD = 9,
81	NODE_FPD = 10,
82	NODE_OCM_BANK_0 = 11,
83	NODE_OCM_BANK_1 = 12,
84	NODE_OCM_BANK_2 = 13,
85	NODE_OCM_BANK_3 = 14,
86	NODE_TCM_0_A = 15,
87	NODE_TCM_0_B = 16,
88	NODE_TCM_1_A = 17,
89	NODE_TCM_1_B = 18,
90	NODE_L2 = 19,
91	NODE_GPU_PP_0 = 20,
92	NODE_GPU_PP_1 = 21,
93	NODE_USB_0 = 22,
94	NODE_USB_1 = 23,
95	NODE_TTC_0 = 24,
96	NODE_TTC_1 = 25,
97	NODE_TTC_2 = 26,
98	NODE_TTC_3 = 27,
99	NODE_SATA = 28,
100	NODE_ETH_0 = 29,
101	NODE_ETH_1 = 30,
102	NODE_ETH_2 = 31,
103	NODE_ETH_3 = 32,
104	NODE_UART_0 = 33,
105	NODE_UART_1 = 34,
106	NODE_SPI_0 = 35,
107	NODE_SPI_1 = 36,
108	NODE_I2C_0 = 37,
109	NODE_I2C_1 = 38,
110	NODE_SD_0 = 39,
111	NODE_SD_1 = 40,
112	NODE_DP = 41,
113	NODE_GDMA = 42,
114	NODE_ADMA = 43,
115	NODE_NAND = 44,
116	NODE_QSPI = 45,
117	NODE_GPIO = 46,
118	NODE_CAN_0 = 47,
119	NODE_CAN_1 = 48,
120	NODE_EXTERN = 49,
121	NODE_APLL = 50,
122	NODE_VPLL = 51,
123	NODE_DPLL = 52,
124	NODE_RPLL = 53,
125	NODE_IOPLL = 54,
126	NODE_DDR = 55,
127	NODE_IPI_APU = 56,
128	NODE_IPI_RPU_0 = 57,
129	NODE_GPU = 58,
130	NODE_PCIE = 59,
131	NODE_PCAP = 60,
132	NODE_RTC = 61,
133	NODE_LPD = 62,
134	NODE_VCU = 63,
135	NODE_IPI_RPU_1 = 64,
136	NODE_IPI_PL_0 = 65,
137	NODE_IPI_PL_1 = 66,
138	NODE_IPI_PL_2 = 67,
139	NODE_IPI_PL_3 = 68,
140	NODE_PL = 69,
141	NODE_GEM_TSU = 70,
142	NODE_SWDT_0 = 71,
143	NODE_SWDT_1 = 72,
144	NODE_CSU = 73,
145	NODE_PJTAG = 74,
146	NODE_TRACE = 75,
147	NODE_TESTSCAN = 76,
148	NODE_PMU = 77,
149	NODE_MAX = 78,
150};
151
152enum tap_delay_type {
153	PM_TAPDELAY_INPUT = 0,
154	PM_TAPDELAY_OUTPUT = 1,
155};
156
157enum dll_reset_type {
158	PM_DLL_RESET_ASSERT = 0,
159	PM_DLL_RESET_RELEASE = 1,
160	PM_DLL_RESET_PULSE = 2,
161};
162
163enum ospi_mux_select_type {
164	PM_OSPI_MUX_SEL_DMA,
165	PM_OSPI_MUX_SEL_LINEAR,
166	PM_OSPI_MUX_GET_MODE,
167};
168
169enum pm_query_id {
170	PM_QID_INVALID = 0,
171	PM_QID_CLOCK_GET_NAME = 1,
172	PM_QID_CLOCK_GET_TOPOLOGY = 2,
173	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
174	PM_QID_CLOCK_GET_PARENTS = 4,
175	PM_QID_CLOCK_GET_ATTRIBUTES = 5,
176	PM_QID_PINCTRL_GET_NUM_PINS = 6,
177	PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
178	PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
179	PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
180	PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
181	PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
182	PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
183	PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
184};
185
186enum pm_pinctrl_config_param {
187	PM_PINCTRL_CONFIG_SLEW_RATE = 0,
188	PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
189	PM_PINCTRL_CONFIG_PULL_CTRL = 2,
190	PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
191	PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
192	PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
193	PM_PINCTRL_CONFIG_TRI_STATE = 6,
194	PM_PINCTRL_CONFIG_MAX = 7,
195};
196
197enum pm_pinctrl_slew_rate {
198	PM_PINCTRL_SLEW_RATE_FAST = 0,
199	PM_PINCTRL_SLEW_RATE_SLOW = 1,
200};
201
202enum pm_pinctrl_bias_status {
203	PM_PINCTRL_BIAS_DISABLE = 0,
204	PM_PINCTRL_BIAS_ENABLE = 1,
205};
206
207enum pm_pinctrl_pull_ctrl {
208	PM_PINCTRL_BIAS_PULL_DOWN = 0,
209	PM_PINCTRL_BIAS_PULL_UP = 1,
210};
211
212enum pm_pinctrl_schmitt_cmos {
213	PM_PINCTRL_INPUT_TYPE_CMOS = 0,
214	PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
215};
216
217enum pm_pinctrl_drive_strength {
218	PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
219	PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
220	PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
221	PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
222};
223
224enum pm_pinctrl_tri_state {
225	PM_PINCTRL_TRI_STATE_DISABLE = 0,
226	PM_PINCTRL_TRI_STATE_ENABLE = 1,
227};
228
229enum zynqmp_pm_reset_action {
230	PM_RESET_ACTION_RELEASE = 0,
231	PM_RESET_ACTION_ASSERT = 1,
232	PM_RESET_ACTION_PULSE = 2,
233};
234
235enum zynqmp_pm_reset {
236	ZYNQMP_PM_RESET_START = 1000,
237	ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
238	ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
239	ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
240	ZYNQMP_PM_RESET_DP = 1003,
241	ZYNQMP_PM_RESET_SWDT_CRF = 1004,
242	ZYNQMP_PM_RESET_AFI_FM5 = 1005,
243	ZYNQMP_PM_RESET_AFI_FM4 = 1006,
244	ZYNQMP_PM_RESET_AFI_FM3 = 1007,
245	ZYNQMP_PM_RESET_AFI_FM2 = 1008,
246	ZYNQMP_PM_RESET_AFI_FM1 = 1009,
247	ZYNQMP_PM_RESET_AFI_FM0 = 1010,
248	ZYNQMP_PM_RESET_GDMA = 1011,
249	ZYNQMP_PM_RESET_GPU_PP1 = 1012,
250	ZYNQMP_PM_RESET_GPU_PP0 = 1013,
251	ZYNQMP_PM_RESET_GPU = 1014,
252	ZYNQMP_PM_RESET_GT = 1015,
253	ZYNQMP_PM_RESET_SATA = 1016,
254	ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
255	ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
256	ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
257	ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
258	ZYNQMP_PM_RESET_APU_L2 = 1021,
259	ZYNQMP_PM_RESET_ACPU3 = 1022,
260	ZYNQMP_PM_RESET_ACPU2 = 1023,
261	ZYNQMP_PM_RESET_ACPU1 = 1024,
262	ZYNQMP_PM_RESET_ACPU0 = 1025,
263	ZYNQMP_PM_RESET_DDR = 1026,
264	ZYNQMP_PM_RESET_APM_FPD = 1027,
265	ZYNQMP_PM_RESET_SOFT = 1028,
266	ZYNQMP_PM_RESET_GEM0 = 1029,
267	ZYNQMP_PM_RESET_GEM1 = 1030,
268	ZYNQMP_PM_RESET_GEM2 = 1031,
269	ZYNQMP_PM_RESET_GEM3 = 1032,
270	ZYNQMP_PM_RESET_QSPI = 1033,
271	ZYNQMP_PM_RESET_UART0 = 1034,
272	ZYNQMP_PM_RESET_UART1 = 1035,
273	ZYNQMP_PM_RESET_SPI0 = 1036,
274	ZYNQMP_PM_RESET_SPI1 = 1037,
275	ZYNQMP_PM_RESET_SDIO0 = 1038,
276	ZYNQMP_PM_RESET_SDIO1 = 1039,
277	ZYNQMP_PM_RESET_CAN0 = 1040,
278	ZYNQMP_PM_RESET_CAN1 = 1041,
279	ZYNQMP_PM_RESET_I2C0 = 1042,
280	ZYNQMP_PM_RESET_I2C1 = 1043,
281	ZYNQMP_PM_RESET_TTC0 = 1044,
282	ZYNQMP_PM_RESET_TTC1 = 1045,
283	ZYNQMP_PM_RESET_TTC2 = 1046,
284	ZYNQMP_PM_RESET_TTC3 = 1047,
285	ZYNQMP_PM_RESET_SWDT_CRL = 1048,
286	ZYNQMP_PM_RESET_NAND = 1049,
287	ZYNQMP_PM_RESET_ADMA = 1050,
288	ZYNQMP_PM_RESET_GPIO = 1051,
289	ZYNQMP_PM_RESET_IOU_CC = 1052,
290	ZYNQMP_PM_RESET_TIMESTAMP = 1053,
291	ZYNQMP_PM_RESET_RPU_R50 = 1054,
292	ZYNQMP_PM_RESET_RPU_R51 = 1055,
293	ZYNQMP_PM_RESET_RPU_AMBA = 1056,
294	ZYNQMP_PM_RESET_OCM = 1057,
295	ZYNQMP_PM_RESET_RPU_PGE = 1058,
296	ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
297	ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
298	ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
299	ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
300	ZYNQMP_PM_RESET_USB0_APB = 1063,
301	ZYNQMP_PM_RESET_USB1_APB = 1064,
302	ZYNQMP_PM_RESET_IPI = 1065,
303	ZYNQMP_PM_RESET_APM_LPD = 1066,
304	ZYNQMP_PM_RESET_RTC = 1067,
305	ZYNQMP_PM_RESET_SYSMON = 1068,
306	ZYNQMP_PM_RESET_AFI_FM6 = 1069,
307	ZYNQMP_PM_RESET_LPD_SWDT = 1070,
308	ZYNQMP_PM_RESET_FPD = 1071,
309	ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
310	ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
311	ZYNQMP_PM_RESET_DBG_LPD = 1074,
312	ZYNQMP_PM_RESET_DBG_FPD = 1075,
313	ZYNQMP_PM_RESET_APLL = 1076,
314	ZYNQMP_PM_RESET_DPLL = 1077,
315	ZYNQMP_PM_RESET_VPLL = 1078,
316	ZYNQMP_PM_RESET_IOPLL = 1079,
317	ZYNQMP_PM_RESET_RPLL = 1080,
318	ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
319	ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
320	ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
321	ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
322	ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
323	ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
324	ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
325	ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
326	ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
327	ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
328	ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
329	ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
330	ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
331	ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
332	ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
333	ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
334	ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
335	ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
336	ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
337	ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
338	ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
339	ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
340	ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
341	ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
342	ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
343	ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
344	ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
345	ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
346	ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
347	ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
348	ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
349	ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
350	ZYNQMP_PM_RESET_RPU_LS = 1113,
351	ZYNQMP_PM_RESET_PS_ONLY = 1114,
352	ZYNQMP_PM_RESET_PL = 1115,
353	ZYNQMP_PM_RESET_PS_PL0 = 1116,
354	ZYNQMP_PM_RESET_PS_PL1 = 1117,
355	ZYNQMP_PM_RESET_PS_PL2 = 1118,
356	ZYNQMP_PM_RESET_PS_PL3 = 1119,
357	ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
358};
359
360enum pm_ioctl_id {
361	IOCTL_GET_RPU_OPER_MODE = 0,
362	IOCTL_SET_RPU_OPER_MODE = 1,
363	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
364	IOCTL_TCM_COMB_CONFIG = 3,
365	IOCTL_SET_TAPDELAY_BYPASS = 4,
366	IOCTL_SET_SGMII_MODE = 5,
367	IOCTL_SD_DLL_RESET = 6,
368	IOCTL_SET_SD_TAPDELAY = 7,
369	IOCTL_SET_PLL_FRAC_MODE = 8,
370	IOCTL_GET_PLL_FRAC_MODE = 9,
371	IOCTL_SET_PLL_FRAC_DATA = 10,
372	IOCTL_GET_PLL_FRAC_DATA = 11,
373	IOCTL_WRITE_GGS = 12,
374	IOCTL_READ_GGS = 13,
375	IOCTL_WRITE_PGGS = 14,
376	IOCTL_READ_PGGS = 15,
377	/* IOCTL for ULPI reset */
378	IOCTL_ULPI_RESET = 16,
379	/* Set healthy bit value*/
380	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
381	IOCTL_AFI = 18,
382	/* Probe counter read/write */
383	IOCTL_PROBE_COUNTER_READ = 19,
384	IOCTL_PROBE_COUNTER_WRITE = 20,
385	IOCTL_OSPI_MUX_SELECT = 21,
386	/* IOCTL for USB power request */
387	IOCTL_USB_SET_STATE = 22,
388	/* IOCTL to get last reset reason */
389	IOCTL_GET_LAST_RESET_REASON = 23,
390	/* AIE ISR Clear */
391	IOCTL_AIE_ISR_CLEAR = 24,
392	/* Register SGI to ATF */
393	IOCTL_REGISTER_SGI = 25,
394	/* Runtime feature configuration */
395	IOCTL_SET_FEATURE_CONFIG = 26,
396	IOCTL_GET_FEATURE_CONFIG = 27,
397	/* IOCTL for Secure Read/Write Interface */
398	IOCTL_READ_REG = 28,
399	IOCTL_MASK_WRITE_REG = 29,
400	/* Dynamic SD/GEM/USB configuration */
401	IOCTL_SET_SD_CONFIG = 30,
402	IOCTL_SET_GEM_CONFIG = 31,
403	IOCTL_SET_USB_CONFIG = 32,
404	/* AIE/AIEML Operations */
405	IOCTL_AIE_OPS = 33,
406	/* IOCTL to get default/current QoS */
407	IOCTL_GET_QOS = 34,
408};
409
410enum pm_sd_config_type {
411	SD_CONFIG_EMMC_SEL = 1,	/* To set SD_EMMC_SEL in CTRL_REG_SD */
412	SD_CONFIG_BASECLK = 2,	/* To set SD_BASECLK in SD_CONFIG_REG1 */
413	SD_CONFIG_8BIT = 3,	/* To set SD_8BIT in SD_CONFIG_REG2 */
414	SD_CONFIG_FIXED = 4,	/* To set fixed config registers */
415};
416
417enum pm_gem_config_type {
418	GEM_CONFIG_SGMII_MODE = 1, /* To set GEM_SGMII_MODE in GEM_CLK_CTRL */
419	GEM_CONFIG_FIXED = 2,   /* To set fixed config registers */
420};
421
422#define PM_SIP_SVC	0xc2000000
423
424#define ZYNQMP_PM_VERSION_MAJOR		1
425#define ZYNQMP_PM_VERSION_MINOR		0
426#define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
427#define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
428
429#define ZYNQMP_PM_VERSION       \
430	((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
431	 ZYNQMP_PM_VERSION_MINOR)
432
433#define ZYNQMP_PM_VERSION_INVALID	~0
434
435#define PMUFW_V1_0	((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
436#define PMIO_NODE_ID_BASE		0x1410801B
437
438/*
439 * Return payload size
440 * Not every firmware call expects the same amount of return bytes, however the
441 * firmware driver always copies 5 bytes from RX buffer to the ret_payload
442 * buffer. Therefore allocating with this defined value is recommended to avoid
443 * overflows.
444 */
445#define PAYLOAD_ARG_CNT	5U
446
447unsigned int zynqmp_firmware_version(void);
448int zynqmp_pmufw_node(u32 id);
449int zynqmp_pmufw_config_close(void);
450int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
451int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
452		      u32 arg3, u32 *ret_payload);
453int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
454int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
455			     u32 value);
456int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
457int zynqmp_mmio_read(const u32 address, u32 *value);
458int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
459int zynqmp_pm_feature(const u32 api_id);
460
461/* Type of Config Object */
462#define PM_CONFIG_OBJECT_TYPE_BASE	0x1U
463#define PM_CONFIG_OBJECT_TYPE_OVERLAY	0x2U
464
465/* Section Id */
466#define PM_CONFIG_SLAVE_SECTION_ID	0x102U
467#define PM_CONFIG_SET_CONFIG_SECTION_ID	0x107U
468
469/* Flag Option */
470#define PM_SLAVE_FLAG_IS_SHAREABLE	0x1U
471#define PM_MASTER_USING_SLAVE_MASK	0x2U
472
473/* IPI Mask for Master */
474#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK	0x00000001
475#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK	0x00000100
476#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK	0x00000200
477
478enum zynqmp_pm_request_ack {
479	ZYNQMP_PM_REQUEST_ACK_NO = 1,
480	ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
481	ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
482};
483
484/* Node capabilities */
485#define ZYNQMP_PM_CAPABILITY_ACCESS	0x1U
486#define ZYNQMP_PM_CAPABILITY_CONTEXT	0x2U
487#define ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
488#define ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
489
490#define ZYNQMP_PM_MAX_QOS		100U
491/* Firmware feature check version mask */
492#define FIRMWARE_VERSION_MASK		GENMASK(15, 0)
493/* PM API versions */
494#define PM_API_VERSION_2		2
495
496#define PM_PINCTRL_PARAM_SET_VERSION	2
497
498struct zynqmp_ipi_msg {
499	size_t len;
500	u32 *buf;
501};
502
503#endif /* _ZYNQMP_FIRMWARE_H_ */
504