1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  tsec.h
4 *
5 *  Driver for the Motorola Triple Speed Ethernet Controller
6 *
7 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003, Motorola, Inc.
9 * maintained by Xianghua Xiao (x.xiao@motorola.com)
10 * author Andy Fleming
11 */
12
13#ifndef __TSEC_H
14#define __TSEC_H
15
16#include <net.h>
17#include <config.h>
18#include <phy.h>
19
20#define TSEC_MDIO_REGS_OFFSET	0x520
21
22#define MAC_ADDR_LEN		6
23
24/* #define TSEC_TIMEOUT	1000000 */
25#define TSEC_TIMEOUT		1000
26#define TOUT_LOOP		1000000
27
28/* TBI register addresses */
29#define TBI_CR			0x00
30#define TBI_SR			0x01
31#define TBI_ANA			0x04
32#define TBI_ANLPBPA		0x05
33#define TBI_ANEX		0x06
34#define TBI_TBICON		0x11
35
36/* TBI MDIO register bit fields*/
37#define TBICON_CLK_SELECT	0x0020
38#define TBIANA_ASYMMETRIC_PAUSE	0x0100
39#define TBIANA_SYMMETRIC_PAUSE	0x0080
40#define TBIANA_HALF_DUPLEX	0x0040
41#define TBIANA_FULL_DUPLEX	0x0020
42#define TBICR_PHY_RESET		0x8000
43#define TBICR_ANEG_ENABLE	0x1000
44#define TBICR_RESTART_ANEG	0x0200
45#define TBICR_FULL_DUPLEX	0x0100
46#define TBICR_SPEED1_SET	0x0040
47
48/* MAC register bits */
49#define MACCFG1_SOFT_RESET	0x80000000
50#define MACCFG1_RESET_RX_MC	0x00080000
51#define MACCFG1_RESET_TX_MC	0x00040000
52#define MACCFG1_RESET_RX_FUN	0x00020000
53#define MACCFG1_RESET_TX_FUN	0x00010000
54#define MACCFG1_LOOPBACK	0x00000100
55#define MACCFG1_RX_FLOW		0x00000020
56#define MACCFG1_TX_FLOW		0x00000010
57#define MACCFG1_SYNCD_RX_EN	0x00000008
58#define MACCFG1_RX_EN		0x00000004
59#define MACCFG1_SYNCD_TX_EN	0x00000002
60#define MACCFG1_TX_EN		0x00000001
61
62#define MACCFG2_INIT_SETTINGS	0x00007205
63#define MACCFG2_FULL_DUPLEX	0x00000001
64#define MACCFG2_IF		0x00000300
65#define MACCFG2_GMII		0x00000200
66#define MACCFG2_MII		0x00000100
67
68#define ECNTRL_INIT_SETTINGS	0x00001000
69#define ECNTRL_TBI_MODE		0x00000020
70#define ECNTRL_REDUCED_MODE	0x00000010
71#define ECNTRL_R100		0x00000008
72#define ECNTRL_REDUCED_MII_MODE	0x00000004
73#define ECNTRL_SGMII_MODE	0x00000002
74
75#define RCTRL_PROM		0x00000008
76
77#ifndef CFG_SYS_TBIPA_VALUE
78# define CFG_SYS_TBIPA_VALUE	0x1f
79#endif
80
81#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
82
83#define MINFLR_INIT_SETTINGS	0x00000040
84
85#define DMACTRL_INIT_SETTINGS	0x000000c3
86#define DMACTRL_GRS		0x00000010
87#define DMACTRL_GTS		0x00000008
88#define DMACTRL_LE		0x00008000
89
90#define TSTAT_CLEAR_THALT	0x80000000
91#define RSTAT_CLEAR_RHALT	0x00800000
92
93#define IEVENT_INIT_CLEAR	0xffffffff
94#define IEVENT_BABR		0x80000000
95#define IEVENT_RXC		0x40000000
96#define IEVENT_BSY		0x20000000
97#define IEVENT_EBERR		0x10000000
98#define IEVENT_MSRO		0x04000000
99#define IEVENT_GTSC		0x02000000
100#define IEVENT_BABT		0x01000000
101#define IEVENT_TXC		0x00800000
102#define IEVENT_TXE		0x00400000
103#define IEVENT_TXB		0x00200000
104#define IEVENT_TXF		0x00100000
105#define IEVENT_IE		0x00080000
106#define IEVENT_LC		0x00040000
107#define IEVENT_CRL		0x00020000
108#define IEVENT_XFUN		0x00010000
109#define IEVENT_RXB0		0x00008000
110#define IEVENT_GRSC		0x00000100
111#define IEVENT_RXF0		0x00000080
112
113#define IMASK_INIT_CLEAR	0x00000000
114#define IMASK_TXEEN		0x00400000
115#define IMASK_TXBEN		0x00200000
116#define IMASK_TXFEN		0x00100000
117#define IMASK_RXFEN0		0x00000080
118
119/* Default Attribute fields */
120#define ATTR_INIT_SETTINGS	0x000000c0
121#define ATTRELI_INIT_SETTINGS	0x00000000
122
123/* TxBD status field bits */
124#define TXBD_READY		0x8000
125#define TXBD_PADCRC		0x4000
126#define TXBD_WRAP		0x2000
127#define TXBD_INTERRUPT		0x1000
128#define TXBD_LAST		0x0800
129#define TXBD_CRC		0x0400
130#define TXBD_DEF		0x0200
131#define TXBD_HUGEFRAME		0x0080
132#define TXBD_LATECOLLISION	0x0080
133#define TXBD_RETRYLIMIT		0x0040
134#define TXBD_RETRYCOUNTMASK	0x003c
135#define TXBD_UNDERRUN		0x0002
136#define TXBD_STATS		0x03ff
137
138/* RxBD status field bits */
139#define RXBD_EMPTY		0x8000
140#define RXBD_RO1		0x4000
141#define RXBD_WRAP		0x2000
142#define RXBD_INTERRUPT		0x1000
143#define RXBD_LAST		0x0800
144#define RXBD_FIRST		0x0400
145#define RXBD_MISS		0x0100
146#define RXBD_BROADCAST		0x0080
147#define RXBD_MULTICAST		0x0040
148#define RXBD_LARGE		0x0020
149#define RXBD_NONOCTET		0x0010
150#define RXBD_SHORT		0x0008
151#define RXBD_CRCERR		0x0004
152#define RXBD_OVERRUN		0x0002
153#define RXBD_TRUNCATED		0x0001
154#define RXBD_STATS		0x003f
155
156struct txbd8 {
157	uint16_t status;	/* Status Fields */
158	uint16_t length;	/* Buffer length */
159	uint32_t bufptr;	/* Buffer Pointer */
160};
161
162struct rxbd8 {
163	uint16_t status;	/* Status Fields */
164	uint16_t length;	/* Buffer Length */
165	uint32_t bufptr;	/* Buffer Pointer */
166};
167
168struct tsec_rmon_mib {
169	/* Transmit and Receive Counters */
170	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
171	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
172	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
173	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
174	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
175	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
176	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
177	/* Receive Counters */
178	u32	rbyt;		/* Receive Byte Counter */
179	u32	rpkt;		/* Receive Packet Counter */
180	u32	rfcs;		/* Receive FCS Error Counter */
181	u32	rmca;		/* Receive Multicast Packet (Counter) */
182	u32	rbca;		/* Receive Broadcast Packet */
183	u32	rxcf;		/* Receive Control Frame Packet */
184	u32	rxpf;		/* Receive Pause Frame Packet */
185	u32	rxuo;		/* Receive Unknown OP Code */
186	u32	raln;		/* Receive Alignment Error */
187	u32	rflr;		/* Receive Frame Length Error */
188	u32	rcde;		/* Receive Code Error */
189	u32	rcse;		/* Receive Carrier Sense Error */
190	u32	rund;		/* Receive Undersize Packet */
191	u32	rovr;		/* Receive Oversize Packet */
192	u32	rfrg;		/* Receive Fragments */
193	u32	rjbr;		/* Receive Jabber */
194	u32	rdrp;		/* Receive Drop */
195	/* Transmit Counters */
196	u32	tbyt;		/* Transmit Byte Counter */
197	u32	tpkt;		/* Transmit Packet */
198	u32	tmca;		/* Transmit Multicast Packet */
199	u32	tbca;		/* Transmit Broadcast Packet */
200	u32	txpf;		/* Transmit Pause Control Frame */
201	u32	tdfr;		/* Transmit Deferral Packet */
202	u32	tedf;		/* Transmit Excessive Deferral Packet */
203	u32	tscl;		/* Transmit Single Collision Packet */
204	/* (0x2_n700) */
205	u32	tmcl;		/* Transmit Multiple Collision Packet */
206	u32	tlcl;		/* Transmit Late Collision Packet */
207	u32	txcl;		/* Transmit Excessive Collision Packet */
208	u32	tncl;		/* Transmit Total Collision */
209
210	u32	res2;
211
212	u32	tdrp;		/* Transmit Drop Frame */
213	u32	tjbr;		/* Transmit Jabber Frame */
214	u32	tfcs;		/* Transmit FCS Error */
215	u32	txcf;		/* Transmit Control Frame */
216	u32	tovr;		/* Transmit Oversize Frame */
217	u32	tund;		/* Transmit Undersize Frame */
218	u32	tfrg;		/* Transmit Fragments Frame */
219	/* General Registers */
220	u32	car1;		/* Carry Register One */
221	u32	car2;		/* Carry Register Two */
222	u32	cam1;		/* Carry Register One Mask */
223	u32	cam2;		/* Carry Register Two Mask */
224};
225
226struct tsec_hash_regs {
227	u32	iaddr0;		/* Individual Address Register 0 */
228	u32	iaddr1;		/* Individual Address Register 1 */
229	u32	iaddr2;		/* Individual Address Register 2 */
230	u32	iaddr3;		/* Individual Address Register 3 */
231	u32	iaddr4;		/* Individual Address Register 4 */
232	u32	iaddr5;		/* Individual Address Register 5 */
233	u32	iaddr6;		/* Individual Address Register 6 */
234	u32	iaddr7;		/* Individual Address Register 7 */
235	u32	res1[24];
236	u32	gaddr0;		/* Group Address Register 0 */
237	u32	gaddr1;		/* Group Address Register 1 */
238	u32	gaddr2;		/* Group Address Register 2 */
239	u32	gaddr3;		/* Group Address Register 3 */
240	u32	gaddr4;		/* Group Address Register 4 */
241	u32	gaddr5;		/* Group Address Register 5 */
242	u32	gaddr6;		/* Group Address Register 6 */
243	u32	gaddr7;		/* Group Address Register 7 */
244	u32	res2[24];
245};
246
247struct tsec {
248	/* General Control and Status Registers (0x2_n000) */
249	u32	res000[4];
250
251	u32	ievent;		/* Interrupt Event */
252	u32	imask;		/* Interrupt Mask */
253	u32	edis;		/* Error Disabled */
254	u32	res01c;
255	u32	ecntrl;		/* Ethernet Control */
256	u32	minflr;		/* Minimum Frame Length */
257	u32	ptv;		/* Pause Time Value */
258	u32	dmactrl;	/* DMA Control */
259	u32	tbipa;		/* TBI PHY Address */
260
261	u32	res034[3];
262	u32	res040[48];
263
264	/* Transmit Control and Status Registers (0x2_n100) */
265	u32	tctrl;		/* Transmit Control */
266	u32	tstat;		/* Transmit Status */
267	u32	res108;
268	u32	tbdlen;		/* Tx BD Data Length */
269	u32	res110[5];
270	u32	ctbptr;		/* Current TxBD Pointer */
271	u32	res128[23];
272	u32	tbptr;		/* TxBD Pointer */
273	u32	res188[30];
274	/* (0x2_n200) */
275	u32	res200;
276	u32	tbase;		/* TxBD Base Address */
277	u32	res208[42];
278	u32	ostbd;		/* Out of Sequence TxBD */
279	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
280	u32	res2b8[18];
281
282	/* Receive Control and Status Registers (0x2_n300) */
283	u32	rctrl;		/* Receive Control */
284	u32	rstat;		/* Receive Status */
285	u32	res308;
286	u32	rbdlen;		/* RxBD Data Length */
287	u32	res310[4];
288	u32	res320;
289	u32	crbptr;		/* Current Receive Buffer Pointer */
290	u32	res328[6];
291	u32	mrblr;		/* Maximum Receive Buffer Length */
292	u32	res344[16];
293	u32	rbptr;		/* RxBD Pointer */
294	u32	res388[30];
295	/* (0x2_n400) */
296	u32	res400;
297	u32	rbase;		/* RxBD Base Address */
298	u32	res408[62];
299
300	/* MAC Registers (0x2_n500) */
301	u32	maccfg1;	/* MAC Configuration #1 */
302	u32	maccfg2;	/* MAC Configuration #2 */
303	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
304	u32	hafdup;		/* Half-duplex */
305	u32	maxfrm;		/* Maximum Frame */
306	u32	res514;
307	u32	res518;
308
309	u32	res51c;
310
311	u32	resmdio[6];
312
313	u32	res538;
314
315	u32	ifstat;		/* Interface Status */
316	u32	macstnaddr1;	/* Station Address, part 1 */
317	u32	macstnaddr2;	/* Station Address, part 2 */
318	u32	res548[46];
319
320	/* (0x2_n600) */
321	u32	res600[32];
322
323	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
324	struct tsec_rmon_mib	rmon;
325	u32	res740[48];
326
327	/* Hash Function Registers (0x2_n800) */
328	struct tsec_hash_regs	hash;
329
330	u32	res900[128];
331
332	/* Pattern Registers (0x2_nb00) */
333	u32	resb00[62];
334	u32	attr; /* Default Attribute Register */
335	u32	attreli; /* Default Attribute Extract Length and Index */
336
337	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
338	u32	resc00[256];
339};
340
341#define TSEC_GIGABIT	(1 << 0)
342
343/* These flags currently only have meaning if we're using the eTSEC */
344#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
345#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
346
347#define TX_BUF_CNT	2
348
349struct tsec_data {
350	u32 mdio_regs_off;
351};
352
353struct tsec_private {
354	struct txbd8 __iomem txbd[TX_BUF_CNT];
355	struct rxbd8 __iomem rxbd[PKTBUFSRX];
356	struct tsec __iomem *regs;
357	struct tsec_mii_mng __iomem *phyregs_sgmii;
358	struct phy_device *phydev;
359	phy_interface_t interface;
360	struct mii_dev *bus;
361	uint phyaddr;
362	uint tbiaddr;
363	char mii_devname[16];
364	u32 flags;
365	uint rx_idx;	/* index of the current RX buffer */
366	uint tx_idx;	/* index of the current TX buffer */
367	struct udevice *dev;
368};
369
370struct tsec_info_struct {
371	struct tsec __iomem *regs;
372	struct tsec_mii_mng __iomem *miiregs_sgmii;
373	char *devname;
374	char *mii_devname;
375	phy_interface_t interface;
376	unsigned int phyaddr;
377	u32 flags;
378};
379
380#endif /* __TSEC_H */
381