1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 */
6
7#ifndef _SPARTAN3_H_
8#define _SPARTAN3_H_
9
10#include <xilinx.h>
11
12/* Slave Parallel Implementation function table */
13typedef struct {
14	xilinx_pre_fn	pre;
15	xilinx_pgm_fn	pgm;
16	xilinx_init_fn	init;
17	xilinx_err_fn	err;
18	xilinx_done_fn	done;
19	xilinx_clk_fn	clk;
20	xilinx_cs_fn	cs;
21	xilinx_wr_fn	wr;
22	xilinx_rdata_fn	rdata;
23	xilinx_wdata_fn	wdata;
24	xilinx_busy_fn	busy;
25	xilinx_abort_fn	abort;
26	xilinx_post_fn	post;
27} xilinx_spartan3_slave_parallel_fns;
28
29/* Slave Serial Implementation function table */
30typedef struct {
31	xilinx_pre_fn	pre;
32	xilinx_pgm_fn	pgm;
33	xilinx_clk_fn	clk;
34	xilinx_init_fn	init;
35	xilinx_done_fn	done;
36	xilinx_wr_fn	wr;
37	xilinx_post_fn	post;
38	xilinx_bwr_fn	bwr; /* block write function */
39	xilinx_abort_fn abort;
40} xilinx_spartan3_slave_serial_fns;
41
42#if defined(CONFIG_FPGA_SPARTAN3)
43extern struct xilinx_fpga_op spartan3_op;
44# define FPGA_SPARTAN3_OPS	&spartan3_op
45#else
46# define FPGA_SPARTAN3_OPS	NULL
47#endif
48
49/* Device Image Sizes
50 *********************************************************************/
51/* Spartan-III (1.2V) */
52#define XILINX_XC3S50_SIZE	439264/8
53#define XILINX_XC3S200_SIZE	1047616/8
54#define XILINX_XC3S400_SIZE	1699136/8
55#define XILINX_XC3S1000_SIZE	3223488/8
56#define XILINX_XC3S1500_SIZE	5214784/8
57#define XILINX_XC3S2000_SIZE	7673024/8
58#define XILINX_XC3S4000_SIZE	11316864/8
59#define XILINX_XC3S5000_SIZE	13271936/8
60
61/* Spartan-3E (v3.4) */
62#define	XILINX_XC3S100E_SIZE	581344/8
63#define	XILINX_XC3S250E_SIZE	1353728/8
64#define	XILINX_XC3S500E_SIZE	2270208/8
65#define	XILINX_XC3S1200E_SIZE	3841184/8
66#define	XILINX_XC3S1600E_SIZE	5969696/8
67
68/*
69 * Spartan-6 : the Spartan-6 family can be programmed
70 * exactly as the Spartan-3
71 */
72#define XILINK_XC6SLX4_SIZE	(3713568/8)
73
74/* Descriptor Macros
75 *********************************************************************/
76/* Spartan-III devices */
77#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
78{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
79	FPGA_SPARTAN3_OPS }
80
81#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
82{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
83	FPGA_SPARTAN3_OPS }
84
85#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
86{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
87	FPGA_SPARTAN3_OPS }
88
89#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
90{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
91	FPGA_SPARTAN3_OPS }
92
93#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
94{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
95	FPGA_SPARTAN3_OPS }
96
97#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
98{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
99	FPGA_SPARTAN3_OPS }
100
101#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
102{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
103	FPGA_SPARTAN3_OPS }
104
105#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
106{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
107	FPGA_SPARTAN3_OPS }
108
109/* Spartan-3E devices */
110#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
111{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
112	FPGA_SPARTAN3_OPS }
113
114#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
115{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
116	FPGA_SPARTAN3_OPS }
117
118#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
119{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
120	FPGA_SPARTAN3_OPS }
121
122#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
123{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
124	FPGA_SPARTAN3_OPS }
125
126#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
127{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
128	FPGA_SPARTAN3_OPS }
129
130#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
131{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
132	FPGA_SPARTAN3_OPS }
133
134#endif /* _SPARTAN3_H_ */
135