1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2002 4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5 */ 6 7#ifndef _SPARTAN2_H_ 8#define _SPARTAN2_H_ 9 10#include <xilinx.h> 11 12/* Slave Parallel Implementation function table */ 13typedef struct { 14 xilinx_pre_fn pre; 15 xilinx_pgm_fn pgm; 16 xilinx_init_fn init; 17 xilinx_err_fn err; 18 xilinx_done_fn done; 19 xilinx_clk_fn clk; 20 xilinx_cs_fn cs; 21 xilinx_wr_fn wr; 22 xilinx_rdata_fn rdata; 23 xilinx_wdata_fn wdata; 24 xilinx_busy_fn busy; 25 xilinx_abort_fn abort; 26 xilinx_post_fn post; 27} xilinx_spartan2_slave_parallel_fns; 28 29/* Slave Serial Implementation function table */ 30typedef struct { 31 xilinx_pre_fn pre; 32 xilinx_pgm_fn pgm; 33 xilinx_clk_fn clk; 34 xilinx_init_fn init; 35 xilinx_done_fn done; 36 xilinx_wr_fn wr; 37 xilinx_post_fn post; 38} xilinx_spartan2_slave_serial_fns; 39 40#if defined(CONFIG_FPGA_SPARTAN2) 41extern struct xilinx_fpga_op spartan2_op; 42# define FPGA_SPARTAN2_OPS &spartan2_op 43#else 44# define FPGA_SPARTAN2_OPS NULL 45#endif 46 47/* Device Image Sizes 48 *********************************************************************/ 49/* Spartan-II (2.5V) */ 50#define XILINX_XC2S15_SIZE 197728/8 51#define XILINX_XC2S30_SIZE 336800/8 52#define XILINX_XC2S50_SIZE 559232/8 53#define XILINX_XC2S100_SIZE 781248/8 54#define XILINX_XC2S150_SIZE 1040128/8 55#define XILINX_XC2S200_SIZE 1335872/8 56 57/* Spartan-IIE (1.8V) */ 58#define XILINX_XC2S50E_SIZE 630048/8 59#define XILINX_XC2S100E_SIZE 863840/8 60#define XILINX_XC2S150E_SIZE 1134496/8 61#define XILINX_XC2S200E_SIZE 1442016/8 62#define XILINX_XC2S300E_SIZE 1875648/8 63 64/* Descriptor Macros 65 *********************************************************************/ 66/* Spartan-II devices */ 67#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ 68{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ 69 FPGA_SPARTAN2_OPS } 70 71#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ 72{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ 73 FPGA_SPARTAN2_OPS } 74 75#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ 76{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ 77 FPGA_SPARTAN2_OPS } 78 79#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ 80{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ 81 FPGA_SPARTAN2_OPS } 82 83#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ 84{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ 85 FPGA_SPARTAN2_OPS } 86 87#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ 88{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ 89 FPGA_SPARTAN2_OPS } 90 91#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ 92{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ 93 FPGA_SPARTAN2_OPS } 94 95#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ 96{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ 97 FPGA_SPARTAN2_OPS } 98 99#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ 100{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ 101 FPGA_SPARTAN2_OPS } 102 103#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ 104{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ 105 FPGA_SPARTAN2_OPS } 106 107#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ 108{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ 109 FPGA_SPARTAN2_OPS } 110 111#endif /* _SPARTAN2_H_ */ 112