1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2015 Google, Inc
4 */
5
6#ifndef __S5M8767_H_
7#define __S5M8767_H_
8
9enum s5m8767_regnum {
10	S5M8767_BUCK1 = 0,
11	S5M8767_BUCK2,
12	S5M8767_BUCK3,
13	S5M8767_BUCK4,
14	S5M8767_BUCK5,
15	S5M8767_BUCK6,
16	S5M8767_BUCK7,
17	S5M8767_BUCK8,
18	S5M8767_BUCK9,
19	S5M8767_LDO1,
20	S5M8767_LDO2,
21	S5M8767_LDO3,
22	S5M8767_LDO4,
23	S5M8767_LDO5,
24	S5M8767_LDO6,
25	S5M8767_LDO7,
26	S5M8767_LDO8,
27	S5M8767_LDO9,
28	S5M8767_LDO10,
29	S5M8767_LDO11,
30	S5M8767_LDO12,
31	S5M8767_LDO13,
32	S5M8767_LDO14,
33	S5M8767_LDO15,
34	S5M8767_LDO16,
35	S5M8767_LDO17,
36	S5M8767_LDO18,
37	S5M8767_LDO19,
38	S5M8767_LDO20,
39	S5M8767_LDO21,
40	S5M8767_LDO22,
41	S5M8767_LDO23,
42	S5M8767_LDO24,
43	S5M8767_LDO25,
44	S5M8767_LDO26,
45	S5M8767_LDO27,
46	S5M8767_LDO28,
47	S5M8767_EN32KHZ_CP,
48
49	S5M8767_NUM_OF_REGS,
50};
51
52struct sec_voltage_desc {
53	int max;
54	int min;
55	int step;
56};
57
58/**
59 * struct s5m8767_para - s5m8767 register parameters
60 * @param vol_addr	i2c address of the given buck/ldo register
61 * @param vol_bitpos	bit position to be set or clear within register
62 * @param vol_bitmask	bit mask value
63 * @param reg_enaddr	control register address, which enable the given
64 *			given buck/ldo.
65 * @param reg_enbiton	value to be written to buck/ldo to make it ON
66 * @param vol		Voltage information
67 */
68struct s5m8767_para {
69	enum s5m8767_regnum regnum;
70	u8	vol_addr;
71	u8	vol_bitpos;
72	u8	vol_bitmask;
73	u8	reg_enaddr;
74	u8	reg_enbiton;
75	const struct sec_voltage_desc *vol;
76};
77
78/* Drivers name */
79#define S5M8767_LDO_DRIVER	"s5m8767_ldo"
80#define S5M8767_BUCK_DRIVER	"s5m8767_buck"
81
82int s5m8767_enable_32khz_cp(struct udevice *dev);
83
84#endif /* __S5M8767_PMIC_H_ */
85