1#ifndef _MICREL_H
2
3#define MII_KSZ9021_EXT_COMMON_CTRL		0x100
4#define MII_KSZ9021_EXT_STRAP_STATUS		0x101
5#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE	0x102
6#define MII_KSZ9021_EXT_OP_STRAP_STATUS		0x103
7#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW	0x104
8#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW	0x105
9#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW	0x106
10#define MII_KSZ9021_EXT_ANALOG_TEST		0x107
11/* Register operations */
12#define MII_KSZ9031_MOD_REG			0x0000
13/* Data operations */
14#define MII_KSZ9031_MOD_DATA_NO_POST_INC	0x4000
15#define MII_KSZ9031_MOD_DATA_POST_INC_RW	0x8000
16#define MII_KSZ9031_MOD_DATA_POST_INC_W		0xC000
17
18#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW	0x4
19#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW	0x5
20#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW	0x6
21#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW	0x8
22
23#define MII_KSZ9031_FLP_BURST_TX_LO		0x3
24#define MII_KSZ9031_FLP_BURST_TX_HI		0x4
25
26#define MII_KSZ9x31_SILICON_REV_MASK		0xfffff0
27
28#define MII_KSZ9131_RXTXDLL_BYPASS		BIT(12)
29#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL	0x4c
30#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL	0x4d
31
32#define PHY_ID_KSZ9031				0x00221620
33#define PHY_ID_KSZ9131				0x00221640
34
35
36/* Registers */
37#define MMD_ACCESS_CONTROL	0xd
38#define MMD_ACCESS_REG_DATA	0xe
39
40struct phy_device;
41int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
42int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
43
44int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
45			       int regnum, u16 mode, u16 val);
46int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
47			      int regnum, u16 mode);
48int ksz9xx1_phy_get_id(struct phy_device *phydev);
49
50#endif
51