1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net> 4 * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de> 5 * Changes for multibus/multiadapter I2C support. 6 * 7 * (C) Copyright 2001 8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. 9 * 10 * The original I2C interface was 11 * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) 12 * AIRVENT SAM s.p.a - RIMINI(ITALY) 13 * but has been changed substantially. 14 */ 15 16#ifndef _I2C_H_ 17#define _I2C_H_ 18 19#include <linker_lists.h> 20 21/* 22 * For now there are essentially two parts to this file - driver model 23 * here at the top, and the older code below (with CONFIG_SYS_I2C_LEGACY being 24 * most recent). The plan is to migrate everything to driver model. 25 * The driver model structures and API are separate as they are different 26 * enough as to be incompatible for compilation purposes. 27 */ 28 29enum dm_i2c_chip_flags { 30 DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */ 31 DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */ 32 DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ 33}; 34 35/** enum i2c_speed_mode - standard I2C speed modes */ 36enum i2c_speed_mode { 37 IC_SPEED_MODE_STANDARD, 38 IC_SPEED_MODE_FAST, 39 IC_SPEED_MODE_FAST_PLUS, 40 IC_SPEED_MODE_HIGH, 41 IC_SPEED_MODE_FAST_ULTRA, 42 43 IC_SPEED_MODE_COUNT, 44}; 45 46/** enum i2c_speed_rate - standard I2C speeds in Hz */ 47enum i2c_speed_rate { 48 I2C_SPEED_STANDARD_RATE = 100000, 49 I2C_SPEED_FAST_RATE = 400000, 50 I2C_SPEED_FAST_PLUS_RATE = 1000000, 51 I2C_SPEED_HIGH_RATE = 3400000, 52 I2C_SPEED_FAST_ULTRA_RATE = 5000000, 53}; 54 55/** enum i2c_address_mode - available address modes */ 56enum i2c_address_mode { 57 I2C_MODE_7_BIT, 58 I2C_MODE_10_BIT 59}; 60 61/** enum i2c_device_t - Types of I2C devices, used for compatible strings */ 62enum i2c_device_t { 63 I2C_DEVICE_GENERIC, 64 I2C_DEVICE_HID_OVER_I2C, 65}; 66 67struct udevice; 68/** 69 * struct dm_i2c_chip - information about an i2c chip 70 * 71 * An I2C chip is a device on the I2C bus. It sits at a particular address 72 * and normally supports 7-bit or 10-bit addressing. 73 * 74 * To obtain this structure, use dev_get_parent_plat(dev) where dev is 75 * the chip to examine. 76 * 77 * @chip_addr: Chip address on bus 78 * @offset_len: Length of offset in bytes. A single byte offset can 79 * represent up to 256 bytes. A value larger than 1 may be 80 * needed for larger devices. 81 * @flags: Flags for this chip (dm_i2c_chip_flags) 82 * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for 83 * devices which steal addresses as part of offset. 84 * If offset_len is zero, then the offset is encoded 85 * completely within the chip address itself. 86 * e.g. a devce with chip address of 0x2c with 512 87 * registers might use the bottom bit of the address 88 * to indicate which half of the address space is being 89 * accessed while still only using 1 byte offset. 90 * This means it will respond to chip address 0x2c and 91 * 0x2d. 92 * A real world example is the Atmel AT24C04. It's 93 * datasheet explains it's usage of this addressing 94 * mode. 95 * @emul: Emulator for this chip address (only used for emulation) 96 * @emul_idx: Emulator index, used for of-platdata and set by each i2c chip's 97 * bind() method. This allows i2c_emul_find() to work with of-platdata. 98 */ 99struct dm_i2c_chip { 100 uint chip_addr; 101 uint offset_len; 102 uint flags; 103 uint chip_addr_offset_mask; 104#ifdef CONFIG_SANDBOX 105 struct udevice *emul; 106 bool test_mode; 107 int emul_idx; 108#endif 109}; 110 111/** 112 * struct dm_i2c_bus- information about an i2c bus 113 * 114 * An I2C bus contains 0 or more chips on it, each at its own address. The 115 * bus can operate at different speeds (measured in Hz, typically 100KHz 116 * or 400KHz). 117 * 118 * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the 119 * I2C bus udevice. 120 * 121 * @speed_hz: Bus speed in hertz (typically 100000) 122 * @max_transaction_bytes: Maximal size of single I2C transfer 123 */ 124struct dm_i2c_bus { 125 int speed_hz; 126 int max_transaction_bytes; 127}; 128 129/* 130 * Not all of these flags are implemented in the U-Boot API 131 */ 132enum dm_i2c_msg_flags { 133 I2C_M_TEN = 0x0010, /* ten-bit chip address */ 134 I2C_M_RD = 0x0001, /* read data, from slave to master */ 135 I2C_M_STOP = 0x8000, /* send stop after this message */ 136 I2C_M_NOSTART = 0x4000, /* no start before this message */ 137 I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ 138 I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ 139 I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ 140 I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ 141}; 142 143/** 144 * struct i2c_msg - an I2C message 145 * 146 * @addr: Slave address 147 * @flags: Flags (see enum dm_i2c_msg_flags) 148 * @len: Length of buffer in bytes, may be 0 for a probe 149 * @buf: Buffer to send/receive, or NULL if no data 150 */ 151struct i2c_msg { 152 uint addr; 153 uint flags; 154 uint len; 155 u8 *buf; 156}; 157 158/** 159 * struct i2c_msg_list - a list of I2C messages 160 * 161 * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem 162 * appropriate in U-Boot. 163 * 164 * @msg: Pointer to i2c_msg array 165 * @nmsgs: Number of elements in the array 166 */ 167struct i2c_msg_list { 168 struct i2c_msg *msgs; 169 uint nmsgs; 170}; 171 172/** 173 * dm_i2c_read() - read bytes from an I2C chip 174 * 175 * To obtain an I2C device (called a 'chip') given the I2C bus address you 176 * can use i2c_get_chip(). To obtain a bus by bus number use 177 * uclass_get_device_by_seq(UCLASS_I2C, <bus number>). 178 * 179 * To set the address length of a devce use i2c_set_addr_len(). It 180 * defaults to 1. 181 * 182 * @dev: Chip to read from 183 * @offset: Offset within chip to start reading 184 * @buffer: Place to put data 185 * @len: Number of bytes to read 186 * 187 * Return: 0 on success, -ve on failure 188 */ 189int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len); 190 191/** 192 * dm_i2c_write() - write bytes to an I2C chip 193 * 194 * See notes for dm_i2c_read() above. 195 * 196 * @dev: Chip to write to 197 * @offset: Offset within chip to start writing 198 * @buffer: Buffer containing data to write 199 * @len: Number of bytes to write 200 * 201 * Return: 0 on success, -ve on failure 202 */ 203int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, 204 int len); 205 206/** 207 * dm_i2c_probe() - probe a particular chip address 208 * 209 * This can be useful to check for the existence of a chip on the bus. 210 * It is typically implemented by writing the chip address to the bus 211 * and checking that the chip replies with an ACK. 212 * 213 * @bus: Bus to probe 214 * @chip_addr: 7-bit address to probe (10-bit and others are not supported) 215 * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags) 216 * @devp: Returns the device found, or NULL if none 217 * Return: 0 if a chip was found at that address, -ve if not 218 */ 219int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, 220 struct udevice **devp); 221 222/** 223 * dm_i2c_reg_read() - Read a value from an I2C register 224 * 225 * This reads a single value from the given address in an I2C chip 226 * 227 * @dev: Device to use for transfer 228 * @addr: Address to read from 229 * Return: value read, or -ve on error 230 */ 231int dm_i2c_reg_read(struct udevice *dev, uint offset); 232 233/** 234 * dm_i2c_reg_write() - Write a value to an I2C register 235 * 236 * This writes a single value to the given address in an I2C chip 237 * 238 * @dev: Device to use for transfer 239 * @addr: Address to write to 240 * @val: Value to write (normally a byte) 241 * Return: 0 on success, -ve on error 242 */ 243int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val); 244 245/** 246 * dm_i2c_reg_clrset() - Apply bitmask to an I2C register 247 * 248 * Read value, apply bitmask and write modified value back to the 249 * given address in an I2C chip 250 * 251 * @dev: Device to use for transfer 252 * @offset: Address for the R/W operation 253 * @clr: Bitmask of bits that should be cleared 254 * @set: Bitmask of bits that should be set 255 * Return: 0 on success, -ve on error 256 */ 257int dm_i2c_reg_clrset(struct udevice *dev, uint offset, u32 clr, u32 set); 258 259/** 260 * dm_i2c_xfer() - Transfer messages over I2C 261 * 262 * This transfers a raw message. It is best to use dm_i2c_reg_read/write() 263 * instead. 264 * 265 * @dev: Device to use for transfer 266 * @msg: List of messages to transfer 267 * @nmsgs: Number of messages to transfer 268 * Return: 0 on success, -ve on error 269 */ 270int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs); 271 272/** 273 * dm_i2c_set_bus_speed() - set the speed of a bus 274 * 275 * @bus: Bus to adjust 276 * @speed: Requested speed in Hz 277 * Return: 0 if OK, -EINVAL for invalid values 278 */ 279int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed); 280 281/** 282 * dm_i2c_get_bus_speed() - get the speed of a bus 283 * 284 * @bus: Bus to check 285 * Return: speed of selected I2C bus in Hz, -ve on error 286 */ 287int dm_i2c_get_bus_speed(struct udevice *bus); 288 289/** 290 * i2c_set_chip_flags() - set flags for a chip 291 * 292 * Typically addresses are 7 bits, but for 10-bit addresses you should set 293 * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing. 294 * 295 * @dev: Chip to adjust 296 * @flags: New flags 297 * Return: 0 if OK, -EINVAL if value is unsupported, other -ve value on error 298 */ 299int i2c_set_chip_flags(struct udevice *dev, uint flags); 300 301/** 302 * i2c_get_chip_flags() - get flags for a chip 303 * 304 * @dev: Chip to check 305 * @flagsp: Place to put flags 306 * Return: 0 if OK, other -ve value on error 307 */ 308int i2c_get_chip_flags(struct udevice *dev, uint *flagsp); 309 310/** 311 * i2c_set_offset_len() - set the offset length for a chip 312 * 313 * The offset used to access a chip may be up to 4 bytes long. Typically it 314 * is only 1 byte, which is enough for chips with 256 bytes of memory or 315 * registers. The default value is 1, but you can call this function to 316 * change it. 317 * 318 * @offset_len: New offset length value (typically 1 or 2) 319 */ 320int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); 321 322/** 323 * i2c_get_offset_len() - get the offset length for a chip 324 * 325 * @return: Current offset length value (typically 1 or 2) 326 */ 327int i2c_get_chip_offset_len(struct udevice *dev); 328 329/** 330 * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset 331 * 332 * Some devices listen on multiple chip addresses to achieve larger offsets 333 * than their single or multiple byte offsets would allow for. You can use this 334 * function to set the bits that are valid to be used for offset overflow. 335 * 336 * @mask: The mask to be used for high offset bits within address 337 * Return: 0 if OK, other -ve value on error 338 */ 339int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask); 340 341/* 342 * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset 343 * 344 * Return: current chip addr offset mask 345 */ 346uint i2c_get_chip_addr_offset_mask(struct udevice *dev); 347 348/** 349 * i2c_deblock() - recover a bus that is in an unknown state 350 * 351 * See the deblock() method in 'struct dm_i2c_ops' for full information 352 * 353 * @bus: Bus to recover 354 * Return: 0 if OK, -ve on error 355 */ 356int i2c_deblock(struct udevice *bus); 357 358/** 359 * i2c_deblock_gpio_loop() - recover a bus from an unknown state by toggling SDA/SCL 360 * 361 * This is the inner logic used for toggling I2C SDA/SCL lines as GPIOs 362 * for deblocking the I2C bus. 363 * 364 * @sda_pin: SDA GPIO 365 * @scl_pin: SCL GPIO 366 * @scl_count: Number of SCL clock cycles generated to deblock SDA 367 * @start_count:Number of I2C start conditions sent after deblocking SDA 368 * @delay: Delay between SCL clock line changes 369 * Return: 0 if OK, -ve on error 370 */ 371struct gpio_desc; 372int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, struct gpio_desc *scl_pin, 373 unsigned int scl_count, unsigned int start_count, 374 unsigned int delay); 375 376/** 377 * struct dm_i2c_ops - driver operations for I2C uclass 378 * 379 * Drivers should support these operations unless otherwise noted. These 380 * operations are intended to be used by uclass code, not directly from 381 * other code. 382 */ 383struct dm_i2c_ops { 384 /** 385 * xfer() - transfer a list of I2C messages 386 * 387 * @bus: Bus to read from 388 * @msg: List of messages to transfer 389 * @nmsgs: Number of messages in the list 390 * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte, 391 * -ECOMM if the speed cannot be supported, -EPROTO if the chip 392 * flags cannot be supported, other -ve value on some other error 393 */ 394 int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs); 395 396 /** 397 * probe_chip() - probe for the presense of a chip address 398 * 399 * This function is optional. If omitted, the uclass will send a zero 400 * length message instead. 401 * 402 * @bus: Bus to probe 403 * @chip_addr: Chip address to probe 404 * @chip_flags: Probe flags (enum dm_i2c_chip_flags) 405 * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back 406 * to default probem other -ve value on error 407 */ 408 int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags); 409 410 /** 411 * set_bus_speed() - set the speed of a bus (optional) 412 * 413 * The bus speed value will be updated by the uclass if this function 414 * does not return an error. This method is optional - if it is not 415 * provided then the driver can read the speed from 416 * dev_get_uclass_priv(bus)->speed_hz 417 * 418 * @bus: Bus to adjust 419 * @speed: Requested speed in Hz 420 * @return 0 if OK, -EINVAL for invalid values 421 */ 422 int (*set_bus_speed)(struct udevice *bus, unsigned int speed); 423 424 /** 425 * get_bus_speed() - get the speed of a bus (optional) 426 * 427 * Normally this can be provided by the uclass, but if you want your 428 * driver to check the bus speed by looking at the hardware, you can 429 * implement that here. This method is optional. This method would 430 * normally be expected to return dev_get_uclass_priv(bus)->speed_hz. 431 * 432 * @bus: Bus to check 433 * @return speed of selected I2C bus in Hz, -ve on error 434 */ 435 int (*get_bus_speed)(struct udevice *bus); 436 437 /** 438 * set_flags() - set the flags for a chip (optional) 439 * 440 * This is generally implemented by the uclass, but drivers can 441 * check the value to ensure that unsupported options are not used. 442 * This method is optional. If provided, this method will always be 443 * called when the flags change. 444 * 445 * @dev: Chip to adjust 446 * @flags: New flags value 447 * @return 0 if OK, -EINVAL if value is unsupported 448 */ 449 int (*set_flags)(struct udevice *dev, uint flags); 450 451 /** 452 * deblock() - recover a bus that is in an unknown state 453 * 454 * I2C is a synchronous protocol and resets of the processor in the 455 * middle of an access can block the I2C Bus until a powerdown of 456 * the full unit is done. This is because slaves can be stuck 457 * waiting for addition bus transitions for a transaction that will 458 * never complete. Resetting the I2C master does not help. The only 459 * way is to force the bus through a series of transitions to make 460 * sure that all slaves are done with the transaction. This method 461 * performs this 'deblocking' if support by the driver. 462 * 463 * This method is optional. 464 */ 465 int (*deblock)(struct udevice *bus); 466}; 467 468#define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops) 469 470/** 471 * struct i2c_mux_ops - operations for an I2C mux 472 * 473 * The current mux state is expected to be stored in the mux itself since 474 * it is the only thing that knows how to make things work. The mux can 475 * record the current state and then avoid switching unless it is necessary. 476 * So select() can be skipped if the mux is already in the correct state. 477 * Also deselect() can be made a nop if required. 478 */ 479struct i2c_mux_ops { 480 /** 481 * select() - select one of of I2C buses attached to a mux 482 * 483 * This will be called when there is no bus currently selected by the 484 * mux. This method does not need to deselect the old bus since 485 * deselect() will be already have been called if necessary. 486 * 487 * @mux: Mux device 488 * @bus: I2C bus to select 489 * @channel: Channel number correponding to the bus to select 490 * @return 0 if OK, -ve on error 491 */ 492 int (*select)(struct udevice *mux, struct udevice *bus, uint channel); 493 494 /** 495 * deselect() - select one of of I2C buses attached to a mux 496 * 497 * This is used to deselect the currently selected I2C bus. 498 * 499 * @mux: Mux device 500 * @bus: I2C bus to deselect 501 * @channel: Channel number correponding to the bus to deselect 502 * @return 0 if OK, -ve on error 503 */ 504 int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel); 505}; 506 507#define i2c_mux_get_ops(dev) ((struct i2c_mux_ops *)(dev)->driver->ops) 508 509/** 510 * i2c_get_chip() - get a device to use to access a chip on a bus 511 * 512 * This returns the device for the given chip address. The device can then 513 * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc. 514 * 515 * @bus: Bus to examine 516 * @chip_addr: Chip address for the new device 517 * @offset_len: Length of a register offset in bytes (normally 1) 518 * @devp: Returns pointer to new device if found or -ENODEV if not 519 * found 520 */ 521int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, 522 struct udevice **devp); 523 524/** 525 * i2c_get_chip_for_busnum() - get a device to use to access a chip on 526 * a bus number 527 * 528 * This returns the device for the given chip address on a particular bus 529 * number. 530 * 531 * @busnum: Bus number to examine 532 * @chip_addr: Chip address for the new device 533 * @offset_len: Length of a register offset in bytes (normally 1) 534 * @devp: Returns pointer to new device if found or -ENODEV if not 535 * found 536 */ 537int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, 538 struct udevice **devp); 539 540/** 541 * i2c_get_chip_by_phandle() - get a device to use to access a chip 542 * based on a phandle property pointing to it 543 * 544 * @parent: Parent device containing the phandle pointer 545 * @name: Name of phandle property in the parent device node 546 * @devp: Returns pointer to new device or NULL if not found 547 * Return: 0 on success, -ve on failure 548 */ 549int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name, 550 struct udevice **devp); 551 552/** 553 * i2c_chip_of_to_plat() - Decode standard I2C platform data 554 * 555 * This decodes the chip address from a device tree node and puts it into 556 * its dm_i2c_chip structure. This should be called in your driver's 557 * of_to_plat() method. 558 * 559 * @blob: Device tree blob 560 * @node: Node offset to read from 561 * @spi: Place to put the decoded information 562 */ 563int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip); 564 565/** 566 * i2c_dump_msgs() - Dump a list of I2C messages 567 * 568 * This may be useful for debugging. 569 * 570 * @msg: Message list to dump 571 * @nmsgs: Number of messages 572 */ 573void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); 574 575/** 576 * i2c_emul_find() - Find an emulator for an i2c sandbox device 577 * 578 * This looks at the device's 'emul' phandle 579 * 580 * @dev: Device to find an emulator for 581 * @emulp: Returns the associated emulator, if found * 582 * Return: 0 if OK, -ENOENT or -ENODEV if not found 583 */ 584int i2c_emul_find(struct udevice *dev, struct udevice **emulp); 585 586/** 587 * i2c_emul_set_idx() - Set the emulator index for an i2c sandbox device 588 * 589 * With of-platdata we cannot find the emulator using the device tree, so rely 590 * on the bind() method of each i2c driver calling this function to tell us 591 * the of-platdata idx of the emulator 592 * 593 * @dev: i2c device to set the emulator for 594 * @emul_idx: of-platdata index for that emulator 595 */ 596void i2c_emul_set_idx(struct udevice *dev, int emul_idx); 597 598/** 599 * i2c_emul_get_device() - Find the device being emulated 600 * 601 * Given an emulator this returns the associated device 602 * 603 * @emul: Emulator for the device 604 * Return: device that @emul is emulating 605 */ 606struct udevice *i2c_emul_get_device(struct udevice *emul); 607 608/* ACPI operations for generic I2C devices */ 609extern struct acpi_ops i2c_acpi_ops; 610 611/** 612 * acpi_i2c_of_to_plat() - Read properties intended for ACPI 613 * 614 * This reads the generic I2C properties from the device tree, so that these 615 * can be used to create ACPI information for the device. 616 * 617 * See the i2c/generic-acpi.txt binding file for information about the 618 * properties. 619 * 620 * @dev: I2C device to process 621 * Return: 0 if OK, -EINVAL if acpi,hid is not present 622 */ 623int acpi_i2c_of_to_plat(struct udevice *dev); 624 625#ifdef CONFIG_SYS_I2C_EARLY_INIT 626void i2c_early_init_f(void); 627#endif 628 629#if !CONFIG_IS_ENABLED(DM_I2C) 630 631/* 632 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING 633 * 634 * The implementation MUST NOT use static or global variables if the 635 * I2C routines are used to read SDRAM configuration information 636 * because this is done before the memories are initialized. Limited 637 * use of stack-based variables are OK (the initial stack size is 638 * limited). 639 * 640 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING 641 */ 642 643/* 644 * Configuration items. 645 */ 646#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ 647 648#if !defined(CFG_SYS_I2C_MAX_HOPS) 649/* no muxes used bus = i2c adapters */ 650#define CFG_SYS_I2C_DIRECT_BUS 1 651#define CFG_SYS_I2C_MAX_HOPS 0 652#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) 653#else 654/* we use i2c muxes */ 655#undef CFG_SYS_I2C_DIRECT_BUS 656#endif 657 658/* define the I2C bus number for RTC and DTT if not already done */ 659#if !defined(CFG_SYS_RTC_BUS_NUM) 660#define CFG_SYS_RTC_BUS_NUM 0 661#endif 662 663struct i2c_adapter { 664 void (*init)(struct i2c_adapter *adap, int speed, 665 int slaveaddr); 666 int (*probe)(struct i2c_adapter *adap, uint8_t chip); 667 int (*read)(struct i2c_adapter *adap, uint8_t chip, 668 uint addr, int alen, uint8_t *buffer, 669 int len); 670 int (*write)(struct i2c_adapter *adap, uint8_t chip, 671 uint addr, int alen, uint8_t *buffer, 672 int len); 673 uint (*set_bus_speed)(struct i2c_adapter *adap, 674 uint speed); 675 int speed; 676 int waitdelay; 677 int slaveaddr; 678 int init_done; 679 int hwadapnr; 680 char *name; 681}; 682 683#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ 684 _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \ 685 { \ 686 .init = _init, \ 687 .probe = _probe, \ 688 .read = _read, \ 689 .write = _write, \ 690 .set_bus_speed = _set_speed, \ 691 .speed = _speed, \ 692 .slaveaddr = _slaveaddr, \ 693 .init_done = 0, \ 694 .hwadapnr = _hwadapnr, \ 695 .name = #_name \ 696}; 697 698#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \ 699 _set_speed, _speed, _slaveaddr, _hwadapnr) \ 700 ll_entry_declare(struct i2c_adapter, _name, i2c) = \ 701 U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ 702 _set_speed, _speed, _slaveaddr, _hwadapnr, _name); 703 704struct i2c_adapter *i2c_get_adapter(int index); 705 706#ifndef CFG_SYS_I2C_DIRECT_BUS 707struct i2c_mux { 708 int id; 709 char name[16]; 710}; 711 712struct i2c_next_hop { 713 struct i2c_mux mux; 714 uint8_t chip; 715 uint8_t channel; 716}; 717 718struct i2c_bus_hose { 719 int adapter; 720 struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; 721}; 722#define I2C_NULL_HOP {{-1, ""}, 0, 0} 723extern struct i2c_bus_hose i2c_bus[]; 724 725#define I2C_ADAPTER(bus) i2c_bus[bus].adapter 726#else 727#define I2C_ADAPTER(bus) bus 728#endif 729#define I2C_BUS gd->cur_i2c_bus 730 731#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus)) 732#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) 733#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) 734 735#ifndef CFG_SYS_I2C_DIRECT_BUS 736#define I2C_MUX_PCA9540_ID 1 737#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} 738#define I2C_MUX_PCA9542_ID 2 739#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} 740#define I2C_MUX_PCA9544_ID 3 741#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} 742#define I2C_MUX_PCA9547_ID 4 743#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} 744#define I2C_MUX_PCA9548_ID 5 745#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} 746#endif 747 748#ifndef I2C_SOFT_DECLARATIONS 749# if (defined(CONFIG_AT91RM9200) || \ 750 defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 751 defined(CONFIG_AT91SAM9263)) 752# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; 753# else 754# define I2C_SOFT_DECLARATIONS 755# endif 756#endif 757 758/* 759 * Initialization, must be called once on start up, may be called 760 * repeatedly to change the speed and slave addresses. 761 */ 762void i2c_init(int speed, int slaveaddr); 763void i2c_init_board(void); 764 765#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) 766/* 767 * i2c_get_bus_num: 768 * 769 * Returns index of currently active I2C bus. Zero-based. 770 */ 771unsigned int i2c_get_bus_num(void); 772 773/* 774 * i2c_set_bus_num: 775 * 776 * Change the active I2C bus. Subsequent read/write calls will 777 * go to this one. 778 * 779 * bus - bus index, zero based 780 * 781 * Returns: 0 on success, not 0 on failure 782 * 783 */ 784int i2c_set_bus_num(unsigned int bus); 785 786/* 787 * i2c_init_all(): 788 * 789 * Initializes all I2C adapters in the system. All i2c_adap structures must 790 * be initialized beforehead with function pointers and data, including 791 * speed and slaveaddr. Returns 0 on success, non-0 on failure. 792 */ 793void i2c_init_all(void); 794 795/* 796 * Probe the given I2C chip address. Returns 0 if a chip responded, 797 * not 0 on failure. 798 */ 799int i2c_probe(uint8_t chip); 800 801/* 802 * Read/Write interface: 803 * chip: I2C chip address, range 0..127 804 * addr: Memory (register) address within the chip 805 * alen: Number of bytes to use for addr (typically 1, 2 for larger 806 * memories, 0 for register type devices with only one 807 * register) 808 * buffer: Where to read/write the data 809 * len: How many bytes to read/write 810 * 811 * Returns: 0 on success, not 0 on failure 812 */ 813int i2c_read(uint8_t chip, unsigned int addr, int alen, 814 uint8_t *buffer, int len); 815 816int i2c_write(uint8_t chip, unsigned int addr, int alen, 817 uint8_t *buffer, int len); 818 819/* 820 * Utility routines to read/write registers. 821 */ 822uint8_t i2c_reg_read(uint8_t addr, uint8_t reg); 823 824void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val); 825 826/* 827 * i2c_set_bus_speed: 828 * 829 * Change the speed of the active I2C bus 830 * 831 * speed - bus speed in Hz 832 * 833 * Returns: new bus speed 834 * 835 */ 836unsigned int i2c_set_bus_speed(unsigned int speed); 837 838/* 839 * i2c_get_bus_speed: 840 * 841 * Returns speed of currently active I2C bus in Hz 842 */ 843 844unsigned int i2c_get_bus_speed(void); 845 846#else 847 848/* 849 * Probe the given I2C chip address. Returns 0 if a chip responded, 850 * not 0 on failure. 851 */ 852int i2c_probe(uchar chip); 853 854/* 855 * Read/Write interface: 856 * chip: I2C chip address, range 0..127 857 * addr: Memory (register) address within the chip 858 * alen: Number of bytes to use for addr (typically 1, 2 for larger 859 * memories, 0 for register type devices with only one 860 * register) 861 * buffer: Where to read/write the data 862 * len: How many bytes to read/write 863 * 864 * Returns: 0 on success, not 0 on failure 865 */ 866int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); 867int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); 868 869/* 870 * Utility routines to read/write registers. 871 */ 872static inline u8 i2c_reg_read(u8 addr, u8 reg) 873{ 874 u8 buf; 875 876#ifdef DEBUG 877 printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); 878#endif 879 880 i2c_read(addr, reg, 1, &buf, 1); 881 882 return buf; 883} 884 885static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) 886{ 887#ifdef DEBUG 888 printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", 889 __func__, addr, reg, val); 890#endif 891 892 i2c_write(addr, reg, 1, &val, 1); 893} 894 895/* 896 * Functions for setting the current I2C bus and its speed 897 */ 898 899/* 900 * i2c_set_bus_num: 901 * 902 * Change the active I2C bus. Subsequent read/write calls will 903 * go to this one. 904 * 905 * bus - bus index, zero based 906 * 907 * Returns: 0 on success, not 0 on failure 908 * 909 */ 910int i2c_set_bus_num(unsigned int bus); 911 912/* 913 * i2c_get_bus_num: 914 * 915 * Returns index of currently active I2C bus. Zero-based. 916 */ 917 918unsigned int i2c_get_bus_num(void); 919 920/* 921 * i2c_set_bus_speed: 922 * 923 * Change the speed of the active I2C bus 924 * 925 * speed - bus speed in Hz 926 * 927 * Returns: 0 on success, not 0 on failure 928 * 929 */ 930int i2c_set_bus_speed(unsigned int); 931 932/* 933 * i2c_get_bus_speed: 934 * 935 * Returns speed of currently active I2C bus in Hz 936 */ 937 938unsigned int i2c_get_bus_speed(void); 939#endif /* CONFIG_SYS_I2C_LEGACY */ 940 941/* 942 * only for backwardcompatibility, should go away if we switched 943 * completely to new multibus support. 944 */ 945#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS) 946# if !defined(CFG_SYS_MAX_I2C_BUS) 947# define CFG_SYS_MAX_I2C_BUS 2 948# endif 949# define I2C_MULTI_BUS 1 950#else 951# define CFG_SYS_MAX_I2C_BUS 1 952# define I2C_MULTI_BUS 0 953#endif 954 955/* NOTE: These two functions MUST be always_inline to avoid code growth! */ 956static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); 957static inline unsigned int I2C_GET_BUS(void) 958{ 959 return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; 960} 961 962static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); 963static inline void I2C_SET_BUS(unsigned int bus) 964{ 965 if (I2C_MULTI_BUS) 966 i2c_set_bus_num(bus); 967} 968 969/* Multi I2C definitions */ 970enum { 971 I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, 972 I2C_8, I2C_9, I2C_10, 973}; 974 975/** 976 * Get FDT values for i2c bus. 977 * 978 * @param blob Device tree blbo 979 * Return: the number of I2C bus 980 */ 981void board_i2c_init(const void *blob); 982 983/** 984 * Find the I2C bus number by given a FDT I2C node. 985 * 986 * @param blob Device tree blbo 987 * @param node FDT I2C node to find 988 * Return: the number of I2C bus (zero based), or -1 on error 989 */ 990int i2c_get_bus_num_fdt(int node); 991 992/** 993 * Reset the I2C bus represented by the given a FDT I2C node. 994 * 995 * @param blob Device tree blbo 996 * @param node FDT I2C node to find 997 * Return: 0 if port was reset, -1 if not found 998 */ 999int i2c_reset_port_fdt(const void *blob, int node); 1000 1001#endif /* !CONFIG_DM_I2C */ 1002 1003#endif /* _I2C_H_ */ 1004