1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Common internal memory map for some Freescale SoCs
4 *
5 * Copyright 2015 Freescale Semiconductor, Inc.
6 */
7
8#ifndef __FSL_SEC_MON_H
9#define __FSL_SEC_MON_H
10
11#include <asm/io.h>
12
13#ifdef CONFIG_SYS_FSL_SEC_MON_LE
14#define sec_mon_in32(a)       in_le32(a)
15#define sec_mon_out32(a, v)   out_le32(a, v)
16#define sec_mon_in16(a)       in_le16(a)
17#define sec_mon_clrbits32     clrbits_le32
18#define sec_mon_setbits32     setbits_le32
19#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
20#define sec_mon_in32(a)       in_be32(a)
21#define sec_mon_out32(a, v)   out_be32(a, v)
22#define sec_mon_in16(a)       in_be16(a)
23#define sec_mon_clrbits32     clrbits_be32
24#define sec_mon_setbits32     setbits_be32
25#endif
26
27struct ccsr_sec_mon_regs {
28	u8 reserved0[0x04];
29	u32 hp_com;	/* 0x04 SEC_MON_HP Command Register */
30	u8 reserved2[0x0c];
31	u32 hp_stat;	/* 0x08 SEC_MON_HP Status Register */
32};
33
34#define HPCOMR_SW_SV		0x100	/* Security Violation bit */
35#define HPCOMR_SW_FSV		0x200	/* Fatal Security Violation bit */
36#define HPCOMR_SSM_ST		0x1	/* SSM_ST field in SEC_MON command */
37#define HPCOMR_SSM_ST_DIS	0x2	/* Disable Secure to Trusted State */
38#define HPCOMR_SSM_SFNS_DIS	0x4	/* Disable Soft Fail to Non-Secure */
39#define HPSR_SSM_ST_CHECK	0x900	/* SEC_MON is in check state */
40#define HPSR_SSM_ST_NON_SECURE	0xb00	/* SEC_MON is in non secure state */
41#define HPSR_SSM_ST_TRUST	0xd00	/* SEC_MON is in trusted state */
42#define HPSR_SSM_ST_SOFT_FAIL	0x300	/* SEC_MON is in soft fail state */
43#define HPSR_SSM_ST_SECURE	0xf00	/* SEC_MON is in secure state */
44#define HPSR_SSM_ST_MASK	0xf00	/* Mask for SSM_ST field */
45
46/*
47 * SEC_MON read. This specifies the possible reads
48 * from the SEC_MON
49 */
50enum {
51	SEC_MON_SSM_ST,
52	SEC_MON_SW_FSV,
53	SEC_MON_SW_SV,
54};
55
56/* Transition SEC_MON state */
57int set_sec_mon_state(u32 state);
58
59#endif /* __FSL_SEC_MON_H */
60