1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * FSL SD/MMC Defines 4 *------------------------------------------------------------------- 5 * 6 * Copyright 2019 NXP 7 * Yangbo Lu <yangbo.lu@nxp.com> 8 * 9 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc 10 */ 11 12#ifndef __FSL_ESDHC_IMX_H__ 13#define __FSL_ESDHC_IMX_H__ 14 15#include <linux/bitops.h> 16#include <linux/errno.h> 17#include <asm/byteorder.h> 18 19/* needed for the mmc_cfg definition */ 20#include <mmc.h> 21 22/* FSL eSDHC-specific constants */ 23#define SYSCTL 0x0002e02c 24#define SYSCTL_INITA 0x08000000 25#define SYSCTL_TIMEOUT_MASK 0x000f0000 26#define SYSCTL_CLOCK_MASK 0x0000fff0 27#define SYSCTL_CKEN 0x00000008 28#define SYSCTL_PEREN 0x00000004 29#define SYSCTL_HCKEN 0x00000002 30#define SYSCTL_IPGEN 0x00000001 31#define SYSCTL_RSTA 0x01000000 32#define SYSCTL_RSTC 0x02000000 33#define SYSCTL_RSTD 0x04000000 34 35#define VENDORSPEC_CKEN 0x00004000 36#define VENDORSPEC_PEREN 0x00002000 37#define VENDORSPEC_HCKEN 0x00001000 38#define VENDORSPEC_IPGEN 0x00000800 39#define VENDORSPEC_INIT 0x20007809 40#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 41 42#define IRQSTAT 0x0002e030 43#define IRQSTAT_DMAE (0x10000000) 44#define IRQSTAT_AC12E (0x01000000) 45#define IRQSTAT_DEBE (0x00400000) 46#define IRQSTAT_DCE (0x00200000) 47#define IRQSTAT_DTOE (0x00100000) 48#define IRQSTAT_CIE (0x00080000) 49#define IRQSTAT_CEBE (0x00040000) 50#define IRQSTAT_CCE (0x00020000) 51#define IRQSTAT_CTOE (0x00010000) 52#define IRQSTAT_CINT (0x00000100) 53#define IRQSTAT_CRM (0x00000080) 54#define IRQSTAT_CINS (0x00000040) 55#define IRQSTAT_BRR (0x00000020) 56#define IRQSTAT_BWR (0x00000010) 57#define IRQSTAT_DINT (0x00000008) 58#define IRQSTAT_BGE (0x00000004) 59#define IRQSTAT_TC (0x00000002) 60#define IRQSTAT_CC (0x00000001) 61 62#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) 63#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ 64 IRQSTAT_DMAE) 65#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) 66 67#define IRQSTATEN 0x0002e034 68#define IRQSTATEN_DMAE (0x10000000) 69#define IRQSTATEN_AC12E (0x01000000) 70#define IRQSTATEN_DEBE (0x00400000) 71#define IRQSTATEN_DCE (0x00200000) 72#define IRQSTATEN_DTOE (0x00100000) 73#define IRQSTATEN_CIE (0x00080000) 74#define IRQSTATEN_CEBE (0x00040000) 75#define IRQSTATEN_CCE (0x00020000) 76#define IRQSTATEN_CTOE (0x00010000) 77#define IRQSTATEN_CINT (0x00000100) 78#define IRQSTATEN_CRM (0x00000080) 79#define IRQSTATEN_CINS (0x00000040) 80#define IRQSTATEN_BRR (0x00000020) 81#define IRQSTATEN_BWR (0x00000010) 82#define IRQSTATEN_DINT (0x00000008) 83#define IRQSTATEN_BGE (0x00000004) 84#define IRQSTATEN_TC (0x00000002) 85#define IRQSTATEN_CC (0x00000001) 86 87#define ESDHCCTL 0x0002e40c 88#define ESDHCCTL_PCS (0x00080000) 89 90#define PRSSTAT 0x0002e024 91#define PRSSTAT_DAT0 (0x01000000) 92#define PRSSTAT_CLSL (0x00800000) 93#define PRSSTAT_WPSPL (0x00080000) 94#define PRSSTAT_CDPL (0x00040000) 95#define PRSSTAT_CINS (0x00010000) 96#define PRSSTAT_BREN (0x00000800) 97#define PRSSTAT_BWEN (0x00000400) 98#define PRSSTAT_SDOFF (0x00000080) 99#define PRSSTAT_SDSTB (0X00000008) 100#define PRSSTAT_DLA (0x00000004) 101#define PRSSTAT_CICHB (0x00000002) 102#define PRSSTAT_CIDHB (0x00000001) 103 104#define PROCTL 0x0002e028 105#define PROCTL_INIT 0x00000020 106#define PROCTL_DTW_4 0x00000002 107#define PROCTL_DTW_8 0x00000004 108#define PROCTL_D3CD 0x00000008 109 110#define CMDARG 0x0002e008 111 112#define XFERTYP 0x0002e00c 113#define XFERTYP_CMD(x) ((x & 0x3f) << 24) 114#define XFERTYP_CMDTYP_NORMAL 0x0 115#define XFERTYP_CMDTYP_SUSPEND 0x00400000 116#define XFERTYP_CMDTYP_RESUME 0x00800000 117#define XFERTYP_CMDTYP_ABORT 0x00c00000 118#define XFERTYP_DPSEL 0x00200000 119#define XFERTYP_CICEN 0x00100000 120#define XFERTYP_CCCEN 0x00080000 121#define XFERTYP_RSPTYP_NONE 0 122#define XFERTYP_RSPTYP_136 0x00010000 123#define XFERTYP_RSPTYP_48 0x00020000 124#define XFERTYP_RSPTYP_48_BUSY 0x00030000 125#define XFERTYP_MSBSEL 0x00000020 126#define XFERTYP_DTDSEL 0x00000010 127#define XFERTYP_DDREN 0x00000008 128#define XFERTYP_AC12EN 0x00000004 129#define XFERTYP_BCEN 0x00000002 130#define XFERTYP_DMAEN 0x00000001 131 132#define CINS_TIMEOUT 1000 133#define PIO_TIMEOUT 500 134 135#define DSADDR 0x2e004 136 137#define CMDRSP0 0x2e010 138#define CMDRSP1 0x2e014 139#define CMDRSP2 0x2e018 140#define CMDRSP3 0x2e01c 141 142#define DATPORT 0x2e020 143 144#define WML 0x2e044 145#define WML_WRITE 0x00010000 146#ifdef CONFIG_FSL_SDHC_V2_3 147#define WML_RD_WML_MAX 0x80 148#define WML_WR_WML_MAX 0x80 149#define WML_RD_WML_MAX_VAL 0x0 150#define WML_WR_WML_MAX_VAL 0x0 151#define WML_RD_WML_MASK 0x7f 152#define WML_WR_WML_MASK 0x7f0000 153#else 154#define WML_RD_WML_MAX 0x10 155#define WML_WR_WML_MAX 0x80 156#define WML_RD_WML_MAX_VAL 0x10 157#define WML_WR_WML_MAX_VAL 0x80 158#define WML_RD_WML_MASK 0xff 159#define WML_WR_WML_MASK 0xff0000 160#endif 161 162#define BLKATTR 0x2e004 163#define BLKATTR_CNT(x) ((x & 0xffff) << 16) 164#define BLKATTR_SIZE(x) (x & 0x1fff) 165#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ 166 167#define HOSTCAPBLT_VS18 0x04000000 168#define HOSTCAPBLT_VS30 0x02000000 169#define HOSTCAPBLT_VS33 0x01000000 170#define HOSTCAPBLT_SRS 0x00800000 171#define HOSTCAPBLT_DMAS 0x00400000 172#define HOSTCAPBLT_HSS 0x00200000 173 174#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ 175 176/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */ 177#define MIX_CTRL_DDREN BIT(3) 178#define MIX_CTRL_DTDSEL_READ BIT(4) 179#define MIX_CTRL_AC23EN BIT(7) 180#define MIX_CTRL_EXE_TUNE BIT(22) 181#define MIX_CTRL_SMPCLK_SEL BIT(23) 182#define MIX_CTRL_AUTO_TUNE_EN BIT(24) 183#define MIX_CTRL_FBCLK_SEL BIT(25) 184#define MIX_CTRL_HS400_EN BIT(26) 185#define MIX_CTRL_HS400_ES BIT(27) 186/* Bits 3 and 6 are not SDHCI standard definitions */ 187#define MIX_CTRL_SDHCI_MASK 0xb7 188/* Tuning bits */ 189#define MIX_CTRL_TUNING_MASK 0x03c00000 190 191/* strobe dll register */ 192#define ESDHC_STROBE_DLL_CTRL 0x70 193#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0) 194#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1) 195#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 196#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 197#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 198 199#define ESDHC_STROBE_DLL_STATUS 0x74 200#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1) 201#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 202#define ESDHC_STROBE_DLL_CLK_FREQ 100000000 203 204#define ESDHC_STD_TUNING_EN BIT(24) 205/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 206#define ESDHC_TUNING_START_TAP_DEFAULT 0x1 207#define ESDHC_TUNING_START_TAP_MASK 0x7f 208#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7) 209#define ESDHC_TUNING_STEP_MASK 0x00070000 210#define ESDHC_TUNING_STEP_SHIFT 16 211 212#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 213#define ESDHC_FLAG_ENGCM07207 BIT(2) 214#define ESDHC_FLAG_USDHC BIT(3) 215#define ESDHC_FLAG_MAN_TUNING BIT(4) 216#define ESDHC_FLAG_STD_TUNING BIT(5) 217#define ESDHC_FLAG_HAVE_CAP1 BIT(6) 218#define ESDHC_FLAG_ERR004536 BIT(7) 219#define ESDHC_FLAG_HS200 BIT(8) 220#define ESDHC_FLAG_HS400 BIT(9) 221#define ESDHC_FLAG_ERR010450 BIT(10) 222#define ESDHC_FLAG_HS400_ES BIT(11) 223 224struct fsl_esdhc_cfg { 225 phys_addr_t esdhc_base; 226 u32 sdhc_clk; 227 u8 max_bus_width; 228 int wp_enable; 229 int vs18_enable; /* Use 1.8V if set to 1 */ 230 struct mmc_config cfg; 231}; 232 233/* Select the correct accessors depending on endianess */ 234#if defined CONFIG_SYS_FSL_ESDHC_LE 235#define esdhc_read32 in_le32 236#define esdhc_write32 out_le32 237#define esdhc_clrsetbits32 clrsetbits_le32 238#define esdhc_clrbits32 clrbits_le32 239#define esdhc_setbits32 setbits_le32 240#elif defined(CONFIG_SYS_FSL_ESDHC_BE) 241#define esdhc_read32 in_be32 242#define esdhc_write32 out_be32 243#define esdhc_clrsetbits32 clrsetbits_be32 244#define esdhc_clrbits32 clrbits_be32 245#define esdhc_setbits32 setbits_be32 246#elif __BYTE_ORDER == __LITTLE_ENDIAN 247#define esdhc_read32 in_le32 248#define esdhc_write32 out_le32 249#define esdhc_clrsetbits32 clrsetbits_le32 250#define esdhc_clrbits32 clrbits_le32 251#define esdhc_setbits32 setbits_le32 252#elif __BYTE_ORDER == __BIG_ENDIAN 253#define esdhc_read32 in_be32 254#define esdhc_write32 out_be32 255#define esdhc_clrsetbits32 clrsetbits_be32 256#define esdhc_clrbits32 clrbits_be32 257#define esdhc_setbits32 setbits_be32 258#else 259#error "Endianess is not defined: please fix to continue" 260#endif 261 262#ifdef CONFIG_FSL_ESDHC_IMX 263int fsl_esdhc_mmc_init(struct bd_info *bis); 264int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); 265void fdt_fixup_esdhc(void *blob, struct bd_info *bd); 266#else 267static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; } 268static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {} 269#endif /* CONFIG_FSL_ESDHC_IMX */ 270void __noreturn mmc_boot(void); 271void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); 272 273#endif /* __FSL_ESDHC_IMX_H__ */ 274