1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2015 Freescale Semiconductor
4 *
5 */
6
7#ifndef __FSL_CSU_H__
8#define __FSL_CSU_H__
9
10enum csu_cslx_access {
11	CSU_NS_SUP_R = 0x08,
12	CSU_NS_SUP_W = 0x80,
13	CSU_NS_SUP_RW = 0x88,
14	CSU_NS_USER_R = 0x04,
15	CSU_NS_USER_W = 0x40,
16	CSU_NS_USER_RW = 0x44,
17	CSU_S_SUP_R = 0x02,
18	CSU_S_SUP_W = 0x20,
19	CSU_S_SUP_RW = 0x22,
20	CSU_S_USER_R = 0x01,
21	CSU_S_USER_W = 0x10,
22	CSU_S_USER_RW = 0x11,
23	CSU_ALL_RW = 0xff,
24};
25
26struct csu_ns_dev {
27	u8 ind;
28	u8 val;
29};
30
31void enable_layerscape_ns_access(void);
32void set_devices_ns_access(unsigned long, u16 val);
33void set_pcie_ns_access(int pcie, u16 val);
34
35#endif
36