1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2009 Faraday Technology
4 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 */
6
7/*
8 * Timer
9 */
10#ifndef __FTTMR010_H
11#define __FTTMR010_H
12
13struct fttmr010 {
14	unsigned int	timer1_counter;		/* 0x00 */
15	unsigned int	timer1_load;		/* 0x04 */
16	unsigned int	timer1_match1;		/* 0x08 */
17	unsigned int	timer1_match2;		/* 0x0c */
18	unsigned int	timer2_counter;		/* 0x10 */
19	unsigned int	timer2_load;		/* 0x14 */
20	unsigned int	timer2_match1;		/* 0x18 */
21	unsigned int	timer2_match2;		/* 0x1c */
22	unsigned int	timer3_counter;		/* 0x20 */
23	unsigned int	timer3_load;		/* 0x24 */
24	unsigned int	timer3_match1;		/* 0x28 */
25	unsigned int	timer3_match2;		/* 0x2c */
26	unsigned int	cr;			/* 0x30 */
27	unsigned int	interrupt_state;	/* 0x34 */
28	unsigned int	interrupt_mask;		/* 0x38 */
29	unsigned int	revision;		/* 0x3c */
30};
31
32/*
33 * Timer Control Register
34 */
35#define FTTMR010_TM3_UPDOWN	(1 << 11)
36#define FTTMR010_TM2_UPDOWN	(1 << 10)
37#define FTTMR010_TM1_UPDOWN	(1 << 9)
38#define FTTMR010_TM3_OFENABLE	(1 << 8)
39#define FTTMR010_TM3_CLOCK	(1 << 7)
40#define FTTMR010_TM3_ENABLE	(1 << 6)
41#define FTTMR010_TM2_OFENABLE	(1 << 5)
42#define FTTMR010_TM2_CLOCK	(1 << 4)
43#define FTTMR010_TM2_ENABLE	(1 << 3)
44#define FTTMR010_TM1_OFENABLE	(1 << 2)
45#define FTTMR010_TM1_CLOCK	(1 << 1)
46#define FTTMR010_TM1_ENABLE	(1 << 0)
47
48/*
49 * Timer Interrupt State & Mask Registers
50 */
51#define FTTMR010_TM3_OVERFLOW	(1 << 8)
52#define FTTMR010_TM3_MATCH2	(1 << 7)
53#define FTTMR010_TM3_MATCH1	(1 << 6)
54#define FTTMR010_TM2_OVERFLOW	(1 << 5)
55#define FTTMR010_TM2_MATCH2	(1 << 4)
56#define FTTMR010_TM2_MATCH1	(1 << 3)
57#define FTTMR010_TM1_OVERFLOW	(1 << 2)
58#define FTTMR010_TM1_MATCH2	(1 << 1)
59#define FTTMR010_TM1_MATCH1	(1 << 0)
60
61#endif	/* __FTTMR010_H */
62