1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright(C) 2020 4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5 */ 6 7#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H 8#define __DT_BINDINGS_CLOCK_IMXRT1020_H 9 10#define IMXRT1020_CLK_DUMMY 0 11#define IMXRT1020_CLK_CKIL 1 12#define IMXRT1020_CLK_CKIH 2 13#define IMXRT1020_CLK_OSC 3 14#define IMXRT1020_CLK_PLL2_PFD0_352M 4 15#define IMXRT1020_CLK_PLL2_PFD1_594M 5 16#define IMXRT1020_CLK_PLL2_PFD2_396M 6 17#define IMXRT1020_CLK_PLL2_PFD3_297M 7 18#define IMXRT1020_CLK_PLL3_PFD0_720M 8 19#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9 20#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10 21#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11 22#define IMXRT1020_CLK_PLL2_198M 12 23#define IMXRT1020_CLK_PLL3_120M 13 24#define IMXRT1020_CLK_PLL3_80M 14 25#define IMXRT1020_CLK_PLL3_60M 15 26#define IMXRT1020_CLK_PLL2_BYPASS 16 27#define IMXRT1020_CLK_PLL3_BYPASS 17 28#define IMXRT1020_CLK_PLL6_BYPASS 18 29#define IMXRT1020_CLK_PRE_PERIPH_SEL 19 30#define IMXRT1020_CLK_PERIPH_SEL 20 31#define IMXRT1020_CLK_SEMC_ALT_SEL 21 32#define IMXRT1020_CLK_SEMC_SEL 22 33#define IMXRT1020_CLK_USDHC1_SEL 23 34#define IMXRT1020_CLK_USDHC2_SEL 24 35#define IMXRT1020_CLK_LPUART_SEL 25 36#define IMXRT1020_CLK_ARM_PODF 26 37#define IMXRT1020_CLK_LPUART_PODF 27 38#define IMXRT1020_CLK_USDHC1_PODF 28 39#define IMXRT1020_CLK_USDHC2_PODF 29 40#define IMXRT1020_CLK_SEMC_PODF 30 41#define IMXRT1020_CLK_AHB_PODF 31 42#define IMXRT1020_CLK_USDHC1 32 43#define IMXRT1020_CLK_USDHC2 33 44#define IMXRT1020_CLK_LPUART1 34 45#define IMXRT1020_CLK_SEMC 35 46#define IMXRT1020_CLK_PLL2_SYS 36 47#define IMXRT1020_CLK_PLL3_USB_OTG 37 48#define IMXRT1020_CLK_PLL4_AUDIO 38 49#define IMXRT1020_CLK_PLL6_ENET 39 50#define IMXRT1020_CLK_END 40 51 52#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */ 53