1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Samsung Electronics 4 * Sanghee Kim <sh0130.kim@samsung.com> 5 * Piotr Wilczek <p.wilczek@samsung.com> 6 * 7 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. 8 */ 9 10#ifndef __CONFIG_TRATS2_H 11#define __CONFIG_TRATS2_H 12 13#include <configs/exynos4-common.h> 14 15#ifndef CONFIG_SYS_L2CACHE_OFF 16#define CFG_SYS_PL310_BASE 0x10502000 17#endif 18 19/* TRATS2 has 4 banks of DRAM */ 20#define CFG_SYS_SDRAM_BASE 0x40000000 21#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE 22#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 23 24/* Tizen - partitions definitions */ 25#define PARTS_CSA "csa-mmc" 26#define PARTS_BOOT "boot" 27#define PARTS_QBOOT "qboot" 28#define PARTS_CSC "csc" 29#define PARTS_ROOT "platform" 30#define PARTS_DATA "data" 31#define PARTS_UMS "ums" 32 33#define PARTS_DEFAULT \ 34 "uuid_disk=${uuid_gpt_disk};" \ 35 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 36 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 37 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 38 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 39 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 40 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 41 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 42 43#define CFG_DFU_ALT \ 44 "u-boot raw 0x80 0x800;" \ 45 "/uImage ext4 0 2;" \ 46 "/modem.bin ext4 0 2;" \ 47 "/exynos4412-trats2.dtb ext4 0 2;" \ 48 ""PARTS_CSA" part 0 1;" \ 49 ""PARTS_BOOT" part 0 2;" \ 50 ""PARTS_QBOOT" part 0 3;" \ 51 ""PARTS_CSC" part 0 4;" \ 52 ""PARTS_ROOT" part 0 5;" \ 53 ""PARTS_DATA" part 0 6;" \ 54 ""PARTS_UMS" part 0 7;" \ 55 "params.bin raw 0x38 0x8;" \ 56 "/Image.itb ext4 0 2\0" 57 58#define CFG_EXTRA_ENV_SETTINGS \ 59 "bootk=" \ 60 "run loaduimage;" \ 61 "if run loaddtb; then " \ 62 "bootm 0x40007FC0 - ${fdtaddr};" \ 63 "fi;" \ 64 "bootm 0x40007FC0;\0" \ 65 "updatebackup=" \ 66 "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ 67 " mmc dev 0 0\0" \ 68 "updatebootb=" \ 69 "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ 70 "mmcboot=" \ 71 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 72 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 73 "run bootk\0" \ 74 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ 75 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 76 "verify=n\0" \ 77 "rootfstype=ext4\0" \ 78 "console=console=ttySAC2,115200n8\0" \ 79 "kernelname=uImage\0" \ 80 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ 81 "${kernelname}\0" \ 82 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 83 "${fdtfile}\0" \ 84 "mmcdev=0\0" \ 85 "mmcbootpart=2\0" \ 86 "mmcrootpart=5\0" \ 87 "opts=always_resume=1\0" \ 88 "partitions=" PARTS_DEFAULT \ 89 "dfu_alt_info=" CFG_DFU_ALT \ 90 "uartpath=ap\0" \ 91 "usbpath=ap\0" \ 92 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ 93 "consoleoff=set console console=ram; save; reset\0" \ 94 "spladdr=0x40000100\0" \ 95 "splsize=0x200\0" \ 96 "splfile=falcon.bin\0" \ 97 "spl_export=" \ 98 "setexpr spl_imgsize ${splsize} + 8 ;" \ 99 "setenv spl_imgsize 0x${spl_imgsize};" \ 100 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 101 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 102 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 103 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 104 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 105 "spl export atags 0x40007FC0;" \ 106 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 107 "mw.l ${spl_addr_tmp} ${splsize};" \ 108 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 109 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 110 "setenv spl_imgsize;" \ 111 "setenv spl_imgaddr;" \ 112 "setenv spl_addr_tmp;\0" \ 113 ENV_ITB \ 114 "fdtaddr=40800000\0" \ 115 116/* GPT */ 117 118/* Download menu - definitions for check keys */ 119#ifndef __ASSEMBLY__ 120 121#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" 122#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 123#define KEY_PWR_STATUS_MASK (1 << 0) 124#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 125#define KEY_PWR_INTERRUPT_MASK (1 << 1) 126 127#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 128#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 129#endif /* __ASSEMBLY__ */ 130 131#endif /* __CONFIG_H */ 132