1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_PICOPI_H
7#define __IMX8M_PICOPI_H
8
9#include <linux/sizes.h>
10#include <asm/arch/imx-regs.h>
11
12#ifdef CONFIG_SPL_BUILD
13/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
14
15/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
16#define CFG_MALLOC_F_ADDR		0x182000
17/* For RAW image gives a error info not panic */
18#endif
19
20/* ENET Config */
21/* ENET1 */
22#if defined(CONFIG_CMD_NET)
23#define CFG_FEC_MXC_PHYADDR		1
24#endif
25
26/* Initial environment variables */
27#define CFG_EXTRA_ENV_SETTINGS					\
28	"script=boot.scr\0"						\
29	"image=Image\0"							\
30	"console=ttymxc0,115200\0"					\
31	"fdt_addr=0x43000000\0"						\
32	"fdt_high=0xffffffffffffffff\0"					\
33	"fdt_file=imx8mq-pico-pi.dtb\0"					\
34	"initrd_addr=0x43800000\0"					\
35	"initrd_high=0xffffffffffffffff\0"				\
36	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0"		\
37	"mmcpart=1\0"	\
38	"mmcroot=/dev/mmcblk1p2 rootwait rw\0"			\
39	"mmcautodetect=yes\0"						\
40	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 "	\
41	"loadbootscript="						\
42		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
43	"bootscript=echo Running bootscript from mmc ...; source\0"	\
44	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
45	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
46	"mmcboot=echo Booting from mmc ...; "				\
47		"run mmcargs; "						\
48		"echo wait for boot; "					\
49		"fi;\0"							\
50	"netargs=setenv bootargs console=${console} "			\
51		"root=/dev/nfs "					\
52		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
53	"netboot=echo Booting from net ...; "				\
54		"run netargs;  "					\
55		"if test ${ip_dyn} = yes; then "			\
56			"setenv get_cmd dhcp; "				\
57		"else "							\
58			"setenv get_cmd tftp; "				\
59		"fi; "							\
60		"${get_cmd} ${loadaddr} ${image}; "			\
61		"booti; "
62
63/* Link Definitions */
64
65#define CFG_SYS_INIT_RAM_ADDR	0x40000000
66#define CFG_SYS_INIT_RAM_SIZE	0x80000
67
68
69#define CFG_SYS_SDRAM_BASE		0x40000000
70#define PHYS_SDRAM			0x40000000
71#define PHYS_SDRAM_SIZE			0x80000000	/* 2 GiB DDR */
72
73#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
74
75#define CFG_SYS_FSL_USDHC_NUM	2
76#define CFG_SYS_FSL_ESDHC_ADDR	0
77
78#endif
79