1/* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#ifndef __PHYCORE_IMX8MM_H
8#define __PHYCORE_IMX8MM_H
9
10#include <linux/sizes.h>
11#include <linux/stringify.h>
12#include <asm/arch/imx-regs.h>
13
14#define CFG_SYS_UBOOT_BASE \
15		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
16
17#ifdef CONFIG_SPL_BUILD
18/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
19#define CFG_MALLOC_F_ADDR		0x930000
20/* For RAW image gives a error info not panic */
21#endif
22
23#define CFG_EXTRA_ENV_SETTINGS \
24	"image=Image\0" \
25	"console=ttymxc2,115200\0" \
26	"fdt_addr=0x48000000\0" \
27	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
28	"ip_dyn=yes\0" \
29	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
30	"mmcpart=1\0" \
31	"mmcroot=2\0" \
32	"mmcautodetect=yes\0" \
33	"mmcargs=setenv bootargs console=${console} " \
34		"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
35	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
36	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
37	"mmcboot=echo Booting from mmc ...; " \
38		"run mmcargs; " \
39		"if run loadfdt; then " \
40			"booti ${loadaddr} - ${fdt_addr}; " \
41		"else " \
42			"echo WARN: Cannot load the DT; " \
43		"fi;\0 " \
44	"nfsroot=/nfs\0" \
45	"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
46		"nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
47	"netboot=echo Booting from net ...; " \
48		"run netargs; " \
49		"if test ${ip_dyn} = yes; then " \
50			"setenv get_cmd dhcp; " \
51		"else " \
52			"setenv get_cmd tftp; " \
53		"fi; " \
54		"${get_cmd} ${loadaddr} ${image}; " \
55		"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
56			"booti ${loadaddr} - ${fdt_addr}; " \
57		"else " \
58			"echo WARN: Cannot load the DT; " \
59		"fi;\0" \
60
61/* Link Definitions */
62
63#define CFG_SYS_INIT_RAM_ADDR	0x40000000
64#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
65
66
67#define CFG_SYS_SDRAM_BASE		0x40000000
68
69#define PHYS_SDRAM			0x40000000
70#define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */
71
72#endif /* __PHYCORE_IMX8MM_H */
73