1/*
2 * DDR Setup
3 */
4#define CFG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
5
6#define CFG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
7					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
8
9/*
10 * The reserved memory
11 */
12#define CFG_SYS_FLASH_BASE		0xF0000000
13
14/* Reserve 768 kB for Mon */
15
16/*
17 * Initial RAM Base Address Setup
18 */
19#define CFG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
20#define CFG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
21/*
22 * Init Local Bus Memory Controller:
23 *
24 * Bank Bus     Machine PortSz  Size  Device
25 * ---- ---     ------- ------  -----  ------
26 *  0   Local   GPCM    16 bit  256MB FLASH
27 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
28 *
29 */
30
31/*
32 * FLASH on the Local Bus
33 */
34#define CFG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
35
36#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
37
38#define CFG_SYS_KMBEC_FPGA_BASE   0xE8000000
39
40#if defined(CONFIG_CMD_NAND)
41#define CFG_SYS_NAND_BASE		CFG_SYS_KMBEC_FPGA_BASE
42#endif
43
44#if defined(CONFIG_TARGET_KMCOGE5NE) || defined(CONFIG_TARGET_KMETER1)
45/*
46 * System IO Setup
47 */
48#define CFG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
49
50#define CFG_SYS_DDRCDR (\
51	DDRCDR_EN | \
52	DDRCDR_Q_DRN)
53#else
54/*
55 * System IO Config
56 */
57#define CFG_SYS_SICRL	SICRL_IRQ_CKS
58
59#define CFG_SYS_DDRCDR (\
60	DDRCDR_EN | \
61	DDRCDR_PZ_MAXZ | \
62	DDRCDR_NZ_MAXZ | \
63	DDRCDR_M_ODR)
64#endif
65
66/*
67 * For booting Linux, the board info and command line data
68 * have to be in the first 8 MB of memory, since this is
69 * the maximum mapped by the Linux kernel during initialization.
70 */
71#define CFG_SYS_BOOTMAPSZ		(8 << 20)
72