1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Sysam AMCORE board configuration
4 *
5 * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
6 */
7
8#ifndef __AMCORE_CONFIG_H
9#define __AMCORE_CONFIG_H
10
11#define CFG_SYS_UART_PORT		0
12
13#define CFG_SYS_UART_PORT		0
14#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
15
16#define CFG_EXTRA_ENV_SETTINGS					\
17	"upgrade_uboot=loady; "					\
18		"protect off 0xffc00000 0xffc2ffff; "		\
19		"erase 0xffc00000 0xffc2ffff; "			\
20		"cp.b 0x20000 0xffc00000 ${filesize}\0"		\
21	"upgrade_kernel=loady; "				\
22		"erase 0xffc30000 0xffefffff; "			\
23		"cp.b 0x20000 0xffc30000 ${filesize}\0"		\
24	"upgrade_jffs2=loady; "					\
25		"erase 0xfff00000 0xffffffff; "			\
26		"cp.b 0x20000 0xfff00000 ${filesize}\0"
27
28#define CFG_SYS_CLK			45000000
29#define CFG_SYS_CPU_CLK		(CFG_SYS_CLK * 2)
30/* Register Base Addrs */
31#define CFG_SYS_MBAR			0x10000000
32/* Definitions for initial stack pointer and data area (in DPRAM) */
33#define CFG_SYS_INIT_RAM_ADDR	0x20000000
34/* size of internal SRAM */
35#define CFG_SYS_INIT_RAM_SIZE	0x1000
36
37#define CFG_SYS_SDRAM_BASE		0x00000000
38#define CFG_SYS_SDRAM_SIZE		0x1000000
39#define CFG_SYS_FLASH_BASE		0xffc00000
40
41/* amcore design has flash data bytes wired swapped */
42#define CFG_SYS_WRITE_SWAPPED_DATA
43
44#define LDS_BOARD_TEXT \
45	. = DEFINED(env_offset) ? env_offset : .; \
46	env/embedded.o(.text*);
47
48/* memory map space for linux boot data */
49#define CFG_SYS_BOOTMAPSZ		(8 << 20)
50
51/*
52 * Cache Configuration
53 *
54 * Special 8K version 3 core cache.
55 * This is a single unified instruction/data cache.
56 * sdram - single region - no masks
57 */
58
59#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
60					 CFG_SYS_INIT_RAM_SIZE - 8)
61#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
62					 CFG_SYS_INIT_RAM_SIZE - 4)
63#define CFG_SYS_ICACHE_INV           (CF_CACR_CINVA)
64#define CFG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
65					 CF_ACR_EN)
66#define CFG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
67					 CF_CACR_EC)
68
69/* CS0 - AMD Flash, address 0xffc00000 */
70#define	CFG_SYS_CS0_BASE		(CFG_SYS_FLASH_BASE>>16)
71/* 4MB, AA=0,V=1  C/I BIT for errata */
72#define	CFG_SYS_CS0_MASK		0x003f0001
73/* WS=10, AA=1, PS=16bit (10) */
74#define	CFG_SYS_CS0_CTRL		0x1980
75/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
76#define CFG_SYS_CS1_BASE		0x3000
77#define CFG_SYS_CS1_MASK		0x00070001
78#define CFG_SYS_CS1_CTRL		0x0100
79
80#endif  /* __AMCORE_CONFIG_H */
81